1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
26 #include <mach_apic.h>
27 #include <asm/genapic.h>
31 #include <asm/pgtable.h>
32 #include <asm/processor.h>
34 #include <asm/atomic.h>
35 #include <asm/proto.h>
36 #include <asm/sections.h>
37 #include <asm/setup.h>
41 static struct cpu_dev
*this_cpu __cpuinitdata
;
44 /* We need valid kernel segments for data and code in long mode too
45 * IRET will check the segment types kkeil 2000/10/28
46 * Also sysret mandates a special GDT layout
48 /* The TLS descriptors are currently at a different place compared to i386.
49 Hopefully nobody expects them at a fixed place (Wine?) */
50 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
51 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
52 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
53 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
54 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
55 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
56 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
59 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
60 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
61 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
62 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
63 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
65 * Segments used for calling PnP BIOS have byte granularity.
66 * They code segments and data segments have fixed 64k limits,
67 * the transfer segment sizes are set at run time.
70 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
72 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
74 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
76 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
78 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
80 * The APM segments have byte granularity and their bases
81 * are set at run time. All have 64k limits.
84 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
86 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
88 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
90 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
91 [GDT_ENTRY_PERCPU
] = { { { 0x00000000, 0x00000000 } } },
94 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
97 static int cachesize_override __cpuinitdata
= -1;
98 static int disable_x86_serial_nr __cpuinitdata
= 1;
100 static int __init
cachesize_setup(char *str
)
102 get_option(&str
, &cachesize_override
);
105 __setup("cachesize=", cachesize_setup
);
108 * Naming convention should be: <Name> [(<Codename>)]
109 * This table only is used unless init_<vendor>() below doesn't set it;
110 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
114 /* Look up CPU names by table lookup. */
115 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
117 struct cpu_model_info
*info
;
119 if (c
->x86_model
>= 16)
120 return NULL
; /* Range check */
125 info
= this_cpu
->c_models
;
127 while (info
&& info
->family
) {
128 if (info
->family
== c
->x86
)
129 return info
->model_names
[c
->x86_model
];
132 return NULL
; /* Not found */
135 static int __init
x86_fxsr_setup(char *s
)
137 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
138 setup_clear_cpu_cap(X86_FEATURE_XMM
);
141 __setup("nofxsr", x86_fxsr_setup
);
143 static int __init
x86_sep_setup(char *s
)
145 setup_clear_cpu_cap(X86_FEATURE_SEP
);
148 __setup("nosep", x86_sep_setup
);
150 /* Standard macro to see if a specific flag is changeable */
151 static inline int flag_is_changeable_p(u32 flag
)
165 : "=&r" (f1
), "=&r" (f2
)
168 return ((f1
^f2
) & flag
) != 0;
171 /* Probe for the CPUID instruction */
172 static int __cpuinit
have_cpuid_p(void)
174 return flag_is_changeable_p(X86_EFLAGS_ID
);
177 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
179 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
180 /* Disable processor serial number */
181 unsigned long lo
, hi
;
182 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
184 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
185 printk(KERN_NOTICE
"CPU serial number disabled.\n");
186 clear_cpu_cap(c
, X86_FEATURE_PN
);
188 /* Disabling the serial number may affect the cpuid level */
189 c
->cpuid_level
= cpuid_eax(0);
193 static int __init
x86_serial_nr_setup(char *s
)
195 disable_x86_serial_nr
= 0;
198 __setup("serialnumber", x86_serial_nr_setup
);
200 /* Probe for the CPUID instruction */
201 static inline int have_cpuid_p(void)
207 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
209 /* Current gdt points %fs at the "master" per-cpu area: after this,
210 * it's on the real one. */
211 void switch_to_new_gdt(void)
213 struct desc_ptr gdt_descr
;
215 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
216 gdt_descr
.size
= GDT_SIZE
- 1;
217 load_gdt(&gdt_descr
);
218 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU
) : "memory");
221 static struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
223 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
225 /* Not much we can do here... */
226 /* Check if at least it has cpuid */
227 if (c
->cpuid_level
== -1) {
228 /* No cpuid. It must be an ancient CPU */
230 strcpy(c
->x86_model_id
, "486");
231 else if (c
->x86
== 3)
232 strcpy(c
->x86_model_id
, "386");
236 static struct cpu_dev __cpuinitdata default_cpu
= {
237 .c_init
= default_init
,
238 .c_vendor
= "Unknown",
239 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
242 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
247 if (c
->extended_cpuid_level
< 0x80000004)
250 v
= (unsigned int *) c
->x86_model_id
;
251 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
252 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
253 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
254 c
->x86_model_id
[48] = 0;
256 /* Intel chips right-justify this string for some dumb reason;
257 undo that brain damage */
258 p
= q
= &c
->x86_model_id
[0];
264 while (q
<= &c
->x86_model_id
[48])
265 *q
++ = '\0'; /* Zero-pad the rest */
271 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
273 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
275 n
= c
->extended_cpuid_level
;
277 if (n
>= 0x80000005) {
278 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
279 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
280 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
281 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
284 if (n
< 0x80000006) /* Some chips just has a large L1. */
287 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
290 /* do processor-specific cache resizing */
291 if (this_cpu
->c_size_cache
)
292 l2size
= this_cpu
->c_size_cache(c
, l2size
);
294 /* Allow user to override all this if necessary. */
295 if (cachesize_override
!= -1)
296 l2size
= cachesize_override
;
299 return; /* Again, no L2 cache is possible */
301 c
->x86_cache_size
= l2size
;
303 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
307 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
310 u32 eax
, ebx
, ecx
, edx
;
311 int index_msb
, core_bits
;
313 if (!cpu_has(c
, X86_FEATURE_HT
))
316 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
319 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
321 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
323 if (smp_num_siblings
== 1) {
324 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
325 } else if (smp_num_siblings
> 1) {
327 if (smp_num_siblings
> NR_CPUS
) {
328 printk(KERN_WARNING
"CPU: Unsupported number of siblings %d",
330 smp_num_siblings
= 1;
334 index_msb
= get_count_order(smp_num_siblings
);
335 c
->phys_proc_id
= phys_pkg_id(c
->initial_apicid
, index_msb
);
338 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
340 index_msb
= get_count_order(smp_num_siblings
);
342 core_bits
= get_count_order(c
->x86_max_cores
);
344 c
->cpu_core_id
= phys_pkg_id(c
->initial_apicid
, index_msb
) &
345 ((1 << core_bits
) - 1);
349 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
350 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
352 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
358 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
360 char *v
= c
->x86_vendor_id
;
364 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
368 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
369 (cpu_devs
[i
]->c_ident
[1] &&
370 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
371 this_cpu
= cpu_devs
[i
];
372 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
379 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
380 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
383 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
384 this_cpu
= &default_cpu
;
387 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
389 /* Get vendor name */
390 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
391 (unsigned int *)&c
->x86_vendor_id
[0],
392 (unsigned int *)&c
->x86_vendor_id
[8],
393 (unsigned int *)&c
->x86_vendor_id
[4]);
396 /* Intel-defined flags: level 0x00000001 */
397 if (c
->cpuid_level
>= 0x00000001) {
398 u32 junk
, tfms
, cap0
, misc
;
399 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
400 c
->x86
= (tfms
>> 8) & 0xf;
401 c
->x86_model
= (tfms
>> 4) & 0xf;
402 c
->x86_mask
= tfms
& 0xf;
404 c
->x86
+= (tfms
>> 20) & 0xff;
406 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
407 if (cap0
& (1<<19)) {
408 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
409 c
->x86_cache_alignment
= c
->x86_clflush_size
;
414 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
419 /* Intel-defined flags: level 0x00000001 */
420 if (c
->cpuid_level
>= 0x00000001) {
421 u32 capability
, excap
;
422 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
423 c
->x86_capability
[0] = capability
;
424 c
->x86_capability
[4] = excap
;
427 /* AMD-defined flags: level 0x80000001 */
428 xlvl
= cpuid_eax(0x80000000);
429 c
->extended_cpuid_level
= xlvl
;
430 if ((xlvl
& 0xffff0000) == 0x80000000) {
431 if (xlvl
>= 0x80000001) {
432 c
->x86_capability
[1] = cpuid_edx(0x80000001);
433 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
438 * Do minimum CPU detection early.
439 * Fields really needed: vendor, cpuid_level, family, model, mask,
441 * The others are not touched to avoid unwanted side effects.
443 * WARNING: this function is only called on the BP. Don't add code here
444 * that is supposed to run on all CPUs.
446 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
448 c
->x86_clflush_size
= 32;
449 c
->x86_cache_alignment
= c
->x86_clflush_size
;
454 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
456 c
->extended_cpuid_level
= 0;
464 if (this_cpu
->c_early_init
)
465 this_cpu
->c_early_init(c
);
467 validate_pat_support(c
);
470 void __init
early_cpu_init(void)
472 struct cpu_dev
**cdev
;
475 printk("KERNEL supported cpus:\n");
476 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
477 struct cpu_dev
*cpudev
= *cdev
;
480 if (count
>= X86_VENDOR_NUM
)
482 cpu_devs
[count
] = cpudev
;
485 for (j
= 0; j
< 2; j
++) {
486 if (!cpudev
->c_ident
[j
])
488 printk(" %s %s\n", cpudev
->c_vendor
,
493 early_identify_cpu(&boot_cpu_data
);
497 * The NOPL instruction is supposed to exist on all CPUs with
498 * family >= 6, unfortunately, that's not true in practice because
499 * of early VIA chips and (more importantly) broken virtualizers that
500 * are not easy to detect. Hence, probe for it based on first
503 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
505 const u32 nopl_signature
= 0x888c53b1; /* Random number */
506 u32 has_nopl
= nopl_signature
;
508 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
511 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
513 " .section .fixup,\"ax\"\n"
520 if (has_nopl
== nopl_signature
)
521 set_cpu_cap(c
, X86_FEATURE_NOPL
);
525 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
530 c
->extended_cpuid_level
= 0;
538 if (c
->cpuid_level
>= 0x00000001) {
539 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
541 c
->apicid
= phys_pkg_id(c
->initial_apicid
, 0);
542 c
->phys_proc_id
= c
->initial_apicid
;
544 c
->apicid
= c
->initial_apicid
;
548 if (c
->extended_cpuid_level
>= 0x80000004)
549 get_model_name(c
); /* Default name */
551 init_scattered_cpuid_features(c
);
556 * This does the hard work of actually picking apart the CPU stuff...
558 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
562 c
->loops_per_jiffy
= loops_per_jiffy
;
563 c
->x86_cache_size
= -1;
564 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
565 c
->cpuid_level
= -1; /* CPUID not detected */
566 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
567 c
->x86_vendor_id
[0] = '\0'; /* Unset */
568 c
->x86_model_id
[0] = '\0'; /* Unset */
569 c
->x86_max_cores
= 1;
570 c
->x86_clflush_size
= 32;
571 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
573 if (!have_cpuid_p()) {
575 * First of all, decide if this is a 486 or higher
576 * It's a 486 if we can modify the AC flag
578 if (flag_is_changeable_p(X86_EFLAGS_AC
))
586 if (this_cpu
->c_identify
)
587 this_cpu
->c_identify(c
);
590 * Vendor-specific initialization. In this section we
591 * canonicalize the feature flags, meaning if there are
592 * features a certain CPU supports which CPUID doesn't
593 * tell us, CPUID claiming incorrect flags, or other bugs,
594 * we handle them here.
596 * At the end of this section, c->x86_capability better
597 * indicate the features this CPU genuinely supports!
599 if (this_cpu
->c_init
)
602 /* Disable the PN if appropriate */
603 squash_the_stupid_serial_number(c
);
606 * The vendor-specific functions might have changed features. Now
607 * we do "generic changes."
610 /* If the model name is still unset, do table lookup. */
611 if (!c
->x86_model_id
[0]) {
613 p
= table_lookup_model(c
);
615 strcpy(c
->x86_model_id
, p
);
618 sprintf(c
->x86_model_id
, "%02x/%02x",
619 c
->x86
, c
->x86_model
);
623 * On SMP, boot_cpu_data holds the common feature set between
624 * all CPUs; so make sure that we indicate which features are
625 * common between the CPUs. The first time this routine gets
626 * executed, c == &boot_cpu_data.
628 if (c
!= &boot_cpu_data
) {
629 /* AND the already accumulated flags with these */
630 for (i
= 0; i
< NCAPINTS
; i
++)
631 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
634 /* Clear all flags overriden by options */
635 for (i
= 0; i
< NCAPINTS
; i
++)
636 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
638 /* Init Machine Check Exception if available. */
641 select_idle_routine(c
);
644 void __init
identify_boot_cpu(void)
646 identify_cpu(&boot_cpu_data
);
651 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
653 BUG_ON(c
== &boot_cpu_data
);
664 static struct msr_range msr_range_array
[] __cpuinitdata
= {
665 { 0x00000000, 0x00000418},
666 { 0xc0000000, 0xc000040b},
667 { 0xc0010000, 0xc0010142},
668 { 0xc0011000, 0xc001103b},
671 static void __cpuinit
print_cpu_msr(void)
676 unsigned index_min
, index_max
;
678 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
679 index_min
= msr_range_array
[i
].min
;
680 index_max
= msr_range_array
[i
].max
;
681 for (index
= index_min
; index
< index_max
; index
++) {
682 if (rdmsrl_amd_safe(index
, &val
))
684 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
689 static int show_msr __cpuinitdata
;
690 static __init
int setup_show_msr(char *arg
)
694 get_option(&arg
, &num
);
700 __setup("show_msr=", setup_show_msr
);
702 static __init
int setup_noclflush(char *arg
)
704 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
707 __setup("noclflush", setup_noclflush
);
709 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
713 if (c
->x86_vendor
< X86_VENDOR_NUM
)
714 vendor
= this_cpu
->c_vendor
;
715 else if (c
->cpuid_level
>= 0)
716 vendor
= c
->x86_vendor_id
;
718 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
719 printk(KERN_CONT
"%s ", vendor
);
721 if (c
->x86_model_id
[0])
722 printk(KERN_CONT
"%s", c
->x86_model_id
);
724 printk(KERN_CONT
"%d86", c
->x86
);
726 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
727 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
729 printk(KERN_CONT
"\n");
732 if (c
->cpu_index
< show_msr
)
740 static __init
int setup_disablecpuid(char *arg
)
743 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
744 setup_clear_cpu_cap(bit
);
749 __setup("clearcpuid=", setup_disablecpuid
);
751 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
754 struct x8664_pda
**_cpu_pda __read_mostly
;
755 EXPORT_SYMBOL(_cpu_pda
);
757 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
759 char boot_cpu_stack
[IRQSTACKSIZE
] __page_aligned_bss
;
761 unsigned long __supported_pte_mask __read_mostly
= ~0UL;
762 EXPORT_SYMBOL_GPL(__supported_pte_mask
);
764 static int do_not_nx __cpuinitdata
;
767 Control non executable mappings for 64bit processes.
772 static int __init
nonx_setup(char *str
)
776 if (!strncmp(str
, "on", 2)) {
777 __supported_pte_mask
|= _PAGE_NX
;
779 } else if (!strncmp(str
, "off", 3)) {
781 __supported_pte_mask
&= ~_PAGE_NX
;
785 early_param("noexec", nonx_setup
);
787 int force_personality32
;
790 Control non executable heap for 32bit processes.
791 To control the stack too use noexec=off
793 on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
794 off PROT_READ implies PROT_EXEC
796 static int __init
nonx32_setup(char *str
)
798 if (!strcmp(str
, "on"))
799 force_personality32
&= ~READ_IMPLIES_EXEC
;
800 else if (!strcmp(str
, "off"))
801 force_personality32
|= READ_IMPLIES_EXEC
;
804 __setup("noexec32=", nonx32_setup
);
806 void pda_init(int cpu
)
808 struct x8664_pda
*pda
= cpu_pda(cpu
);
810 /* Setup up data that may be needed in __get_free_pages early */
813 /* Memory clobbers used to order PDA accessed */
815 wrmsrl(MSR_GS_BASE
, pda
);
818 pda
->cpunumber
= cpu
;
820 pda
->kernelstack
= (unsigned long)stack_thread_info() -
821 PDA_STACKOFFSET
+ THREAD_SIZE
;
822 pda
->active_mm
= &init_mm
;
826 /* others are initialized in smpboot.c */
827 pda
->pcurrent
= &init_task
;
828 pda
->irqstackptr
= boot_cpu_stack
;
829 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
831 if (!pda
->irqstackptr
) {
832 pda
->irqstackptr
= (char *)
833 __get_free_pages(GFP_ATOMIC
, IRQSTACK_ORDER
);
834 if (!pda
->irqstackptr
)
835 panic("cannot allocate irqstack for cpu %d",
837 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
840 if (pda
->nodenumber
== 0 && cpu_to_node(cpu
) != NUMA_NO_NODE
)
841 pda
->nodenumber
= cpu_to_node(cpu
);
845 char boot_exception_stacks
[(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+
846 DEBUG_STKSZ
] __page_aligned_bss
;
848 extern asmlinkage
void ignore_sysret(void);
850 /* May not be marked __init: used by software suspend */
851 void syscall_init(void)
854 * LSTAR and STAR live in a bit strange symbiosis.
855 * They both write to the same internal register. STAR allows to
856 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
858 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
859 wrmsrl(MSR_LSTAR
, system_call
);
860 wrmsrl(MSR_CSTAR
, ignore_sysret
);
862 #ifdef CONFIG_IA32_EMULATION
863 syscall32_cpu_init();
866 /* Flags to clear on syscall */
867 wrmsrl(MSR_SYSCALL_MASK
,
868 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
871 void __cpuinit
check_efer(void)
875 rdmsrl(MSR_EFER
, efer
);
876 if (!(efer
& EFER_NX
) || do_not_nx
)
877 __supported_pte_mask
&= ~_PAGE_NX
;
880 unsigned long kernel_eflags
;
883 * Copies of the original ist values from the tss are only accessed during
884 * debugging, no special alignment required.
886 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
890 /* Make sure %fs is initialized properly in idle threads */
891 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
893 memset(regs
, 0, sizeof(struct pt_regs
));
894 regs
->fs
= __KERNEL_PERCPU
;
900 * cpu_init() initializes state that is per-CPU. Some data is already
901 * initialized (naturally) in the bootstrap process, such as the GDT
902 * and IDT. We reload them nevertheless, this function acts as a
903 * 'CPU state barrier', nothing should get across.
905 void __cpuinit
cpu_init(void)
907 int cpu
= smp_processor_id();
908 struct task_struct
*curr
= current
;
909 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
910 struct thread_struct
*thread
= &curr
->thread
;
912 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
913 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
914 for (;;) local_irq_enable();
917 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
919 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
920 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
922 load_idt(&idt_descr
);
926 * Set up and load the per-CPU TSS and LDT
928 atomic_inc(&init_mm
.mm_count
);
929 curr
->active_mm
= &init_mm
;
932 enter_lazy_tlb(&init_mm
, curr
);
935 set_tss_desc(cpu
, t
);
937 load_LDT(&init_mm
.context
);
939 #ifdef CONFIG_DOUBLEFAULT
940 /* Set up doublefault TSS pointer in the GDT */
941 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
945 asm volatile ("mov %0, %%gs" : : "r" (0));
947 /* Clear all 6 debug registers: */
956 * Force FPU initialization:
959 current_thread_info()->status
= TS_XSAVE
;
961 current_thread_info()->status
= 0;
963 mxcsr_feature_mask_init();
966 * Boot processor to setup the FP and extended state context info.
968 if (!smp_processor_id())
969 init_thread_xstate();
974 #ifdef CONFIG_HOTPLUG_CPU
975 void __cpuinit
cpu_uninit(void)
977 int cpu
= raw_smp_processor_id();
978 cpu_clear(cpu
, cpu_initialized
);
981 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
982 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;