1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/init.h>
18 #include <linux/kprobes.h>
19 #include <linux/kgdb.h>
20 #include <linux/smp.h>
22 #include <linux/syscore_ops.h>
24 #include <asm/stackprotector.h>
25 #include <asm/perf_event.h>
26 #include <asm/mmu_context.h>
27 #include <asm/archrandom.h>
28 #include <asm/hypervisor.h>
29 #include <asm/processor.h>
30 #include <asm/tlbflush.h>
31 #include <asm/debugreg.h>
32 #include <asm/sections.h>
33 #include <asm/vsyscall.h>
34 #include <linux/topology.h>
35 #include <linux/cpumask.h>
36 #include <asm/pgtable.h>
37 #include <linux/atomic.h>
38 #include <asm/proto.h>
39 #include <asm/setup.h>
42 #include <asm/fpu/internal.h>
44 #include <asm/hwcap2.h>
45 #include <linux/numa.h>
52 #include <asm/microcode.h>
53 #include <asm/microcode_intel.h>
54 #include <asm/intel-family.h>
55 #include <asm/cpu_device_id.h>
57 #ifdef CONFIG_X86_LOCAL_APIC
58 #include <asm/uv/uv.h>
63 u32 elf_hwcap2 __read_mostly
;
65 /* all of these masks are initialized in setup_cpu_local_masks() */
66 cpumask_var_t cpu_initialized_mask
;
67 cpumask_var_t cpu_callout_mask
;
68 cpumask_var_t cpu_callin_mask
;
70 /* representing cpus for which sibling maps can be computed */
71 cpumask_var_t cpu_sibling_setup_mask
;
73 /* Number of siblings per CPU package */
74 int smp_num_siblings
= 1;
75 EXPORT_SYMBOL(smp_num_siblings
);
77 /* Last level cache ID of each logical CPU */
78 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
80 /* correctly size the local cpu masks */
81 void __init
setup_cpu_local_masks(void)
83 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
84 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
85 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
86 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
89 static void default_init(struct cpuinfo_x86
*c
)
92 cpu_detect_cache_sizes(c
);
94 /* Not much we can do here... */
95 /* Check if at least it has cpuid */
96 if (c
->cpuid_level
== -1) {
97 /* No cpuid. It must be an ancient CPU */
99 strcpy(c
->x86_model_id
, "486");
100 else if (c
->x86
== 3)
101 strcpy(c
->x86_model_id
, "386");
106 static const struct cpu_dev default_cpu
= {
107 .c_init
= default_init
,
108 .c_vendor
= "Unknown",
109 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
112 static const struct cpu_dev
*this_cpu
= &default_cpu
;
114 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
117 * We need valid kernel segments for data and code in long mode too
118 * IRET will check the segment types kkeil 2000/10/28
119 * Also sysret mandates a special GDT layout
121 * TLS descriptors are currently at a different place compared to i386.
122 * Hopefully nobody expects them at a fixed place (Wine?)
124 [GDT_ENTRY_KERNEL32_CS
] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
126 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER32_CS
] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
131 [GDT_ENTRY_KERNEL_CS
] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
132 [GDT_ENTRY_KERNEL_DS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_CS
] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
134 [GDT_ENTRY_DEFAULT_USER_DS
] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
136 * Segments used for calling PnP BIOS have byte granularity.
137 * They code segments and data segments have fixed 64k limits,
138 * the transfer segment sizes are set at run time.
141 [GDT_ENTRY_PNPBIOS_CS32
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
143 [GDT_ENTRY_PNPBIOS_CS16
] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
145 [GDT_ENTRY_PNPBIOS_DS
] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
147 [GDT_ENTRY_PNPBIOS_TS1
] = GDT_ENTRY_INIT(0x0092, 0, 0),
149 [GDT_ENTRY_PNPBIOS_TS2
] = GDT_ENTRY_INIT(0x0092, 0, 0),
151 * The APM segments have byte granularity and their bases
152 * are set at run time. All have 64k limits.
155 [GDT_ENTRY_APMBIOS_BASE
] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
157 [GDT_ENTRY_APMBIOS_BASE
+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
159 [GDT_ENTRY_APMBIOS_BASE
+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
161 [GDT_ENTRY_ESPFIX_SS
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 [GDT_ENTRY_PERCPU
] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
163 GDT_STACK_CANARY_INIT
166 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
168 static int __init
x86_mpx_setup(char *s
)
170 /* require an exact match without trailing characters */
174 /* do not emit a message if the feature is not present */
175 if (!boot_cpu_has(X86_FEATURE_MPX
))
178 setup_clear_cpu_cap(X86_FEATURE_MPX
);
179 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
182 __setup("nompx", x86_mpx_setup
);
185 static int __init
x86_nopcid_setup(char *s
)
187 /* nopcid doesn't accept parameters */
191 /* do not emit a message if the feature is not present */
192 if (!boot_cpu_has(X86_FEATURE_PCID
))
195 setup_clear_cpu_cap(X86_FEATURE_PCID
);
196 pr_info("nopcid: PCID feature disabled\n");
199 early_param("nopcid", x86_nopcid_setup
);
202 static int __init
x86_noinvpcid_setup(char *s
)
204 /* noinvpcid doesn't accept parameters */
208 /* do not emit a message if the feature is not present */
209 if (!boot_cpu_has(X86_FEATURE_INVPCID
))
212 setup_clear_cpu_cap(X86_FEATURE_INVPCID
);
213 pr_info("noinvpcid: INVPCID feature disabled\n");
216 early_param("noinvpcid", x86_noinvpcid_setup
);
219 static int cachesize_override
= -1;
220 static int disable_x86_serial_nr
= 1;
222 static int __init
cachesize_setup(char *str
)
224 get_option(&str
, &cachesize_override
);
227 __setup("cachesize=", cachesize_setup
);
229 static int __init
x86_sep_setup(char *s
)
231 setup_clear_cpu_cap(X86_FEATURE_SEP
);
234 __setup("nosep", x86_sep_setup
);
236 /* Standard macro to see if a specific flag is changeable */
237 static inline int flag_is_changeable_p(u32 flag
)
242 * Cyrix and IDT cpus allow disabling of CPUID
243 * so the code below may return different results
244 * when it is executed before and after enabling
245 * the CPUID. Add "volatile" to not allow gcc to
246 * optimize the subsequent calls to this function.
248 asm volatile ("pushfl \n\t"
259 : "=&r" (f1
), "=&r" (f2
)
262 return ((f1
^f2
) & flag
) != 0;
265 /* Probe for the CPUID instruction */
266 int have_cpuid_p(void)
268 return flag_is_changeable_p(X86_EFLAGS_ID
);
271 static void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
273 unsigned long lo
, hi
;
275 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
278 /* Disable processor serial number: */
280 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
282 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
284 pr_notice("CPU serial number disabled.\n");
285 clear_cpu_cap(c
, X86_FEATURE_PN
);
287 /* Disabling the serial number may affect the cpuid level */
288 c
->cpuid_level
= cpuid_eax(0);
291 static int __init
x86_serial_nr_setup(char *s
)
293 disable_x86_serial_nr
= 0;
296 __setup("serialnumber", x86_serial_nr_setup
);
298 static inline int flag_is_changeable_p(u32 flag
)
302 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
307 static __init
int setup_disable_smep(char *arg
)
309 setup_clear_cpu_cap(X86_FEATURE_SMEP
);
310 /* Check for things that depend on SMEP being enabled: */
311 check_mpx_erratum(&boot_cpu_data
);
314 __setup("nosmep", setup_disable_smep
);
316 static __always_inline
void setup_smep(struct cpuinfo_x86
*c
)
318 if (cpu_has(c
, X86_FEATURE_SMEP
))
319 cr4_set_bits(X86_CR4_SMEP
);
322 static __init
int setup_disable_smap(char *arg
)
324 setup_clear_cpu_cap(X86_FEATURE_SMAP
);
327 __setup("nosmap", setup_disable_smap
);
329 static __always_inline
void setup_smap(struct cpuinfo_x86
*c
)
331 unsigned long eflags
= native_save_fl();
333 /* This should have been cleared long ago */
334 BUG_ON(eflags
& X86_EFLAGS_AC
);
336 if (cpu_has(c
, X86_FEATURE_SMAP
)) {
337 #ifdef CONFIG_X86_SMAP
338 cr4_set_bits(X86_CR4_SMAP
);
340 cr4_clear_bits(X86_CR4_SMAP
);
345 static __always_inline
void setup_umip(struct cpuinfo_x86
*c
)
347 /* Check the boot processor, plus build option for UMIP. */
348 if (!cpu_feature_enabled(X86_FEATURE_UMIP
))
351 /* Check the current processor's cpuid bits. */
352 if (!cpu_has(c
, X86_FEATURE_UMIP
))
355 cr4_set_bits(X86_CR4_UMIP
);
357 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
363 * Make sure UMIP is disabled in case it was enabled in a
364 * previous boot (e.g., via kexec).
366 cr4_clear_bits(X86_CR4_UMIP
);
369 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning
);
370 static unsigned long cr4_pinned_bits __ro_after_init
;
372 void native_write_cr0(unsigned long val
)
374 unsigned long bits_missing
= 0;
377 asm volatile("mov %0,%%cr0": "+r" (val
), "+m" (__force_order
));
379 if (static_branch_likely(&cr_pinning
)) {
380 if (unlikely((val
& X86_CR0_WP
) != X86_CR0_WP
)) {
381 bits_missing
= X86_CR0_WP
;
385 /* Warn after we've set the missing bits. */
386 WARN_ONCE(bits_missing
, "CR0 WP bit went missing!?\n");
389 EXPORT_SYMBOL(native_write_cr0
);
391 void native_write_cr4(unsigned long val
)
393 unsigned long bits_missing
= 0;
396 asm volatile("mov %0,%%cr4": "+r" (val
), "+m" (cr4_pinned_bits
));
398 if (static_branch_likely(&cr_pinning
)) {
399 if (unlikely((val
& cr4_pinned_bits
) != cr4_pinned_bits
)) {
400 bits_missing
= ~val
& cr4_pinned_bits
;
404 /* Warn after we've set the missing bits. */
405 WARN_ONCE(bits_missing
, "CR4 bits went missing: %lx!?\n",
409 EXPORT_SYMBOL(native_write_cr4
);
413 unsigned long cr4
= __read_cr4();
415 if (boot_cpu_has(X86_FEATURE_PCID
))
416 cr4
|= X86_CR4_PCIDE
;
417 if (static_branch_likely(&cr_pinning
))
418 cr4
|= cr4_pinned_bits
;
422 /* Initialize cr4 shadow for this CPU. */
423 this_cpu_write(cpu_tlbstate
.cr4
, cr4
);
427 * Once CPU feature detection is finished (and boot params have been
428 * parsed), record any of the sensitive CR bits that are set, and
431 static void __init
setup_cr_pinning(void)
435 mask
= (X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_UMIP
);
436 cr4_pinned_bits
= this_cpu_read(cpu_tlbstate
.cr4
) & mask
;
437 static_key_enable(&cr_pinning
.key
);
441 * Protection Keys are not available in 32-bit mode.
443 static bool pku_disabled
;
445 static __always_inline
void setup_pku(struct cpuinfo_x86
*c
)
447 struct pkru_state
*pk
;
449 /* check the boot processor, plus compile options for PKU: */
450 if (!cpu_feature_enabled(X86_FEATURE_PKU
))
452 /* checks the actual processor's cpuid bits: */
453 if (!cpu_has(c
, X86_FEATURE_PKU
))
458 cr4_set_bits(X86_CR4_PKE
);
459 pk
= get_xsave_addr(&init_fpstate
.xsave
, XFEATURE_PKRU
);
461 pk
->pkru
= init_pkru_value
;
463 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
464 * cpuid bit to be set. We need to ensure that we
465 * update that bit in this CPU's "cpu_info".
470 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
471 static __init
int setup_disable_pku(char *arg
)
474 * Do not clear the X86_FEATURE_PKU bit. All of the
475 * runtime checks are against OSPKE so clearing the
478 * This way, we will see "pku" in cpuinfo, but not
479 * "ospke", which is exactly what we want. It shows
480 * that the CPU has PKU, but the OS has not enabled it.
481 * This happens to be exactly how a system would look
482 * if we disabled the config option.
484 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
488 __setup("nopku", setup_disable_pku
);
489 #endif /* CONFIG_X86_64 */
492 * Some CPU features depend on higher CPUID levels, which may not always
493 * be available due to CPUID level capping or broken virtualization
494 * software. Add those features to this table to auto-disable them.
496 struct cpuid_dependent_feature
{
501 static const struct cpuid_dependent_feature
502 cpuid_dependent_features
[] = {
503 { X86_FEATURE_MWAIT
, 0x00000005 },
504 { X86_FEATURE_DCA
, 0x00000009 },
505 { X86_FEATURE_XSAVE
, 0x0000000d },
509 static void filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
511 const struct cpuid_dependent_feature
*df
;
513 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
515 if (!cpu_has(c
, df
->feature
))
518 * Note: cpuid_level is set to -1 if unavailable, but
519 * extended_extended_level is set to 0 if unavailable
520 * and the legitimate extended levels are all negative
521 * when signed; hence the weird messing around with
524 if (!((s32
)df
->level
< 0 ?
525 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
526 (s32
)df
->level
> (s32
)c
->cpuid_level
))
529 clear_cpu_cap(c
, df
->feature
);
533 pr_warn("CPU: CPU feature " X86_CAP_FMT
" disabled, no CPUID level 0x%x\n",
534 x86_cap_flag(df
->feature
), df
->level
);
539 * Naming convention should be: <Name> [(<Codename>)]
540 * This table only is used unless init_<vendor>() below doesn't set it;
541 * in particular, if CPUID levels 0x80000002..4 are supported, this
545 /* Look up CPU names by table lookup. */
546 static const char *table_lookup_model(struct cpuinfo_x86
*c
)
549 const struct legacy_cpu_model_info
*info
;
551 if (c
->x86_model
>= 16)
552 return NULL
; /* Range check */
557 info
= this_cpu
->legacy_models
;
559 while (info
->family
) {
560 if (info
->family
== c
->x86
)
561 return info
->model_names
[c
->x86_model
];
565 return NULL
; /* Not found */
568 __u32 cpu_caps_cleared
[NCAPINTS
+ NBUGINTS
];
569 __u32 cpu_caps_set
[NCAPINTS
+ NBUGINTS
];
571 void load_percpu_segment(int cpu
)
574 loadsegment(fs
, __KERNEL_PERCPU
);
576 __loadsegment_simple(gs
, 0);
577 wrmsrl(MSR_GS_BASE
, cpu_kernelmode_gs_base(cpu
));
579 load_stack_canary_segment();
583 /* The 32-bit entry code needs to find cpu_entry_area. */
584 DEFINE_PER_CPU(struct cpu_entry_area
*, cpu_entry_area
);
587 /* Load the original GDT from the per-cpu structure */
588 void load_direct_gdt(int cpu
)
590 struct desc_ptr gdt_descr
;
592 gdt_descr
.address
= (long)get_cpu_gdt_rw(cpu
);
593 gdt_descr
.size
= GDT_SIZE
- 1;
594 load_gdt(&gdt_descr
);
596 EXPORT_SYMBOL_GPL(load_direct_gdt
);
598 /* Load a fixmap remapping of the per-cpu GDT */
599 void load_fixmap_gdt(int cpu
)
601 struct desc_ptr gdt_descr
;
603 gdt_descr
.address
= (long)get_cpu_gdt_ro(cpu
);
604 gdt_descr
.size
= GDT_SIZE
- 1;
605 load_gdt(&gdt_descr
);
607 EXPORT_SYMBOL_GPL(load_fixmap_gdt
);
610 * Current gdt points %fs at the "master" per-cpu area: after this,
611 * it's on the real one.
613 void switch_to_new_gdt(int cpu
)
615 /* Load the original GDT */
616 load_direct_gdt(cpu
);
617 /* Reload the per-cpu base */
618 load_percpu_segment(cpu
);
621 static const struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
623 static void get_model_name(struct cpuinfo_x86
*c
)
628 if (c
->extended_cpuid_level
< 0x80000004)
631 v
= (unsigned int *)c
->x86_model_id
;
632 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
633 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
634 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
635 c
->x86_model_id
[48] = 0;
637 /* Trim whitespace */
638 p
= q
= s
= &c
->x86_model_id
[0];
644 /* Note the last non-whitespace index */
654 void detect_num_cpu_cores(struct cpuinfo_x86
*c
)
656 unsigned int eax
, ebx
, ecx
, edx
;
658 c
->x86_max_cores
= 1;
659 if (!IS_ENABLED(CONFIG_SMP
) || c
->cpuid_level
< 4)
662 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
664 c
->x86_max_cores
= (eax
>> 26) + 1;
667 void cpu_detect_cache_sizes(struct cpuinfo_x86
*c
)
669 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
671 n
= c
->extended_cpuid_level
;
673 if (n
>= 0x80000005) {
674 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
675 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
677 /* On K8 L1 TLB is inclusive, so don't count it */
682 if (n
< 0x80000006) /* Some chips just has a large L1. */
685 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
689 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
691 /* do processor-specific cache resizing */
692 if (this_cpu
->legacy_cache_size
)
693 l2size
= this_cpu
->legacy_cache_size(c
, l2size
);
695 /* Allow user to override all this if necessary. */
696 if (cachesize_override
!= -1)
697 l2size
= cachesize_override
;
700 return; /* Again, no L2 cache is possible */
703 c
->x86_cache_size
= l2size
;
706 u16 __read_mostly tlb_lli_4k
[NR_INFO
];
707 u16 __read_mostly tlb_lli_2m
[NR_INFO
];
708 u16 __read_mostly tlb_lli_4m
[NR_INFO
];
709 u16 __read_mostly tlb_lld_4k
[NR_INFO
];
710 u16 __read_mostly tlb_lld_2m
[NR_INFO
];
711 u16 __read_mostly tlb_lld_4m
[NR_INFO
];
712 u16 __read_mostly tlb_lld_1g
[NR_INFO
];
714 static void cpu_detect_tlb(struct cpuinfo_x86
*c
)
716 if (this_cpu
->c_detect_tlb
)
717 this_cpu
->c_detect_tlb(c
);
719 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
720 tlb_lli_4k
[ENTRIES
], tlb_lli_2m
[ENTRIES
],
721 tlb_lli_4m
[ENTRIES
]);
723 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
724 tlb_lld_4k
[ENTRIES
], tlb_lld_2m
[ENTRIES
],
725 tlb_lld_4m
[ENTRIES
], tlb_lld_1g
[ENTRIES
]);
728 int detect_ht_early(struct cpuinfo_x86
*c
)
731 u32 eax
, ebx
, ecx
, edx
;
733 if (!cpu_has(c
, X86_FEATURE_HT
))
736 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
739 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
742 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
744 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
745 if (smp_num_siblings
== 1)
746 pr_info_once("CPU0: Hyper-Threading is disabled\n");
751 void detect_ht(struct cpuinfo_x86
*c
)
754 int index_msb
, core_bits
;
756 if (detect_ht_early(c
) < 0)
759 index_msb
= get_count_order(smp_num_siblings
);
760 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
762 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
764 index_msb
= get_count_order(smp_num_siblings
);
766 core_bits
= get_count_order(c
->x86_max_cores
);
768 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
769 ((1 << core_bits
) - 1);
773 static void get_cpu_vendor(struct cpuinfo_x86
*c
)
775 char *v
= c
->x86_vendor_id
;
778 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
782 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
783 (cpu_devs
[i
]->c_ident
[1] &&
784 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
786 this_cpu
= cpu_devs
[i
];
787 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
792 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
793 "CPU: Your system may be unstable.\n", v
);
795 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
796 this_cpu
= &default_cpu
;
799 void cpu_detect(struct cpuinfo_x86
*c
)
801 /* Get vendor name */
802 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
803 (unsigned int *)&c
->x86_vendor_id
[0],
804 (unsigned int *)&c
->x86_vendor_id
[8],
805 (unsigned int *)&c
->x86_vendor_id
[4]);
808 /* Intel-defined flags: level 0x00000001 */
809 if (c
->cpuid_level
>= 0x00000001) {
810 u32 junk
, tfms
, cap0
, misc
;
812 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
813 c
->x86
= x86_family(tfms
);
814 c
->x86_model
= x86_model(tfms
);
815 c
->x86_stepping
= x86_stepping(tfms
);
817 if (cap0
& (1<<19)) {
818 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
819 c
->x86_cache_alignment
= c
->x86_clflush_size
;
824 static void apply_forced_caps(struct cpuinfo_x86
*c
)
828 for (i
= 0; i
< NCAPINTS
+ NBUGINTS
; i
++) {
829 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
830 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
834 static void init_speculation_control(struct cpuinfo_x86
*c
)
837 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
838 * and they also have a different bit for STIBP support. Also,
839 * a hypervisor might have set the individual AMD bits even on
840 * Intel CPUs, for finer-grained selection of what's available.
842 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL
)) {
843 set_cpu_cap(c
, X86_FEATURE_IBRS
);
844 set_cpu_cap(c
, X86_FEATURE_IBPB
);
845 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
848 if (cpu_has(c
, X86_FEATURE_INTEL_STIBP
))
849 set_cpu_cap(c
, X86_FEATURE_STIBP
);
851 if (cpu_has(c
, X86_FEATURE_SPEC_CTRL_SSBD
) ||
852 cpu_has(c
, X86_FEATURE_VIRT_SSBD
))
853 set_cpu_cap(c
, X86_FEATURE_SSBD
);
855 if (cpu_has(c
, X86_FEATURE_AMD_IBRS
)) {
856 set_cpu_cap(c
, X86_FEATURE_IBRS
);
857 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
860 if (cpu_has(c
, X86_FEATURE_AMD_IBPB
))
861 set_cpu_cap(c
, X86_FEATURE_IBPB
);
863 if (cpu_has(c
, X86_FEATURE_AMD_STIBP
)) {
864 set_cpu_cap(c
, X86_FEATURE_STIBP
);
865 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
868 if (cpu_has(c
, X86_FEATURE_AMD_SSBD
)) {
869 set_cpu_cap(c
, X86_FEATURE_SSBD
);
870 set_cpu_cap(c
, X86_FEATURE_MSR_SPEC_CTRL
);
871 clear_cpu_cap(c
, X86_FEATURE_VIRT_SSBD
);
875 static void init_cqm(struct cpuinfo_x86
*c
)
877 if (!cpu_has(c
, X86_FEATURE_CQM_LLC
)) {
878 c
->x86_cache_max_rmid
= -1;
879 c
->x86_cache_occ_scale
= -1;
883 /* will be overridden if occupancy monitoring exists */
884 c
->x86_cache_max_rmid
= cpuid_ebx(0xf);
886 if (cpu_has(c
, X86_FEATURE_CQM_OCCUP_LLC
) ||
887 cpu_has(c
, X86_FEATURE_CQM_MBM_TOTAL
) ||
888 cpu_has(c
, X86_FEATURE_CQM_MBM_LOCAL
)) {
889 u32 eax
, ebx
, ecx
, edx
;
891 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
892 cpuid_count(0xf, 1, &eax
, &ebx
, &ecx
, &edx
);
894 c
->x86_cache_max_rmid
= ecx
;
895 c
->x86_cache_occ_scale
= ebx
;
899 void get_cpu_cap(struct cpuinfo_x86
*c
)
901 u32 eax
, ebx
, ecx
, edx
;
903 /* Intel-defined flags: level 0x00000001 */
904 if (c
->cpuid_level
>= 0x00000001) {
905 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
907 c
->x86_capability
[CPUID_1_ECX
] = ecx
;
908 c
->x86_capability
[CPUID_1_EDX
] = edx
;
911 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
912 if (c
->cpuid_level
>= 0x00000006)
913 c
->x86_capability
[CPUID_6_EAX
] = cpuid_eax(0x00000006);
915 /* Additional Intel-defined flags: level 0x00000007 */
916 if (c
->cpuid_level
>= 0x00000007) {
917 cpuid_count(0x00000007, 0, &eax
, &ebx
, &ecx
, &edx
);
918 c
->x86_capability
[CPUID_7_0_EBX
] = ebx
;
919 c
->x86_capability
[CPUID_7_ECX
] = ecx
;
920 c
->x86_capability
[CPUID_7_EDX
] = edx
;
922 /* Check valid sub-leaf index before accessing it */
924 cpuid_count(0x00000007, 1, &eax
, &ebx
, &ecx
, &edx
);
925 c
->x86_capability
[CPUID_7_1_EAX
] = eax
;
929 /* Extended state features: level 0x0000000d */
930 if (c
->cpuid_level
>= 0x0000000d) {
931 cpuid_count(0x0000000d, 1, &eax
, &ebx
, &ecx
, &edx
);
933 c
->x86_capability
[CPUID_D_1_EAX
] = eax
;
936 /* AMD-defined flags: level 0x80000001 */
937 eax
= cpuid_eax(0x80000000);
938 c
->extended_cpuid_level
= eax
;
940 if ((eax
& 0xffff0000) == 0x80000000) {
941 if (eax
>= 0x80000001) {
942 cpuid(0x80000001, &eax
, &ebx
, &ecx
, &edx
);
944 c
->x86_capability
[CPUID_8000_0001_ECX
] = ecx
;
945 c
->x86_capability
[CPUID_8000_0001_EDX
] = edx
;
949 if (c
->extended_cpuid_level
>= 0x80000007) {
950 cpuid(0x80000007, &eax
, &ebx
, &ecx
, &edx
);
952 c
->x86_capability
[CPUID_8000_0007_EBX
] = ebx
;
956 if (c
->extended_cpuid_level
>= 0x80000008) {
957 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
958 c
->x86_capability
[CPUID_8000_0008_EBX
] = ebx
;
961 if (c
->extended_cpuid_level
>= 0x8000000a)
962 c
->x86_capability
[CPUID_8000_000A_EDX
] = cpuid_edx(0x8000000a);
964 init_scattered_cpuid_features(c
);
965 init_speculation_control(c
);
969 * Clear/Set all flags overridden by options, after probe.
970 * This needs to happen each time we re-probe, which may happen
971 * several times during CPU initialization.
973 apply_forced_caps(c
);
976 void get_cpu_address_sizes(struct cpuinfo_x86
*c
)
978 u32 eax
, ebx
, ecx
, edx
;
980 if (c
->extended_cpuid_level
>= 0x80000008) {
981 cpuid(0x80000008, &eax
, &ebx
, &ecx
, &edx
);
983 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
984 c
->x86_phys_bits
= eax
& 0xff;
987 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
988 c
->x86_phys_bits
= 36;
990 c
->x86_cache_bits
= c
->x86_phys_bits
;
993 static void identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
999 * First of all, decide if this is a 486 or higher
1000 * It's a 486 if we can modify the AC flag
1002 if (flag_is_changeable_p(X86_EFLAGS_AC
))
1007 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
1008 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
1009 c
->x86_vendor_id
[0] = 0;
1010 cpu_devs
[i
]->c_identify(c
);
1011 if (c
->x86_vendor_id
[0]) {
1019 #define NO_SPECULATION BIT(0)
1020 #define NO_MELTDOWN BIT(1)
1021 #define NO_SSB BIT(2)
1022 #define NO_L1TF BIT(3)
1023 #define NO_MDS BIT(4)
1024 #define MSBDS_ONLY BIT(5)
1026 #define VULNWL(_vendor, _family, _model, _whitelist) \
1027 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
1029 #define VULNWL_INTEL(model, whitelist) \
1030 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1032 #define VULNWL_AMD(family, whitelist) \
1033 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1035 #define VULNWL_HYGON(family, whitelist) \
1036 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1038 static const __initconst
struct x86_cpu_id cpu_vuln_whitelist
[] = {
1039 VULNWL(ANY
, 4, X86_MODEL_ANY
, NO_SPECULATION
),
1040 VULNWL(CENTAUR
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1041 VULNWL(INTEL
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1042 VULNWL(NSC
, 5, X86_MODEL_ANY
, NO_SPECULATION
),
1044 /* Intel Family 6 */
1045 VULNWL_INTEL(ATOM_SALTWELL
, NO_SPECULATION
),
1046 VULNWL_INTEL(ATOM_SALTWELL_TABLET
, NO_SPECULATION
),
1047 VULNWL_INTEL(ATOM_SALTWELL_MID
, NO_SPECULATION
),
1048 VULNWL_INTEL(ATOM_BONNELL
, NO_SPECULATION
),
1049 VULNWL_INTEL(ATOM_BONNELL_MID
, NO_SPECULATION
),
1051 VULNWL_INTEL(ATOM_SILVERMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
),
1052 VULNWL_INTEL(ATOM_SILVERMONT_X
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
),
1053 VULNWL_INTEL(ATOM_SILVERMONT_MID
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
),
1054 VULNWL_INTEL(ATOM_AIRMONT
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
),
1055 VULNWL_INTEL(XEON_PHI_KNL
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
),
1056 VULNWL_INTEL(XEON_PHI_KNM
, NO_SSB
| NO_L1TF
| MSBDS_ONLY
),
1058 VULNWL_INTEL(CORE_YONAH
, NO_SSB
),
1060 VULNWL_INTEL(ATOM_AIRMONT_MID
, NO_L1TF
| MSBDS_ONLY
),
1062 VULNWL_INTEL(ATOM_GOLDMONT
, NO_MDS
| NO_L1TF
),
1063 VULNWL_INTEL(ATOM_GOLDMONT_X
, NO_MDS
| NO_L1TF
),
1064 VULNWL_INTEL(ATOM_GOLDMONT_PLUS
, NO_MDS
| NO_L1TF
),
1066 /* AMD Family 0xf - 0x12 */
1067 VULNWL_AMD(0x0f, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
),
1068 VULNWL_AMD(0x10, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
),
1069 VULNWL_AMD(0x11, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
),
1070 VULNWL_AMD(0x12, NO_MELTDOWN
| NO_SSB
| NO_L1TF
| NO_MDS
),
1072 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1073 VULNWL_AMD(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
),
1074 VULNWL_HYGON(X86_FAMILY_ANY
, NO_MELTDOWN
| NO_L1TF
| NO_MDS
),
1078 static bool __init
cpu_matches(unsigned long which
)
1080 const struct x86_cpu_id
*m
= x86_match_cpu(cpu_vuln_whitelist
);
1082 return m
&& !!(m
->driver_data
& which
);
1085 static void __init
cpu_set_bug_bits(struct cpuinfo_x86
*c
)
1089 if (cpu_matches(NO_SPECULATION
))
1092 setup_force_cpu_bug(X86_BUG_SPECTRE_V1
);
1093 setup_force_cpu_bug(X86_BUG_SPECTRE_V2
);
1095 if (cpu_has(c
, X86_FEATURE_ARCH_CAPABILITIES
))
1096 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, ia32_cap
);
1098 if (!cpu_matches(NO_SSB
) && !(ia32_cap
& ARCH_CAP_SSB_NO
) &&
1099 !cpu_has(c
, X86_FEATURE_AMD_SSB_NO
))
1100 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS
);
1102 if (ia32_cap
& ARCH_CAP_IBRS_ALL
)
1103 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED
);
1105 if (!cpu_matches(NO_MDS
) && !(ia32_cap
& ARCH_CAP_MDS_NO
)) {
1106 setup_force_cpu_bug(X86_BUG_MDS
);
1107 if (cpu_matches(MSBDS_ONLY
))
1108 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY
);
1111 if (cpu_matches(NO_MELTDOWN
))
1114 /* Rogue Data Cache Load? No! */
1115 if (ia32_cap
& ARCH_CAP_RDCL_NO
)
1118 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN
);
1120 if (cpu_matches(NO_L1TF
))
1123 setup_force_cpu_bug(X86_BUG_L1TF
);
1127 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1128 * unfortunately, that's not true in practice because of early VIA
1129 * chips and (more importantly) broken virtualizers that are not easy
1130 * to detect. In the latter case it doesn't even *fail* reliably, so
1131 * probing for it doesn't even work. Disable it completely on 32-bit
1132 * unless we can find a reliable way to detect all the broken cases.
1133 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1135 static void detect_nopl(void)
1137 #ifdef CONFIG_X86_32
1138 setup_clear_cpu_cap(X86_FEATURE_NOPL
);
1140 setup_force_cpu_cap(X86_FEATURE_NOPL
);
1145 * Do minimum CPU detection early.
1146 * Fields really needed: vendor, cpuid_level, family, model, mask,
1148 * The others are not touched to avoid unwanted side effects.
1150 * WARNING: this function is only called on the boot CPU. Don't add code
1151 * here that is supposed to run on all CPUs.
1153 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
1155 #ifdef CONFIG_X86_64
1156 c
->x86_clflush_size
= 64;
1157 c
->x86_phys_bits
= 36;
1158 c
->x86_virt_bits
= 48;
1160 c
->x86_clflush_size
= 32;
1161 c
->x86_phys_bits
= 32;
1162 c
->x86_virt_bits
= 32;
1164 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1166 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1167 c
->extended_cpuid_level
= 0;
1169 if (!have_cpuid_p())
1170 identify_cpu_without_cpuid(c
);
1172 /* cyrix could have cpuid enabled via c_identify()*/
1173 if (have_cpuid_p()) {
1177 get_cpu_address_sizes(c
);
1178 setup_force_cpu_cap(X86_FEATURE_CPUID
);
1180 if (this_cpu
->c_early_init
)
1181 this_cpu
->c_early_init(c
);
1184 filter_cpuid_features(c
, false);
1186 if (this_cpu
->c_bsp_init
)
1187 this_cpu
->c_bsp_init(c
);
1189 setup_clear_cpu_cap(X86_FEATURE_CPUID
);
1192 setup_force_cpu_cap(X86_FEATURE_ALWAYS
);
1194 cpu_set_bug_bits(c
);
1196 fpu__init_system(c
);
1198 #ifdef CONFIG_X86_32
1200 * Regardless of whether PCID is enumerated, the SDM says
1201 * that it can't be enabled in 32-bit mode.
1203 setup_clear_cpu_cap(X86_FEATURE_PCID
);
1207 * Later in the boot process pgtable_l5_enabled() relies on
1208 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1209 * enabled by this point we need to clear the feature bit to avoid
1210 * false-positives at the later stage.
1212 * pgtable_l5_enabled() can be false here for several reasons:
1213 * - 5-level paging is disabled compile-time;
1214 * - it's 32-bit kernel;
1215 * - machine doesn't support 5-level paging;
1216 * - user specified 'no5lvl' in kernel command line.
1218 if (!pgtable_l5_enabled())
1219 setup_clear_cpu_cap(X86_FEATURE_LA57
);
1224 void __init
early_cpu_init(void)
1226 const struct cpu_dev
*const *cdev
;
1229 #ifdef CONFIG_PROCESSOR_SELECT
1230 pr_info("KERNEL supported cpus:\n");
1233 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
1234 const struct cpu_dev
*cpudev
= *cdev
;
1236 if (count
>= X86_VENDOR_NUM
)
1238 cpu_devs
[count
] = cpudev
;
1241 #ifdef CONFIG_PROCESSOR_SELECT
1245 for (j
= 0; j
< 2; j
++) {
1246 if (!cpudev
->c_ident
[j
])
1248 pr_info(" %s %s\n", cpudev
->c_vendor
,
1249 cpudev
->c_ident
[j
]);
1254 early_identify_cpu(&boot_cpu_data
);
1257 static void detect_null_seg_behavior(struct cpuinfo_x86
*c
)
1259 #ifdef CONFIG_X86_64
1261 * Empirically, writing zero to a segment selector on AMD does
1262 * not clear the base, whereas writing zero to a segment
1263 * selector on Intel does clear the base. Intel's behavior
1264 * allows slightly faster context switches in the common case
1265 * where GS is unused by the prev and next threads.
1267 * Since neither vendor documents this anywhere that I can see,
1268 * detect it directly instead of hardcoding the choice by
1271 * I've designated AMD's behavior as the "bug" because it's
1272 * counterintuitive and less friendly.
1275 unsigned long old_base
, tmp
;
1276 rdmsrl(MSR_FS_BASE
, old_base
);
1277 wrmsrl(MSR_FS_BASE
, 1);
1279 rdmsrl(MSR_FS_BASE
, tmp
);
1281 set_cpu_bug(c
, X86_BUG_NULL_SEG
);
1282 wrmsrl(MSR_FS_BASE
, old_base
);
1286 static void generic_identify(struct cpuinfo_x86
*c
)
1288 c
->extended_cpuid_level
= 0;
1290 if (!have_cpuid_p())
1291 identify_cpu_without_cpuid(c
);
1293 /* cyrix could have cpuid enabled via c_identify()*/
1294 if (!have_cpuid_p())
1303 get_cpu_address_sizes(c
);
1305 if (c
->cpuid_level
>= 0x00000001) {
1306 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
1307 #ifdef CONFIG_X86_32
1309 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1311 c
->apicid
= c
->initial_apicid
;
1314 c
->phys_proc_id
= c
->initial_apicid
;
1317 get_model_name(c
); /* Default name */
1319 detect_null_seg_behavior(c
);
1322 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1323 * systems that run Linux at CPL > 0 may or may not have the
1324 * issue, but, even if they have the issue, there's absolutely
1325 * nothing we can do about it because we can't use the real IRET
1328 * NB: For the time being, only 32-bit kernels support
1329 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1330 * whether to apply espfix using paravirt hooks. If any
1331 * non-paravirt system ever shows up that does *not* have the
1332 * ESPFIX issue, we can change this.
1334 #ifdef CONFIG_X86_32
1335 # ifdef CONFIG_PARAVIRT_XXL
1337 extern void native_iret(void);
1338 if (pv_ops
.cpu
.iret
== native_iret
)
1339 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1342 set_cpu_bug(c
, X86_BUG_ESPFIX
);
1347 static void x86_init_cache_qos(struct cpuinfo_x86
*c
)
1350 * The heavy lifting of max_rmid and cache_occ_scale are handled
1351 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1352 * in case CQM bits really aren't there in this CPU.
1354 if (c
!= &boot_cpu_data
) {
1355 boot_cpu_data
.x86_cache_max_rmid
=
1356 min(boot_cpu_data
.x86_cache_max_rmid
,
1357 c
->x86_cache_max_rmid
);
1362 * Validate that ACPI/mptables have the same information about the
1363 * effective APIC id and update the package map.
1365 static void validate_apic_and_package_id(struct cpuinfo_x86
*c
)
1368 unsigned int apicid
, cpu
= smp_processor_id();
1370 apicid
= apic
->cpu_present_to_apicid(cpu
);
1372 if (apicid
!= c
->apicid
) {
1373 pr_err(FW_BUG
"CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1374 cpu
, apicid
, c
->initial_apicid
);
1376 BUG_ON(topology_update_package_map(c
->phys_proc_id
, cpu
));
1377 BUG_ON(topology_update_die_map(c
->cpu_die_id
, cpu
));
1379 c
->logical_proc_id
= 0;
1384 * This does the hard work of actually picking apart the CPU stuff...
1386 static void identify_cpu(struct cpuinfo_x86
*c
)
1390 c
->loops_per_jiffy
= loops_per_jiffy
;
1391 c
->x86_cache_size
= 0;
1392 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
1393 c
->x86_model
= c
->x86_stepping
= 0; /* So far unknown... */
1394 c
->x86_vendor_id
[0] = '\0'; /* Unset */
1395 c
->x86_model_id
[0] = '\0'; /* Unset */
1396 c
->x86_max_cores
= 1;
1397 c
->x86_coreid_bits
= 0;
1399 #ifdef CONFIG_X86_64
1400 c
->x86_clflush_size
= 64;
1401 c
->x86_phys_bits
= 36;
1402 c
->x86_virt_bits
= 48;
1404 c
->cpuid_level
= -1; /* CPUID not detected */
1405 c
->x86_clflush_size
= 32;
1406 c
->x86_phys_bits
= 32;
1407 c
->x86_virt_bits
= 32;
1409 c
->x86_cache_alignment
= c
->x86_clflush_size
;
1410 memset(&c
->x86_capability
, 0, sizeof(c
->x86_capability
));
1412 generic_identify(c
);
1414 if (this_cpu
->c_identify
)
1415 this_cpu
->c_identify(c
);
1417 /* Clear/Set all flags overridden by options, after probe */
1418 apply_forced_caps(c
);
1420 #ifdef CONFIG_X86_64
1421 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
1425 * Vendor-specific initialization. In this section we
1426 * canonicalize the feature flags, meaning if there are
1427 * features a certain CPU supports which CPUID doesn't
1428 * tell us, CPUID claiming incorrect flags, or other bugs,
1429 * we handle them here.
1431 * At the end of this section, c->x86_capability better
1432 * indicate the features this CPU genuinely supports!
1434 if (this_cpu
->c_init
)
1435 this_cpu
->c_init(c
);
1437 /* Disable the PN if appropriate */
1438 squash_the_stupid_serial_number(c
);
1440 /* Set up SMEP/SMAP/UMIP */
1446 * The vendor-specific functions might have changed features.
1447 * Now we do "generic changes."
1450 /* Filter out anything that depends on CPUID levels we don't have */
1451 filter_cpuid_features(c
, true);
1453 /* If the model name is still unset, do table lookup. */
1454 if (!c
->x86_model_id
[0]) {
1456 p
= table_lookup_model(c
);
1458 strcpy(c
->x86_model_id
, p
);
1460 /* Last resort... */
1461 sprintf(c
->x86_model_id
, "%02x/%02x",
1462 c
->x86
, c
->x86_model
);
1465 #ifdef CONFIG_X86_64
1470 x86_init_cache_qos(c
);
1474 * Clear/Set all flags overridden by options, need do it
1475 * before following smp all cpus cap AND.
1477 apply_forced_caps(c
);
1480 * On SMP, boot_cpu_data holds the common feature set between
1481 * all CPUs; so make sure that we indicate which features are
1482 * common between the CPUs. The first time this routine gets
1483 * executed, c == &boot_cpu_data.
1485 if (c
!= &boot_cpu_data
) {
1486 /* AND the already accumulated flags with these */
1487 for (i
= 0; i
< NCAPINTS
; i
++)
1488 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1490 /* OR, i.e. replicate the bug flags */
1491 for (i
= NCAPINTS
; i
< NCAPINTS
+ NBUGINTS
; i
++)
1492 c
->x86_capability
[i
] |= boot_cpu_data
.x86_capability
[i
];
1495 /* Init Machine Check Exception if available. */
1498 select_idle_routine(c
);
1501 numa_add_cpu(smp_processor_id());
1506 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1507 * on 32-bit kernels:
1509 #ifdef CONFIG_X86_32
1510 void enable_sep_cpu(void)
1512 struct tss_struct
*tss
;
1515 if (!boot_cpu_has(X86_FEATURE_SEP
))
1519 tss
= &per_cpu(cpu_tss_rw
, cpu
);
1522 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1523 * see the big comment in struct x86_hw_tss's definition.
1526 tss
->x86_tss
.ss1
= __KERNEL_CS
;
1527 wrmsr(MSR_IA32_SYSENTER_CS
, tss
->x86_tss
.ss1
, 0);
1528 wrmsr(MSR_IA32_SYSENTER_ESP
, (unsigned long)(cpu_entry_stack(cpu
) + 1), 0);
1529 wrmsr(MSR_IA32_SYSENTER_EIP
, (unsigned long)entry_SYSENTER_32
, 0);
1535 void __init
identify_boot_cpu(void)
1537 identify_cpu(&boot_cpu_data
);
1538 #ifdef CONFIG_X86_32
1542 cpu_detect_tlb(&boot_cpu_data
);
1546 void identify_secondary_cpu(struct cpuinfo_x86
*c
)
1548 BUG_ON(c
== &boot_cpu_data
);
1550 #ifdef CONFIG_X86_32
1554 validate_apic_and_package_id(c
);
1555 x86_spec_ctrl_setup_ap();
1558 static __init
int setup_noclflush(char *arg
)
1560 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH
);
1561 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT
);
1564 __setup("noclflush", setup_noclflush
);
1566 void print_cpu_info(struct cpuinfo_x86
*c
)
1568 const char *vendor
= NULL
;
1570 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
1571 vendor
= this_cpu
->c_vendor
;
1573 if (c
->cpuid_level
>= 0)
1574 vendor
= c
->x86_vendor_id
;
1577 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
1578 pr_cont("%s ", vendor
);
1580 if (c
->x86_model_id
[0])
1581 pr_cont("%s", c
->x86_model_id
);
1583 pr_cont("%d86", c
->x86
);
1585 pr_cont(" (family: 0x%x, model: 0x%x", c
->x86
, c
->x86_model
);
1587 if (c
->x86_stepping
|| c
->cpuid_level
>= 0)
1588 pr_cont(", stepping: 0x%x)\n", c
->x86_stepping
);
1594 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1595 * But we need to keep a dummy __setup around otherwise it would
1596 * show up as an environment variable for init.
1598 static __init
int setup_clearcpuid(char *arg
)
1602 __setup("clearcpuid=", setup_clearcpuid
);
1604 #ifdef CONFIG_X86_64
1605 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data
,
1606 fixed_percpu_data
) __aligned(PAGE_SIZE
) __visible
;
1607 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data
);
1610 * The following percpu variables are hot. Align current_task to
1611 * cacheline size such that they fall in the same cacheline.
1613 DEFINE_PER_CPU(struct task_struct
*, current_task
) ____cacheline_aligned
=
1615 EXPORT_PER_CPU_SYMBOL(current_task
);
1617 DEFINE_PER_CPU(struct irq_stack
*, hardirq_stack_ptr
);
1618 DEFINE_PER_CPU(unsigned int, irq_count
) __visible
= -1;
1620 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1621 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1623 /* May not be marked __init: used by software suspend */
1624 void syscall_init(void)
1626 wrmsr(MSR_STAR
, 0, (__USER32_CS
<< 16) | __KERNEL_CS
);
1627 wrmsrl(MSR_LSTAR
, (unsigned long)entry_SYSCALL_64
);
1629 #ifdef CONFIG_IA32_EMULATION
1630 wrmsrl(MSR_CSTAR
, (unsigned long)entry_SYSCALL_compat
);
1632 * This only works on Intel CPUs.
1633 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1634 * This does not cause SYSENTER to jump to the wrong location, because
1635 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1637 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)__KERNEL_CS
);
1638 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
,
1639 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1640 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, (u64
)entry_SYSENTER_compat
);
1642 wrmsrl(MSR_CSTAR
, (unsigned long)ignore_sysret
);
1643 wrmsrl_safe(MSR_IA32_SYSENTER_CS
, (u64
)GDT_ENTRY_INVALID_SEG
);
1644 wrmsrl_safe(MSR_IA32_SYSENTER_ESP
, 0ULL);
1645 wrmsrl_safe(MSR_IA32_SYSENTER_EIP
, 0ULL);
1648 /* Flags to clear on syscall */
1649 wrmsrl(MSR_SYSCALL_MASK
,
1650 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|
1651 X86_EFLAGS_IOPL
|X86_EFLAGS_AC
|X86_EFLAGS_NT
);
1654 DEFINE_PER_CPU(int, debug_stack_usage
);
1655 DEFINE_PER_CPU(u32
, debug_idt_ctr
);
1657 void debug_stack_set_zero(void)
1659 this_cpu_inc(debug_idt_ctr
);
1662 NOKPROBE_SYMBOL(debug_stack_set_zero
);
1664 void debug_stack_reset(void)
1666 if (WARN_ON(!this_cpu_read(debug_idt_ctr
)))
1668 if (this_cpu_dec_return(debug_idt_ctr
) == 0)
1671 NOKPROBE_SYMBOL(debug_stack_reset
);
1673 #else /* CONFIG_X86_64 */
1675 DEFINE_PER_CPU(struct task_struct
*, current_task
) = &init_task
;
1676 EXPORT_PER_CPU_SYMBOL(current_task
);
1677 DEFINE_PER_CPU(int, __preempt_count
) = INIT_PREEMPT_COUNT
;
1678 EXPORT_PER_CPU_SYMBOL(__preempt_count
);
1681 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1682 * the top of the kernel stack. Use an extra percpu variable to track the
1683 * top of the kernel stack directly.
1685 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack
) =
1686 (unsigned long)&init_thread_union
+ THREAD_SIZE
;
1687 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack
);
1689 #ifdef CONFIG_STACKPROTECTOR
1690 DEFINE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
1693 #endif /* CONFIG_X86_64 */
1696 * Clear all 6 debug registers:
1698 static void clear_all_debug_regs(void)
1702 for (i
= 0; i
< 8; i
++) {
1703 /* Ignore db4, db5 */
1704 if ((i
== 4) || (i
== 5))
1713 * Restore debug regs if using kgdbwait and you have a kernel debugger
1714 * connection established.
1716 static void dbg_restore_debug_regs(void)
1718 if (unlikely(kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
))
1719 arch_kgdb_ops
.correct_hw_break();
1721 #else /* ! CONFIG_KGDB */
1722 #define dbg_restore_debug_regs()
1723 #endif /* ! CONFIG_KGDB */
1725 static void wait_for_master_cpu(int cpu
)
1729 * wait for ACK from master CPU before continuing
1730 * with AP initialization
1732 WARN_ON(cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
));
1733 while (!cpumask_test_cpu(cpu
, cpu_callout_mask
))
1738 #ifdef CONFIG_X86_64
1739 static void setup_getcpu(int cpu
)
1741 unsigned long cpudata
= vdso_encode_cpunode(cpu
, early_cpu_to_node(cpu
));
1742 struct desc_struct d
= { };
1744 if (boot_cpu_has(X86_FEATURE_RDTSCP
))
1745 write_rdtscp_aux(cpudata
);
1747 /* Store CPU and node number in limit. */
1749 d
.limit1
= cpudata
>> 16;
1751 d
.type
= 5; /* RO data, expand down, accessed */
1752 d
.dpl
= 3; /* Visible to user code */
1753 d
.s
= 1; /* Not a system segment */
1754 d
.p
= 1; /* Present */
1755 d
.d
= 1; /* 32-bit */
1757 write_gdt_entry(get_cpu_gdt_rw(cpu
), GDT_ENTRY_CPUNODE
, &d
, DESCTYPE_S
);
1762 * cpu_init() initializes state that is per-CPU. Some data is already
1763 * initialized (naturally) in the bootstrap process, such as the GDT
1764 * and IDT. We reload them nevertheless, this function acts as a
1765 * 'CPU state barrier', nothing should get across.
1767 #ifdef CONFIG_X86_64
1771 int cpu
= raw_smp_processor_id();
1772 struct task_struct
*me
;
1773 struct tss_struct
*t
;
1776 wait_for_master_cpu(cpu
);
1781 t
= &per_cpu(cpu_tss_rw
, cpu
);
1784 if (this_cpu_read(numa_node
) == 0 &&
1785 early_cpu_to_node(cpu
) != NUMA_NO_NODE
)
1786 set_numa_node(early_cpu_to_node(cpu
));
1792 pr_debug("Initializing CPU#%d\n", cpu
);
1794 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1797 * Initialize the per-CPU GDT with the boot GDT,
1798 * and set up the GDT descriptor:
1801 switch_to_new_gdt(cpu
);
1806 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1809 wrmsrl(MSR_FS_BASE
, 0);
1810 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1817 * set up and load the per-CPU TSS
1819 if (!t
->x86_tss
.ist
[0]) {
1820 t
->x86_tss
.ist
[IST_INDEX_DF
] = __this_cpu_ist_top_va(DF
);
1821 t
->x86_tss
.ist
[IST_INDEX_NMI
] = __this_cpu_ist_top_va(NMI
);
1822 t
->x86_tss
.ist
[IST_INDEX_DB
] = __this_cpu_ist_top_va(DB
);
1823 t
->x86_tss
.ist
[IST_INDEX_MCE
] = __this_cpu_ist_top_va(MCE
);
1826 t
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET
;
1829 * <= is required because the CPU will access up to
1830 * 8 bits beyond the end of the IO permission bitmap.
1832 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1833 t
->io_bitmap
[i
] = ~0UL;
1836 me
->active_mm
= &init_mm
;
1838 initialize_tlbstate_and_flush();
1839 enter_lazy_tlb(&init_mm
, me
);
1842 * Initialize the TSS. sp0 points to the entry trampoline stack
1843 * regardless of what task is running.
1845 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1847 load_sp0((unsigned long)(cpu_entry_stack(cpu
) + 1));
1849 load_mm_ldt(&init_mm
);
1851 clear_all_debug_regs();
1852 dbg_restore_debug_regs();
1859 load_fixmap_gdt(cpu
);
1866 int cpu
= smp_processor_id();
1867 struct task_struct
*curr
= current
;
1868 struct tss_struct
*t
= &per_cpu(cpu_tss_rw
, cpu
);
1870 wait_for_master_cpu(cpu
);
1872 show_ucode_info_early();
1874 pr_info("Initializing CPU#%d\n", cpu
);
1876 if (cpu_feature_enabled(X86_FEATURE_VME
) ||
1877 boot_cpu_has(X86_FEATURE_TSC
) ||
1878 boot_cpu_has(X86_FEATURE_DE
))
1879 cr4_clear_bits(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1882 switch_to_new_gdt(cpu
);
1885 * Set up and load the per-CPU TSS and LDT
1888 curr
->active_mm
= &init_mm
;
1890 initialize_tlbstate_and_flush();
1891 enter_lazy_tlb(&init_mm
, curr
);
1894 * Initialize the TSS. sp0 points to the entry trampoline stack
1895 * regardless of what task is running.
1897 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1899 load_sp0((unsigned long)(cpu_entry_stack(cpu
) + 1));
1901 load_mm_ldt(&init_mm
);
1903 t
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET
;
1905 #ifdef CONFIG_DOUBLEFAULT
1906 /* Set up doublefault TSS pointer in the GDT */
1907 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1910 clear_all_debug_regs();
1911 dbg_restore_debug_regs();
1915 load_fixmap_gdt(cpu
);
1920 * The microcode loader calls this upon late microcode load to recheck features,
1921 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1924 void microcode_check(void)
1926 struct cpuinfo_x86 info
;
1928 perf_check_microcode();
1930 /* Reload CPUID max function as it might've changed. */
1931 info
.cpuid_level
= cpuid_eax(0);
1934 * Copy all capability leafs to pick up the synthetic ones so that
1935 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1936 * get overwritten in get_cpu_cap().
1938 memcpy(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
));
1942 if (!memcmp(&info
.x86_capability
, &boot_cpu_data
.x86_capability
, sizeof(info
.x86_capability
)))
1945 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1946 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");