1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
26 #include <mach_apic.h>
29 #include <asm/pgtable.h>
30 #include <asm/processor.h>
32 #include <asm/atomic.h>
33 #include <asm/proto.h>
34 #include <asm/sections.h>
35 #include <asm/setup.h>
36 #include <asm/genapic.h>
40 /* We need valid kernel segments for data and code in long mode too
41 * IRET will check the segment types kkeil 2000/10/28
42 * Also sysret mandates a special GDT layout
44 /* The TLS descriptors are currently at a different place compared to i386.
45 Hopefully nobody expects them at a fixed place (Wine?) */
46 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
47 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
48 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
49 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
50 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
51 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
52 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
54 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
56 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
58 /* Current gdt points %fs at the "master" per-cpu area: after this,
59 * it's on the real one. */
60 void switch_to_new_gdt(void)
62 struct desc_ptr gdt_descr
;
64 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
65 gdt_descr
.size
= GDT_SIZE
- 1;
69 struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
71 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
76 static struct cpu_dev __cpuinitdata default_cpu
= {
77 .c_init
= default_init
,
78 .c_vendor
= "Unknown",
80 static struct cpu_dev
*this_cpu __cpuinitdata
= &default_cpu
;
82 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
86 if (c
->extended_cpuid_level
< 0x80000004)
89 v
= (unsigned int *) c
->x86_model_id
;
90 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
91 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
92 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
93 c
->x86_model_id
[48] = 0;
98 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
100 unsigned int n
, dummy
, ebx
, ecx
, edx
;
102 n
= c
->extended_cpuid_level
;
104 if (n
>= 0x80000005) {
105 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
106 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
107 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
108 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
109 /* On K8 L1 TLB is inclusive, so don't count it */
113 if (n
>= 0x80000006) {
114 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
115 ecx
= cpuid_ecx(0x80000006);
116 c
->x86_cache_size
= ecx
>> 16;
117 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
119 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
120 c
->x86_cache_size
, ecx
& 0xFF);
124 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
127 u32 eax
, ebx
, ecx
, edx
;
128 int index_msb
, core_bits
;
130 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
133 if (!cpu_has(c
, X86_FEATURE_HT
))
135 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
138 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
140 if (smp_num_siblings
== 1) {
141 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
142 } else if (smp_num_siblings
> 1) {
144 if (smp_num_siblings
> NR_CPUS
) {
145 printk(KERN_WARNING
"CPU: Unsupported number of siblings %d",
147 smp_num_siblings
= 1;
151 index_msb
= get_count_order(smp_num_siblings
);
152 c
->phys_proc_id
= phys_pkg_id(index_msb
);
154 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
156 index_msb
= get_count_order(smp_num_siblings
);
158 core_bits
= get_count_order(c
->x86_max_cores
);
160 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
161 ((1 << core_bits
) - 1);
164 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
165 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
167 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
174 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
176 char *v
= c
->x86_vendor_id
;
180 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
182 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
183 (cpu_devs
[i
]->c_ident
[1] &&
184 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
186 this_cpu
= cpu_devs
[i
];
193 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
194 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
196 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
197 this_cpu
= &default_cpu
;
200 static void __init
early_cpu_support_print(void)
203 struct cpu_dev
*cpu_devx
;
205 printk("KERNEL supported cpus:\n");
206 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
207 cpu_devx
= cpu_devs
[i
];
210 for (j
= 0; j
< 2; j
++) {
211 if (!cpu_devx
->c_ident
[j
])
213 printk(" %s %s\n", cpu_devx
->c_vendor
,
214 cpu_devx
->c_ident
[j
]);
219 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
221 /* Get vendor name */
222 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
223 (unsigned int *)&c
->x86_vendor_id
[0],
224 (unsigned int *)&c
->x86_vendor_id
[8],
225 (unsigned int *)&c
->x86_vendor_id
[4]);
228 /* Intel-defined flags: level 0x00000001 */
229 if (c
->cpuid_level
>= 0x00000001) {
230 u32 junk
, tfms
, cap0
, misc
;
231 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
232 c
->x86
= (tfms
>> 8) & 0xf;
233 c
->x86_model
= (tfms
>> 4) & 0xf;
234 c
->x86_mask
= tfms
& 0xf;
236 c
->x86
+= (tfms
>> 20) & 0xff;
238 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
239 if (cap0
& (1<<19)) {
240 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
241 c
->x86_cache_alignment
= c
->x86_clflush_size
;
247 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
252 /* Intel-defined flags: level 0x00000001 */
253 if (c
->cpuid_level
>= 0x00000001) {
254 u32 capability
, excap
;
256 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
257 c
->x86_capability
[0] = capability
;
258 c
->x86_capability
[4] = excap
;
261 /* AMD-defined flags: level 0x80000001 */
262 xlvl
= cpuid_eax(0x80000000);
263 c
->extended_cpuid_level
= xlvl
;
264 if ((xlvl
& 0xffff0000) == 0x80000000) {
265 if (xlvl
>= 0x80000001) {
266 c
->x86_capability
[1] = cpuid_edx(0x80000001);
267 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
271 /* Transmeta-defined flags: level 0x80860001 */
272 xlvl
= cpuid_eax(0x80860000);
273 if ((xlvl
& 0xffff0000) == 0x80860000) {
274 /* Don't set x86_cpuid_level here for now to not confuse. */
275 if (xlvl
>= 0x80860001)
276 c
->x86_capability
[2] = cpuid_edx(0x80860001);
279 if (c
->extended_cpuid_level
>= 0x80000007)
280 c
->x86_power
= cpuid_edx(0x80000007);
282 if (c
->extended_cpuid_level
>= 0x80000008) {
283 u32 eax
= cpuid_eax(0x80000008);
285 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
286 c
->x86_phys_bits
= eax
& 0xff;
290 /* Do some early cpuid on the boot CPU to get some parameter that are
291 needed before check_bugs. Everything advanced is in identify_cpu
293 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
296 c
->x86_clflush_size
= 64;
297 c
->x86_cache_alignment
= c
->x86_clflush_size
;
299 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
301 c
->extended_cpuid_level
= 0;
309 if (c
->x86_vendor
!= X86_VENDOR_UNKNOWN
&&
310 cpu_devs
[c
->x86_vendor
]->c_early_init
)
311 cpu_devs
[c
->x86_vendor
]->c_early_init(c
);
313 validate_pat_support(c
);
316 void __init
early_cpu_init(void)
318 struct cpu_vendor_dev
*cvdev
;
320 for (cvdev
= __x86cpuvendor_start
; cvdev
< __x86cpuvendor_end
; cvdev
++)
321 cpu_devs
[cvdev
->vendor
] = cvdev
->cpu_dev
;
323 early_cpu_support_print();
324 early_identify_cpu(&boot_cpu_data
);
328 * The NOPL instruction is supposed to exist on all CPUs with
329 * family >= 6, unfortunately, that's not true in practice because
330 * of early VIA chips and (more importantly) broken virtualizers that
331 * are not easy to detect. Hence, probe for it based on first
334 * Note: no 64-bit chip is known to lack these, but put the code here
335 * for consistency with 32 bits, and to make it utterly trivial to
336 * diagnose the problem should it ever surface.
338 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
340 const u32 nopl_signature
= 0x888c53b1; /* Random number */
341 u32 has_nopl
= nopl_signature
;
343 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
346 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
348 " .section .fixup,\"ax\"\n"
355 if (has_nopl
== nopl_signature
)
356 set_cpu_cap(c
, X86_FEATURE_NOPL
);
360 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
362 c
->extended_cpuid_level
= 0;
370 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xff;
372 c
->phys_proc_id
= c
->initial_apicid
;
375 if (c
->extended_cpuid_level
>= 0x80000004)
376 get_model_name(c
); /* Default name */
378 init_scattered_cpuid_features(c
);
383 * This does the hard work of actually picking apart the CPU stuff...
385 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
389 c
->loops_per_jiffy
= loops_per_jiffy
;
390 c
->x86_cache_size
= -1;
391 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
392 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
393 c
->x86_vendor_id
[0] = '\0'; /* Unset */
394 c
->x86_model_id
[0] = '\0'; /* Unset */
395 c
->x86_clflush_size
= 64;
396 c
->x86_cache_alignment
= c
->x86_clflush_size
;
397 c
->x86_max_cores
= 1;
398 c
->x86_coreid_bits
= 0;
399 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
403 c
->apicid
= phys_pkg_id(0);
406 * Vendor-specific initialization. In this section we
407 * canonicalize the feature flags, meaning if there are
408 * features a certain CPU supports which CPUID doesn't
409 * tell us, CPUID claiming incorrect flags, or other bugs,
410 * we handle them here.
412 * At the end of this section, c->x86_capability better
413 * indicate the features this CPU genuinely supports!
415 if (this_cpu
->c_init
)
421 * On SMP, boot_cpu_data holds the common feature set between
422 * all CPUs; so make sure that we indicate which features are
423 * common between the CPUs. The first time this routine gets
424 * executed, c == &boot_cpu_data.
426 if (c
!= &boot_cpu_data
) {
427 /* AND the already accumulated flags with these */
428 for (i
= 0; i
< NCAPINTS
; i
++)
429 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
432 /* Clear all flags overriden by options */
433 for (i
= 0; i
< NCAPINTS
; i
++)
434 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
436 #ifdef CONFIG_X86_MCE
439 select_idle_routine(c
);
442 numa_add_cpu(smp_processor_id());
447 void __init
identify_boot_cpu(void)
449 identify_cpu(&boot_cpu_data
);
452 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
454 BUG_ON(c
== &boot_cpu_data
);
464 static struct msr_range msr_range_array
[] __cpuinitdata
= {
465 { 0x00000000, 0x00000418},
466 { 0xc0000000, 0xc000040b},
467 { 0xc0010000, 0xc0010142},
468 { 0xc0011000, 0xc001103b},
471 static void __cpuinit
print_cpu_msr(void)
476 unsigned index_min
, index_max
;
478 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
479 index_min
= msr_range_array
[i
].min
;
480 index_max
= msr_range_array
[i
].max
;
481 for (index
= index_min
; index
< index_max
; index
++) {
482 if (rdmsrl_amd_safe(index
, &val
))
484 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
489 static int show_msr __cpuinitdata
;
490 static __init
int setup_show_msr(char *arg
)
494 get_option(&arg
, &num
);
500 __setup("show_msr=", setup_show_msr
);
502 static __init
int setup_noclflush(char *arg
)
504 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
507 __setup("noclflush", setup_noclflush
);
509 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
511 if (c
->x86_model_id
[0])
512 printk(KERN_CONT
"%s", c
->x86_model_id
);
514 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
515 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
517 printk(KERN_CONT
"\n");
520 if (c
->cpu_index
< show_msr
)
528 static __init
int setup_disablecpuid(char *arg
)
531 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
532 setup_clear_cpu_cap(bit
);
537 __setup("clearcpuid=", setup_disablecpuid
);
539 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
541 struct x8664_pda
**_cpu_pda __read_mostly
;
542 EXPORT_SYMBOL(_cpu_pda
);
544 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
546 char boot_cpu_stack
[IRQSTACKSIZE
] __page_aligned_bss
;
548 unsigned long __supported_pte_mask __read_mostly
= ~0UL;
549 EXPORT_SYMBOL_GPL(__supported_pte_mask
);
551 static int do_not_nx __cpuinitdata
;
554 Control non executable mappings for 64bit processes.
559 static int __init
nonx_setup(char *str
)
563 if (!strncmp(str
, "on", 2)) {
564 __supported_pte_mask
|= _PAGE_NX
;
566 } else if (!strncmp(str
, "off", 3)) {
568 __supported_pte_mask
&= ~_PAGE_NX
;
572 early_param("noexec", nonx_setup
);
574 int force_personality32
;
577 Control non executable heap for 32bit processes.
578 To control the stack too use noexec=off
580 on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
581 off PROT_READ implies PROT_EXEC
583 static int __init
nonx32_setup(char *str
)
585 if (!strcmp(str
, "on"))
586 force_personality32
&= ~READ_IMPLIES_EXEC
;
587 else if (!strcmp(str
, "off"))
588 force_personality32
|= READ_IMPLIES_EXEC
;
591 __setup("noexec32=", nonx32_setup
);
593 void pda_init(int cpu
)
595 struct x8664_pda
*pda
= cpu_pda(cpu
);
597 /* Setup up data that may be needed in __get_free_pages early */
600 /* Memory clobbers used to order PDA accessed */
602 wrmsrl(MSR_GS_BASE
, pda
);
605 pda
->cpunumber
= cpu
;
607 pda
->kernelstack
= (unsigned long)stack_thread_info() -
608 PDA_STACKOFFSET
+ THREAD_SIZE
;
609 pda
->active_mm
= &init_mm
;
613 /* others are initialized in smpboot.c */
614 pda
->pcurrent
= &init_task
;
615 pda
->irqstackptr
= boot_cpu_stack
;
617 pda
->irqstackptr
= (char *)
618 __get_free_pages(GFP_ATOMIC
, IRQSTACK_ORDER
);
619 if (!pda
->irqstackptr
)
620 panic("cannot allocate irqstack for cpu %d", cpu
);
622 if (pda
->nodenumber
== 0 && cpu_to_node(cpu
) != NUMA_NO_NODE
)
623 pda
->nodenumber
= cpu_to_node(cpu
);
626 pda
->irqstackptr
+= IRQSTACKSIZE
-64;
629 char boot_exception_stacks
[(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+
630 DEBUG_STKSZ
] __page_aligned_bss
;
632 extern asmlinkage
void ignore_sysret(void);
634 /* May not be marked __init: used by software suspend */
635 void syscall_init(void)
638 * LSTAR and STAR live in a bit strange symbiosis.
639 * They both write to the same internal register. STAR allows to
640 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
642 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
643 wrmsrl(MSR_LSTAR
, system_call
);
644 wrmsrl(MSR_CSTAR
, ignore_sysret
);
646 #ifdef CONFIG_IA32_EMULATION
647 syscall32_cpu_init();
650 /* Flags to clear on syscall */
651 wrmsrl(MSR_SYSCALL_MASK
,
652 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
655 void __cpuinit
check_efer(void)
659 rdmsrl(MSR_EFER
, efer
);
660 if (!(efer
& EFER_NX
) || do_not_nx
)
661 __supported_pte_mask
&= ~_PAGE_NX
;
664 unsigned long kernel_eflags
;
667 * Copies of the original ist values from the tss are only accessed during
668 * debugging, no special alignment required.
670 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
673 * cpu_init() initializes state that is per-CPU. Some data is already
674 * initialized (naturally) in the bootstrap process, such as the GDT
675 * and IDT. We reload them nevertheless, this function acts as a
676 * 'CPU state barrier', nothing should get across.
677 * A lot of state is already set up in PDA init.
679 void __cpuinit
cpu_init(void)
681 int cpu
= stack_smp_processor_id();
682 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
683 struct orig_ist
*orig_ist
= &per_cpu(orig_ist
, cpu
);
685 char *estacks
= NULL
;
686 struct task_struct
*me
;
689 /* CPU 0 is initialised in head64.c */
693 estacks
= boot_exception_stacks
;
697 if (cpu_test_and_set(cpu
, cpu_initialized
))
698 panic("CPU#%d already initialized!\n", cpu
);
700 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
702 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
705 * Initialize the per-CPU GDT with the boot GDT,
706 * and set up the GDT descriptor:
710 load_idt((const struct desc_ptr
*)&idt_descr
);
712 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
715 wrmsrl(MSR_FS_BASE
, 0);
716 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
722 * set up and load the per-CPU TSS
724 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
725 static const unsigned int order
[N_EXCEPTION_STACKS
] = {
726 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STACK_ORDER
,
727 [DEBUG_STACK
- 1] = DEBUG_STACK_ORDER
730 estacks
= (char *)__get_free_pages(GFP_ATOMIC
, order
[v
]);
732 panic("Cannot allocate exception stack %ld %d\n",
735 estacks
+= PAGE_SIZE
<< order
[v
];
736 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] = (unsigned long)estacks
;
739 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
741 * <= is required because the CPU will access up to
742 * 8 bits beyond the end of the IO permission bitmap.
744 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
745 t
->io_bitmap
[i
] = ~0UL;
747 atomic_inc(&init_mm
.mm_count
);
748 me
->active_mm
= &init_mm
;
751 enter_lazy_tlb(&init_mm
, me
);
753 load_sp0(t
, ¤t
->thread
);
754 set_tss_desc(cpu
, t
);
756 load_LDT(&init_mm
.context
);
760 * If the kgdb is connected no debug regs should be altered. This
761 * is only applicable when KGDB and a KGDB I/O module are built
762 * into the kernel and you are using early debugging with
763 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
765 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
766 arch_kgdb_ops
.correct_hw_break();
770 * Clear all 6 debug registers:
773 set_debugreg(0UL, 0);
774 set_debugreg(0UL, 1);
775 set_debugreg(0UL, 2);
776 set_debugreg(0UL, 3);
777 set_debugreg(0UL, 6);
778 set_debugreg(0UL, 7);
780 /* If the kgdb is connected no debug regs should be altered. */
786 raw_local_save_flags(kernel_eflags
);