2 * (C) 2001-2004 Dave Jones. <davej@redhat.com>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is backward compatible with v1, but adds
12 * LONGHAUL MSR for purpose of both frequency and voltage scaling.
13 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14 * Version 3 of longhaul got renamed to Powersaver and redesigned
15 * to use only the POWERSAVER MSR at 0x110a.
16 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17 * It's pretty much the same feature wise to longhaul v2, though
18 * there is provision for scaling FSB too, but this doesn't work
19 * too well in practice so we don't even try to use this.
21 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/cpufreq.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33 #include <linux/timex.h>
35 #include <linux/acpi.h>
36 #include <linux/kernel.h>
39 #include <acpi/processor.h>
43 #define PFX "longhaul: "
45 #define TYPE_LONGHAUL_V1 1
46 #define TYPE_LONGHAUL_V2 2
47 #define TYPE_POWERSAVER 3
53 #define CPU_NEHEMIAH 5
54 #define CPU_NEHEMIAH_C 6
57 #define USE_ACPI_C3 (1 << 1)
58 #define USE_NORTHBRIDGE (1 << 2)
61 static unsigned int numscales
= 16;
62 static unsigned int fsb
;
64 static const struct mV_pos
*vrm_mV_table
;
65 static const unsigned char *mV_vrm_table
;
67 static unsigned int highest_speed
, lowest_speed
; /* kHz */
68 static unsigned int minmult
, maxmult
;
69 static int can_scale_voltage
;
70 static struct acpi_processor
*pr
;
71 static struct acpi_processor_cx
*cx
;
72 static u32 acpi_regs_addr
;
73 static u8 longhaul_flags
;
74 static unsigned int longhaul_index
;
76 /* Module parameters */
77 static int scale_voltage
;
78 static int disable_acpi_c3
;
79 static int revid_errata
;
81 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
85 /* Clock ratios multiplied by 10 */
88 static int longhaul_version
;
89 static struct cpufreq_frequency_table
*longhaul_table
;
91 #ifdef CONFIG_CPU_FREQ_DEBUG
92 static char speedbuffer
[8];
94 static char *print_speed(int speed
)
97 snprintf(speedbuffer
, sizeof(speedbuffer
), "%dMHz", speed
);
102 snprintf(speedbuffer
, sizeof(speedbuffer
),
103 "%dGHz", speed
/1000);
105 snprintf(speedbuffer
, sizeof(speedbuffer
),
106 "%d.%dGHz", speed
/1000, (speed
%1000)/100);
113 static unsigned int calc_speed(int mult
)
124 static int longhaul_get_cpu_mult(void)
126 unsigned long invalue
= 0, lo
, hi
;
128 rdmsr(MSR_IA32_EBL_CR_POWERON
, lo
, hi
);
129 invalue
= (lo
& (1<<22|1<<23|1<<24|1<<25))>>22;
130 if (longhaul_version
== TYPE_LONGHAUL_V2
||
131 longhaul_version
== TYPE_POWERSAVER
) {
135 return eblcr
[invalue
];
138 /* For processor with BCR2 MSR */
140 static void do_longhaul1(unsigned int mults_index
)
144 rdmsrl(MSR_VIA_BCR2
, bcr2
.val
);
145 /* Enable software clock multiplier */
146 bcr2
.bits
.ESOFTBF
= 1;
147 bcr2
.bits
.CLOCKMUL
= mults_index
& 0xff;
149 /* Sync to timer tick */
151 /* Change frequency on next halt or sleep */
152 wrmsrl(MSR_VIA_BCR2
, bcr2
.val
);
153 /* Invoke transition */
154 ACPI_FLUSH_CPU_CACHE();
157 /* Disable software clock multiplier */
159 rdmsrl(MSR_VIA_BCR2
, bcr2
.val
);
160 bcr2
.bits
.ESOFTBF
= 0;
161 wrmsrl(MSR_VIA_BCR2
, bcr2
.val
);
164 /* For processor with Longhaul MSR */
166 static void do_powersaver(int cx_address
, unsigned int mults_index
,
169 union msr_longhaul longhaul
;
172 rdmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
173 /* Setup new frequency */
175 longhaul
.bits
.RevisionKey
= longhaul
.bits
.RevisionID
;
177 longhaul
.bits
.RevisionKey
= 0;
178 longhaul
.bits
.SoftBusRatio
= mults_index
& 0xf;
179 longhaul
.bits
.SoftBusRatio4
= (mults_index
& 0x10) >> 4;
180 /* Setup new voltage */
181 if (can_scale_voltage
)
182 longhaul
.bits
.SoftVID
= (mults_index
>> 8) & 0x1f;
183 /* Sync to timer tick */
185 /* Raise voltage if necessary */
186 if (can_scale_voltage
&& dir
) {
187 longhaul
.bits
.EnableSoftVID
= 1;
188 wrmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
191 ACPI_FLUSH_CPU_CACHE();
194 ACPI_FLUSH_CPU_CACHE();
197 /* Dummy op - must do something useless after P_LVL3
199 t
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
201 longhaul
.bits
.EnableSoftVID
= 0;
202 wrmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
205 /* Change frequency on next halt or sleep */
206 longhaul
.bits
.EnableSoftBusRatio
= 1;
207 wrmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
209 ACPI_FLUSH_CPU_CACHE();
212 ACPI_FLUSH_CPU_CACHE();
215 /* Dummy op - must do something useless after P_LVL3 read */
216 t
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
218 /* Disable bus ratio bit */
219 longhaul
.bits
.EnableSoftBusRatio
= 0;
220 wrmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
222 /* Reduce voltage if necessary */
223 if (can_scale_voltage
&& !dir
) {
224 longhaul
.bits
.EnableSoftVID
= 1;
225 wrmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
228 ACPI_FLUSH_CPU_CACHE();
231 ACPI_FLUSH_CPU_CACHE();
234 /* Dummy op - must do something useless after P_LVL3
236 t
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
238 longhaul
.bits
.EnableSoftVID
= 0;
239 wrmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
244 * longhaul_set_cpu_frequency()
245 * @mults_index : bitpattern of the new multiplier.
247 * Sets a new clock ratio.
250 static void longhaul_setstate(unsigned int table_index
)
252 unsigned int mults_index
;
254 struct cpufreq_freqs freqs
;
256 unsigned int pic1_mask
, pic2_mask
;
258 u32 bm_timeout
= 1000;
259 unsigned int dir
= 0;
261 mults_index
= longhaul_table
[table_index
].index
;
262 /* Safety precautions */
263 mult
= mults
[mults_index
& 0x1f];
266 speed
= calc_speed(mult
);
267 if ((speed
> highest_speed
) || (speed
< lowest_speed
))
269 /* Voltage transition before frequency transition? */
270 if (can_scale_voltage
&& longhaul_index
< table_index
)
273 freqs
.old
= calc_speed(longhaul_get_cpu_mult());
275 freqs
.cpu
= 0; /* longhaul.c is UP only driver */
277 cpufreq_notify_transition(&freqs
, CPUFREQ_PRECHANGE
);
279 dprintk("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
280 fsb
, mult
/10, mult
%10, print_speed(speed
/1000));
283 local_irq_save(flags
);
285 pic2_mask
= inb(0xA1);
286 pic1_mask
= inb(0x21); /* works on C3. save mask. */
287 outb(0xFF, 0xA1); /* Overkill */
288 outb(0xFE, 0x21); /* TMR0 only */
290 /* Wait while PCI bus is busy. */
291 if (acpi_regs_addr
&& (longhaul_flags
& USE_NORTHBRIDGE
292 || ((pr
!= NULL
) && pr
->flags
.bm_control
))) {
293 bm_status
= inw(acpi_regs_addr
);
295 while (bm_status
&& bm_timeout
) {
296 outw(1 << 4, acpi_regs_addr
);
298 bm_status
= inw(acpi_regs_addr
);
303 if (longhaul_flags
& USE_NORTHBRIDGE
) {
304 /* Disable AGP and PCI arbiters */
306 } else if ((pr
!= NULL
) && pr
->flags
.bm_control
) {
307 /* Disable bus master arbitration */
308 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE
, 1);
310 switch (longhaul_version
) {
313 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
314 * Software controlled multipliers only.
316 case TYPE_LONGHAUL_V1
:
317 do_longhaul1(mults_index
);
321 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
323 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
324 * Nehemiah can do FSB scaling too, but this has never been proven
325 * to work in practice.
327 case TYPE_LONGHAUL_V2
:
328 case TYPE_POWERSAVER
:
329 if (longhaul_flags
& USE_ACPI_C3
) {
330 /* Don't allow wakeup */
331 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD
, 0);
332 do_powersaver(cx
->address
, mults_index
, dir
);
334 do_powersaver(0, mults_index
, dir
);
339 if (longhaul_flags
& USE_NORTHBRIDGE
) {
340 /* Enable arbiters */
342 } else if ((pr
!= NULL
) && pr
->flags
.bm_control
) {
343 /* Enable bus master arbitration */
344 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE
, 0);
346 outb(pic2_mask
, 0xA1); /* restore mask */
347 outb(pic1_mask
, 0x21);
349 local_irq_restore(flags
);
352 freqs
.new = calc_speed(longhaul_get_cpu_mult());
353 /* Check if requested frequency is set. */
354 if (unlikely(freqs
.new != speed
)) {
355 printk(KERN_INFO PFX
"Failed to set requested frequency!\n");
356 /* Revision ID = 1 but processor is expecting revision key
357 * equal to 0. Jumpers at the bottom of processor will change
358 * multiplier and FSB, but will not change bits in Longhaul
359 * MSR nor enable voltage scaling. */
361 printk(KERN_INFO PFX
"Enabling \"Ignore Revision ID\" "
367 /* Why ACPI C3 sometimes doesn't work is a mystery for me.
368 * But it does happen. Processor is entering ACPI C3 state,
369 * but it doesn't change frequency. I tried poking various
370 * bits in northbridge registers, but without success. */
371 if (longhaul_flags
& USE_ACPI_C3
) {
372 printk(KERN_INFO PFX
"Disabling ACPI C3 support.\n");
373 longhaul_flags
&= ~USE_ACPI_C3
;
375 printk(KERN_INFO PFX
"Disabling \"Ignore "
376 "Revision ID\" option.\n");
382 /* This shouldn't happen. Longhaul ver. 2 was reported not
383 * working on processors without voltage scaling, but with
384 * RevID = 1. RevID errata will make things right. Just
385 * to be 100% sure. */
386 if (longhaul_version
== TYPE_LONGHAUL_V2
) {
387 printk(KERN_INFO PFX
"Switching to Longhaul ver. 1\n");
388 longhaul_version
= TYPE_LONGHAUL_V1
;
393 /* Report true CPU frequency */
394 cpufreq_notify_transition(&freqs
, CPUFREQ_POSTCHANGE
);
397 printk(KERN_INFO PFX
"Warning: Timeout while waiting for "
402 * Centaur decided to make life a little more tricky.
403 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
404 * Samuel2 and above have to try and guess what the FSB is.
405 * We do this by assuming we booted at maximum multiplier, and interpolate
406 * between that value multiplied by possible FSBs and cpu_mhz which
407 * was calculated at boot time. Really ugly, but no other way to do this.
412 static int guess_fsb(int mult
)
414 int speed
= cpu_khz
/ 1000;
416 int speeds
[] = { 666, 1000, 1333, 2000 };
419 for (i
= 0; i
< 4; i
++) {
420 f_max
= ((speeds
[i
] * mult
) + 50) / 100;
421 f_max
+= (ROUNDING
/ 2);
422 f_min
= f_max
- ROUNDING
;
423 if ((speed
<= f_max
) && (speed
>= f_min
))
424 return speeds
[i
] / 10;
430 static int __init
longhaul_get_ranges(void)
432 unsigned int i
, j
, k
= 0;
436 /* Get current frequency */
437 mult
= longhaul_get_cpu_mult();
439 printk(KERN_INFO PFX
"Invalid (reserved) multiplier!\n");
442 fsb
= guess_fsb(mult
);
444 printk(KERN_INFO PFX
"Invalid (reserved) FSB!\n");
447 /* Get max multiplier - as we always did.
448 * Longhaul MSR is usefull only when voltage scaling is enabled.
449 * C3 is booting at max anyway. */
451 /* Get min multiplier */
464 dprintk("MinMult:%d.%dx MaxMult:%d.%dx\n",
465 minmult
/10, minmult
%10, maxmult
/10, maxmult
%10);
467 highest_speed
= calc_speed(maxmult
);
468 lowest_speed
= calc_speed(minmult
);
469 dprintk("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb
,
470 print_speed(lowest_speed
/1000),
471 print_speed(highest_speed
/1000));
473 if (lowest_speed
== highest_speed
) {
474 printk(KERN_INFO PFX
"highestspeed == lowest, aborting.\n");
477 if (lowest_speed
> highest_speed
) {
478 printk(KERN_INFO PFX
"nonsense! lowest (%d > %d) !\n",
479 lowest_speed
, highest_speed
);
483 longhaul_table
= kmalloc((numscales
+ 1) * sizeof(*longhaul_table
),
488 for (j
= 0; j
< numscales
; j
++) {
492 if (ratio
> maxmult
|| ratio
< minmult
)
494 longhaul_table
[k
].frequency
= calc_speed(ratio
);
495 longhaul_table
[k
].index
= j
;
499 kfree(longhaul_table
);
503 for (j
= 0; j
< k
- 1; j
++) {
504 unsigned int min_f
, min_i
;
505 min_f
= longhaul_table
[j
].frequency
;
507 for (i
= j
+ 1; i
< k
; i
++) {
508 if (longhaul_table
[i
].frequency
< min_f
) {
509 min_f
= longhaul_table
[i
].frequency
;
514 swap(longhaul_table
[j
].frequency
,
515 longhaul_table
[min_i
].frequency
);
516 swap(longhaul_table
[j
].index
,
517 longhaul_table
[min_i
].index
);
521 longhaul_table
[k
].frequency
= CPUFREQ_TABLE_END
;
523 /* Find index we are running on */
524 for (j
= 0; j
< k
; j
++) {
525 if (mults
[longhaul_table
[j
].index
& 0x1f] == mult
) {
534 static void __init
longhaul_setup_voltagescaling(void)
536 union msr_longhaul longhaul
;
537 struct mV_pos minvid
, maxvid
, vid
;
538 unsigned int j
, speed
, pos
, kHz_step
, numvscales
;
541 rdmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
542 if (!(longhaul
.bits
.RevisionID
& 1)) {
543 printk(KERN_INFO PFX
"Voltage scaling not supported by CPU.\n");
547 if (!longhaul
.bits
.VRMRev
) {
548 printk(KERN_INFO PFX
"VRM 8.5\n");
549 vrm_mV_table
= &vrm85_mV
[0];
550 mV_vrm_table
= &mV_vrm85
[0];
552 printk(KERN_INFO PFX
"Mobile VRM\n");
553 if (cpu_model
< CPU_NEHEMIAH
)
555 vrm_mV_table
= &mobilevrm_mV
[0];
556 mV_vrm_table
= &mV_mobilevrm
[0];
559 minvid
= vrm_mV_table
[longhaul
.bits
.MinimumVID
];
560 maxvid
= vrm_mV_table
[longhaul
.bits
.MaximumVID
];
562 if (minvid
.mV
== 0 || maxvid
.mV
== 0 || minvid
.mV
> maxvid
.mV
) {
563 printk(KERN_INFO PFX
"Bogus values Min:%d.%03d Max:%d.%03d. "
564 "Voltage scaling disabled.\n",
565 minvid
.mV
/1000, minvid
.mV
%1000,
566 maxvid
.mV
/1000, maxvid
.mV
%1000);
570 if (minvid
.mV
== maxvid
.mV
) {
571 printk(KERN_INFO PFX
"Claims to support voltage scaling but "
572 "min & max are both %d.%03d. "
573 "Voltage scaling disabled\n",
574 maxvid
.mV
/1000, maxvid
.mV
%1000);
578 /* How many voltage steps*/
579 numvscales
= maxvid
.pos
- minvid
.pos
+ 1;
583 "%d possible voltage scales\n",
584 maxvid
.mV
/1000, maxvid
.mV
%1000,
585 minvid
.mV
/1000, minvid
.mV
%1000,
588 /* Calculate max frequency at min voltage */
589 j
= longhaul
.bits
.MinMHzBR
;
590 if (longhaul
.bits
.MinMHzBR4
)
592 min_vid_speed
= eblcr
[j
];
593 if (min_vid_speed
== -1)
595 switch (longhaul
.bits
.MinMHzFSB
) {
597 min_vid_speed
*= 13333;
600 min_vid_speed
*= 10000;
603 min_vid_speed
*= 6666;
609 if (min_vid_speed
>= highest_speed
)
611 /* Calculate kHz for one voltage step */
612 kHz_step
= (highest_speed
- min_vid_speed
) / numvscales
;
615 while (longhaul_table
[j
].frequency
!= CPUFREQ_TABLE_END
) {
616 speed
= longhaul_table
[j
].frequency
;
617 if (speed
> min_vid_speed
)
618 pos
= (speed
- min_vid_speed
) / kHz_step
+ minvid
.pos
;
621 longhaul_table
[j
].index
|= mV_vrm_table
[pos
] << 8;
622 vid
= vrm_mV_table
[mV_vrm_table
[pos
]];
623 printk(KERN_INFO PFX
"f: %d kHz, index: %d, vid: %d mV\n",
628 can_scale_voltage
= 1;
629 printk(KERN_INFO PFX
"Voltage scaling enabled.\n");
633 static int longhaul_verify(struct cpufreq_policy
*policy
)
635 return cpufreq_frequency_table_verify(policy
, longhaul_table
);
639 static int longhaul_target(struct cpufreq_policy
*policy
,
640 unsigned int target_freq
, unsigned int relation
)
642 unsigned int table_index
= 0;
644 unsigned int dir
= 0;
647 if (cpufreq_frequency_table_target(policy
, longhaul_table
, target_freq
,
648 relation
, &table_index
))
651 /* Don't set same frequency again */
652 if (longhaul_index
== table_index
)
655 if (!can_scale_voltage
)
656 longhaul_setstate(table_index
);
658 /* On test system voltage transitions exceeding single
659 * step up or down were turning motherboard off. Both
660 * "ondemand" and "userspace" are unsafe. C7 is doing
661 * this in hardware, C3 is old and we need to do this
664 current_vid
= (longhaul_table
[longhaul_index
].index
>> 8);
666 if (table_index
> longhaul_index
)
668 while (i
!= table_index
) {
669 vid
= (longhaul_table
[i
].index
>> 8) & 0x1f;
670 if (vid
!= current_vid
) {
671 longhaul_setstate(i
);
680 longhaul_setstate(table_index
);
682 longhaul_index
= table_index
;
687 static unsigned int longhaul_get(unsigned int cpu
)
691 return calc_speed(longhaul_get_cpu_mult());
694 static acpi_status
longhaul_walk_callback(acpi_handle obj_handle
,
696 void *context
, void **return_value
)
698 struct acpi_device
*d
;
700 if (acpi_bus_get_device(obj_handle
, &d
))
703 *return_value
= acpi_driver_data(d
);
707 /* VIA don't support PM2 reg, but have something similar */
708 static int enable_arbiter_disable(void)
715 /* Find PLE133 host bridge */
717 dev
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8601_0
,
719 /* Find PM133/VT8605 host bridge */
721 dev
= pci_get_device(PCI_VENDOR_ID_VIA
,
722 PCI_DEVICE_ID_VIA_8605_0
, NULL
);
723 /* Find CLE266 host bridge */
726 dev
= pci_get_device(PCI_VENDOR_ID_VIA
,
727 PCI_DEVICE_ID_VIA_862X_0
, NULL
);
728 /* Find CN400 V-Link host bridge */
730 dev
= pci_get_device(PCI_VENDOR_ID_VIA
, 0x7259, NULL
);
733 /* Enable access to port 0x22 */
734 pci_read_config_byte(dev
, reg
, &pci_cmd
);
735 if (!(pci_cmd
& 1<<7)) {
737 pci_write_config_byte(dev
, reg
, pci_cmd
);
738 pci_read_config_byte(dev
, reg
, &pci_cmd
);
739 if (!(pci_cmd
& 1<<7)) {
741 "Can't enable access to port 0x22.\n");
751 static int longhaul_setup_southbridge(void)
756 /* Find VT8235 southbridge */
757 dev
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, NULL
);
759 /* Find VT8237 southbridge */
760 dev
= pci_get_device(PCI_VENDOR_ID_VIA
,
761 PCI_DEVICE_ID_VIA_8237
, NULL
);
763 /* Set transition time to max */
764 pci_read_config_byte(dev
, 0xec, &pci_cmd
);
765 pci_cmd
&= ~(1 << 2);
766 pci_write_config_byte(dev
, 0xec, pci_cmd
);
767 pci_read_config_byte(dev
, 0xe4, &pci_cmd
);
768 pci_cmd
&= ~(1 << 7);
769 pci_write_config_byte(dev
, 0xe4, pci_cmd
);
770 pci_read_config_byte(dev
, 0xe5, &pci_cmd
);
772 pci_write_config_byte(dev
, 0xe5, pci_cmd
);
773 /* Get address of ACPI registers block*/
774 pci_read_config_byte(dev
, 0x81, &pci_cmd
);
775 if (pci_cmd
& 1 << 7) {
776 pci_read_config_dword(dev
, 0x88, &acpi_regs_addr
);
777 acpi_regs_addr
&= 0xff00;
778 printk(KERN_INFO PFX
"ACPI I/O at 0x%x\n",
788 static int __init
longhaul_cpu_init(struct cpufreq_policy
*policy
)
790 struct cpuinfo_x86
*c
= &cpu_data(0);
791 char *cpuname
= NULL
;
795 /* Check what we have on this motherboard */
796 switch (c
->x86_model
) {
798 cpu_model
= CPU_SAMUEL
;
799 cpuname
= "C3 'Samuel' [C5A]";
800 longhaul_version
= TYPE_LONGHAUL_V1
;
801 memcpy(mults
, samuel1_mults
, sizeof(samuel1_mults
));
802 memcpy(eblcr
, samuel1_eblcr
, sizeof(samuel1_eblcr
));
806 switch (c
->x86_mask
) {
808 longhaul_version
= TYPE_LONGHAUL_V1
;
809 cpu_model
= CPU_SAMUEL2
;
810 cpuname
= "C3 'Samuel 2' [C5B]";
811 /* Note, this is not a typo, early Samuel2's had
813 memcpy(mults
, samuel1_mults
, sizeof(samuel1_mults
));
814 memcpy(eblcr
, samuel2_eblcr
, sizeof(samuel2_eblcr
));
817 longhaul_version
= TYPE_LONGHAUL_V1
;
818 if (c
->x86_mask
< 8) {
819 cpu_model
= CPU_SAMUEL2
;
820 cpuname
= "C3 'Samuel 2' [C5B]";
822 cpu_model
= CPU_EZRA
;
823 cpuname
= "C3 'Ezra' [C5C]";
825 memcpy(mults
, ezra_mults
, sizeof(ezra_mults
));
826 memcpy(eblcr
, ezra_eblcr
, sizeof(ezra_eblcr
));
832 cpu_model
= CPU_EZRA_T
;
833 cpuname
= "C3 'Ezra-T' [C5M]";
834 longhaul_version
= TYPE_POWERSAVER
;
836 memcpy(mults
, ezrat_mults
, sizeof(ezrat_mults
));
837 memcpy(eblcr
, ezrat_eblcr
, sizeof(ezrat_eblcr
));
841 longhaul_version
= TYPE_POWERSAVER
;
843 memcpy(mults
, nehemiah_mults
, sizeof(nehemiah_mults
));
844 memcpy(eblcr
, nehemiah_eblcr
, sizeof(nehemiah_eblcr
));
845 switch (c
->x86_mask
) {
847 cpu_model
= CPU_NEHEMIAH
;
848 cpuname
= "C3 'Nehemiah A' [C5XLOE]";
851 cpu_model
= CPU_NEHEMIAH
;
852 cpuname
= "C3 'Nehemiah B' [C5XLOH]";
855 cpu_model
= CPU_NEHEMIAH_C
;
856 cpuname
= "C3 'Nehemiah C' [C5P]";
865 /* Check Longhaul ver. 2 */
866 if (longhaul_version
== TYPE_LONGHAUL_V2
) {
867 rdmsr(MSR_VIA_LONGHAUL
, lo
, hi
);
868 if (lo
== 0 && hi
== 0)
869 /* Looks like MSR isn't present */
870 longhaul_version
= TYPE_LONGHAUL_V1
;
873 printk(KERN_INFO PFX
"VIA %s CPU detected. ", cpuname
);
874 switch (longhaul_version
) {
875 case TYPE_LONGHAUL_V1
:
876 case TYPE_LONGHAUL_V2
:
877 printk(KERN_CONT
"Longhaul v%d supported.\n", longhaul_version
);
879 case TYPE_POWERSAVER
:
880 printk(KERN_CONT
"Powersaver supported.\n");
885 longhaul_setup_southbridge();
887 /* Find ACPI data for processor */
888 acpi_walk_namespace(ACPI_TYPE_PROCESSOR
, ACPI_ROOT_OBJECT
,
889 ACPI_UINT32_MAX
, &longhaul_walk_callback
,
892 /* Check ACPI support for C3 state */
893 if (pr
!= NULL
&& longhaul_version
== TYPE_POWERSAVER
) {
894 cx
= &pr
->power
.states
[ACPI_STATE_C3
];
895 if (cx
->address
> 0 && cx
->latency
<= 1000)
896 longhaul_flags
|= USE_ACPI_C3
;
898 /* Disable if it isn't working */
900 longhaul_flags
&= ~USE_ACPI_C3
;
901 /* Check if northbridge is friendly */
902 if (enable_arbiter_disable())
903 longhaul_flags
|= USE_NORTHBRIDGE
;
905 /* Check ACPI support for bus master arbiter disable */
906 if (!(longhaul_flags
& USE_ACPI_C3
907 || longhaul_flags
& USE_NORTHBRIDGE
)
908 && ((pr
== NULL
) || !(pr
->flags
.bm_control
))) {
910 "No ACPI support. Unsupported northbridge.\n");
914 if (longhaul_flags
& USE_NORTHBRIDGE
)
915 printk(KERN_INFO PFX
"Using northbridge support.\n");
916 if (longhaul_flags
& USE_ACPI_C3
)
917 printk(KERN_INFO PFX
"Using ACPI support.\n");
919 ret
= longhaul_get_ranges();
923 if ((longhaul_version
!= TYPE_LONGHAUL_V1
) && (scale_voltage
!= 0))
924 longhaul_setup_voltagescaling();
926 policy
->cpuinfo
.transition_latency
= 200000; /* nsec */
927 policy
->cur
= calc_speed(longhaul_get_cpu_mult());
929 ret
= cpufreq_frequency_table_cpuinfo(policy
, longhaul_table
);
933 cpufreq_frequency_table_get_attr(longhaul_table
, policy
->cpu
);
938 static int __devexit
longhaul_cpu_exit(struct cpufreq_policy
*policy
)
940 cpufreq_frequency_table_put_attr(policy
->cpu
);
944 static struct freq_attr
*longhaul_attr
[] = {
945 &cpufreq_freq_attr_scaling_available_freqs
,
949 static struct cpufreq_driver longhaul_driver
= {
950 .verify
= longhaul_verify
,
951 .target
= longhaul_target
,
953 .init
= longhaul_cpu_init
,
954 .exit
= __devexit_p(longhaul_cpu_exit
),
956 .owner
= THIS_MODULE
,
957 .attr
= longhaul_attr
,
961 static int __init
longhaul_init(void)
963 struct cpuinfo_x86
*c
= &cpu_data(0);
965 if (c
->x86_vendor
!= X86_VENDOR_CENTAUR
|| c
->x86
!= 6)
969 if (num_online_cpus() > 1) {
970 printk(KERN_ERR PFX
"More than 1 CPU detected, "
971 "longhaul disabled.\n");
975 #ifdef CONFIG_X86_IO_APIC
977 printk(KERN_ERR PFX
"APIC detected. Longhaul is currently "
978 "broken in this configuration.\n");
982 switch (c
->x86_model
) {
984 return cpufreq_register_driver(&longhaul_driver
);
986 printk(KERN_ERR PFX
"Use acpi-cpufreq driver for VIA C7\n");
995 static void __exit
longhaul_exit(void)
999 for (i
= 0; i
< numscales
; i
++) {
1000 if (mults
[i
] == maxmult
) {
1001 longhaul_setstate(i
);
1006 cpufreq_unregister_driver(&longhaul_driver
);
1007 kfree(longhaul_table
);
1010 /* Even if BIOS is exporting ACPI C3 state, and it is used
1011 * with success when CPU is idle, this state doesn't
1012 * trigger frequency transition in some cases. */
1013 module_param(disable_acpi_c3
, int, 0644);
1014 MODULE_PARM_DESC(disable_acpi_c3
, "Don't use ACPI C3 support");
1015 /* Change CPU voltage with frequency. Very usefull to save
1016 * power, but most VIA C3 processors aren't supporting it. */
1017 module_param(scale_voltage
, int, 0644);
1018 MODULE_PARM_DESC(scale_voltage
, "Scale voltage of processor");
1019 /* Force revision key to 0 for processors which doesn't
1020 * support voltage scaling, but are introducing itself as
1022 module_param(revid_errata
, int, 0644);
1023 MODULE_PARM_DESC(revid_errata
, "Ignore CPU Revision ID");
1025 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1026 MODULE_DESCRIPTION("Longhaul driver for VIA Cyrix processors.");
1027 MODULE_LICENSE("GPL");
1029 late_initcall(longhaul_init
);
1030 module_exit(longhaul_exit
);