arch/x86/kernel/cpu/cyrix.c

   1 #include <linux/bitops.h>
   2 #include <linux/delay.h>
   3 #include <linux/pci.h>
   4 #include <asm/dma.h>
   5 #include <linux/io.h>
   6 #include <asm/processor-cyrix.h>
   7 #include <asm/processor-flags.h>
   8 #include <linux/timer.h>
   9 #include <asm/pci-direct.h>
  10 #include <asm/tsc.h>
  11 #include <asm/cpufeature.h>
  12 #include <linux/sched.h>
  13
  14 #include "cpu.h"
  15
  16 /*
  17  * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
  18  */
  19 static void __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
  20 {
  21         unsigned char ccr2, ccr3;
  22
  23         /* we test for DEVID by checking whether CCR3 is writable */
  24         ccr3 = getCx86(CX86_CCR3);
  25         setCx86(CX86_CCR3, ccr3 ^ 0x80);
  26         getCx86(0xc0);   /* dummy to change bus */
  27
  28         if (getCx86(CX86_CCR3) == ccr3) {       /* no DEVID regs. */
  29                 ccr2 = getCx86(CX86_CCR2);
  30                 setCx86(CX86_CCR2, ccr2 ^ 0x04);
  31                 getCx86(0xc0);  /* dummy */
  32
  33                 if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
  34                         *dir0 = 0xfd;
  35                 else {                          /* Cx486S A step */
  36                         setCx86(CX86_CCR2, ccr2);
  37                         *dir0 = 0xfe;
  38                 }
  39         } else {
  40                 setCx86(CX86_CCR3, ccr3);  /* restore CCR3 */
  41
  42                 /* read DIR0 and DIR1 CPU registers */
  43                 *dir0 = getCx86(CX86_DIR0);
  44                 *dir1 = getCx86(CX86_DIR1);
  45         }
  46 }
  47
  48 static void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
  49 {
  50         unsigned long flags;
  51
  52         local_irq_save(flags);
  53         __do_cyrix_devid(dir0, dir1);
  54         local_irq_restore(flags);
  55 }
  56 /*
  57  * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
  58  * order to identify the Cyrix CPU model after we're out of setup.c
  59  *
  60  * Actually since bugs.h doesn't even reference this perhaps someone should
  61  * fix the documentation ???
  62  */
  63 static unsigned char Cx86_dir0_msb = 0;
  64
  65 static const char Cx86_model[][9] = {
  66         "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
  67         "M II ", "Unknown"
  68 };
  69 static const char Cx486_name[][5] = {
  70         "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
  71         "SRx2", "DRx2"
  72 };
  73 static const char Cx486S_name[][4] = {
  74         "S", "S2", "Se", "S2e"
  75 };
  76 static const char Cx486D_name[][4] = {
  77         "DX", "DX2", "?", "?", "?", "DX4"
  78 };
  79 static char Cx86_cb[] = "?.5x Core/Bus Clock";
  80 static const char cyrix_model_mult1[] = "12??43";
  81 static const char cyrix_model_mult2[] = "12233445";
  82
  83 /*
  84  * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
  85  * BIOSes for compatibility with DOS games.  This makes the udelay loop
  86  * work correctly, and improves performance.
  87  *
  88  * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
  89  */
  90
  91 static void check_cx686_slop(struct cpuinfo_x86 *c)
  92 {
  93         unsigned long flags;
  94
  95         if (Cx86_dir0_msb == 3) {
  96                 unsigned char ccr3, ccr5;
  97
  98                 local_irq_save(flags);
  99                 ccr3 = getCx86(CX86_CCR3);
 100                 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
 101                 ccr5 = getCx86(CX86_CCR5);
 102                 if (ccr5 & 2)
 103                         setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
 104                 setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
 105                 local_irq_restore(flags);
 106
 107                 if (ccr5 & 2) { /* possible wrong calibration done */
 108                         pr_info("Recalibrating delay loop with SLOP bit reset\n");
 109                         calibrate_delay();
 110                         c->loops_per_jiffy = loops_per_jiffy;
 111                 }
 112         }
 113 }
 114
 115
 116 static void set_cx86_reorder(void)
 117 {
 118         u8 ccr3;
 119
 120         pr_info("Enable Memory access reorder on Cyrix/NSC processor.\n");
 121         ccr3 = getCx86(CX86_CCR3);
 122         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
 123
 124         /* Load/Store Serialize to mem access disable (=reorder it) */
 125         setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);
 126         /* set load/store serialize from 1GB to 4GB */
 127         ccr3 |= 0xe0;
 128         setCx86(CX86_CCR3, ccr3);
 129 }
 130
 131 static void set_cx86_memwb(void)
 132 {
 133         pr_info("Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
 134
 135         /* CCR2 bit 2: unlock NW bit */
 136         setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);
 137         /* set 'Not Write-through' */
 138         write_cr0(read_cr0() | X86_CR0_NW);
 139         /* CCR2 bit 2: lock NW bit and set WT1 */
 140         setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14);
 141 }
 142
 143 /*
 144  *      Configure later MediaGX and/or Geode processor.
 145  */
 146
 147 static void geode_configure(void)
 148 {
 149         unsigned long flags;
 150         u8 ccr3;
 151         local_irq_save(flags);
 152
 153         /* Suspend on halt power saving and enable #SUSP pin */
 154         setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x88);
 155
 156         ccr3 = getCx86(CX86_CCR3);
 157         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN */
 158
 159
 160         /* FPU fast, DTE cache, Mem bypass */
 161         setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x38);
 162         setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
 163
 164         set_cx86_memwb();
 165         set_cx86_reorder();
 166
 167         local_irq_restore(flags);
 168 }
 169
 170 static void early_init_cyrix(struct cpuinfo_x86 *c)
 171 {
 172         unsigned char dir0, dir0_msn, dir1 = 0;
 173
 174         __do_cyrix_devid(&dir0, &dir1);
 175         dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
 176
 177         switch (dir0_msn) {
 178         case 3: /* 6x86/6x86L */
 179                 /* Emulate MTRRs using Cyrix's ARRs. */
 180                 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
 181                 break;
 182         case 5: /* 6x86MX/M II */
 183                 /* Emulate MTRRs using Cyrix's ARRs. */
 184                 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
 185                 break;
 186         }
 187         clear_sched_clock_stable();
 188 }
 189
 190 static void init_cyrix(struct cpuinfo_x86 *c)
 191 {
 192         unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
 193         char *buf = c->x86_model_id;
 194         const char *p = NULL;
 195
 196         /*
 197          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 198          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
 199          */
 200         clear_cpu_cap(c, 0*32+31);
 201
 202         /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
 203         if (test_cpu_cap(c, 1*32+24)) {
 204                 clear_cpu_cap(c, 1*32+24);
 205                 set_cpu_cap(c, X86_FEATURE_CXMMX);
 206         }
 207
 208         do_cyrix_devid(&dir0, &dir1);
 209
 210         check_cx686_slop(c);
 211
 212         Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
 213         dir0_lsn = dir0 & 0xf;                /* model or clock multiplier */
 214
 215         /* common case step number/rev -- exceptions handled below */
 216         c->x86_model = (dir1 >> 4) + 1;
 217         c->x86_mask = dir1 & 0xf;
 218
 219         /* Now cook; the original recipe is by Channing Corn, from Cyrix.
 220          * We do the same thing for each generation: we work out
 221          * the model, multiplier and stepping.  Black magic included,
 222          * to make the silicon step/rev numbers match the printed ones.
 223          */
 224
 225         switch (dir0_msn) {
 226                 unsigned char tmp;
 227
 228         case 0: /* Cx486SLC/DLC/SRx/DRx */
 229                 p = Cx486_name[dir0_lsn & 7];
 230                 break;
 231
 232         case 1: /* Cx486S/DX/DX2/DX4 */
 233                 p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
 234                         : Cx486S_name[dir0_lsn & 3];
 235                 break;
 236
 237         case 2: /* 5x86 */
 238                 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
 239                 p = Cx86_cb+2;
 240                 break;
 241
 242         case 3: /* 6x86/6x86L */
 243                 Cx86_cb[1] = ' ';
 244                 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
 245                 if (dir1 > 0x21) { /* 686L */
 246                         Cx86_cb[0] = 'L';
 247                         p = Cx86_cb;
 248                         (c->x86_model)++;
 249                 } else             /* 686 */
 250                         p = Cx86_cb+1;
 251                 /* Emulate MTRRs using Cyrix's ARRs. */
 252                 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
 253                 /* 6x86's contain this bug */
 254                 set_cpu_bug(c, X86_BUG_COMA);
 255                 break;
 256
 257         case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
 258 #ifdef CONFIG_PCI
 259         {
 260                 u32 vendor, device;
 261                 /*
 262                  * It isn't really a PCI quirk directly, but the cure is the
 263                  * same. The MediaGX has deep magic SMM stuff that handles the
 264                  * SB emulation. It throws away the fifo on disable_dma() which
 265                  * is wrong and ruins the audio.
 266                  *
 267                  *  Bug2: VSA1 has a wrap bug so that using maximum sized DMA
 268                  *  causes bad things. According to NatSemi VSA2 has another
 269                  *  bug to do with 'hlt'. I've not seen any boards using VSA2
 270                  *  and X doesn't seem to support it either so who cares 8).
 271                  *  VSA1 we work around however.
 272                  */
 273
 274                 pr_info("Working around Cyrix MediaGX virtual DMA bugs.\n");
 275                 isa_dma_bridge_buggy = 2;
 276
 277                 /* We do this before the PCI layer is running. However we
 278                    are safe here as we know the bridge must be a Cyrix
 279                    companion and must be present */
 280                 vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
 281                 device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);
 282
 283                 /*
 284                  *  The 5510/5520 companion chips have a funky PIT.
 285                  */
 286                 if (vendor == PCI_VENDOR_ID_CYRIX &&
 287                         (device == PCI_DEVICE_ID_CYRIX_5510 ||
 288                                         device == PCI_DEVICE_ID_CYRIX_5520))
 289                         mark_tsc_unstable("cyrix 5510/5520 detected");
 290         }
 291 #endif
 292                 c->x86_cache_size = 16; /* Yep 16K integrated cache thats it */
 293
 294                 /* GXm supports extended cpuid levels 'ala' AMD */
 295                 if (c->cpuid_level == 2) {
 296                         /* Enable cxMMX extensions (GX1 Datasheet 54) */
 297                         setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) | 1);
 298
 299                         /*
 300                          * GXm : 0x30 ... 0x5f GXm  datasheet 51
 301                          * GXlv: 0x6x          GXlv datasheet 54
 302                          *  ?  : 0x7x
 303                          * GX1 : 0x8x          GX1  datasheet 56
 304                          */
 305                         if ((0x30 <= dir1 && dir1 <= 0x6f) ||
 306                                         (0x80 <= dir1 && dir1 <= 0x8f))
 307                                 geode_configure();
 308                         return;
 309                 } else { /* MediaGX */
 310                         Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
 311                         p = Cx86_cb+2;
 312                         c->x86_model = (dir1 & 0x20) ? 1 : 2;
 313                 }
 314                 break;
 315
 316         case 5: /* 6x86MX/M II */
 317                 if (dir1 > 7) {
 318                         dir0_msn++;  /* M II */
 319                         /* Enable MMX extensions (App note 108) */
 320                         setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1);
 321                 } else {
 322                         /* A 6x86MX - it has the bug. */
 323                         set_cpu_bug(c, X86_BUG_COMA);
 324                 }
 325                 tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
 326                 Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
 327                 p = Cx86_cb+tmp;
 328                 if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
 329                         (c->x86_model)++;
 330                 /* Emulate MTRRs using Cyrix's ARRs. */
 331                 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
 332                 break;
 333
 334         case 0xf:  /* Cyrix 486 without DEVID registers */
 335                 switch (dir0_lsn) {
 336                 case 0xd:  /* either a 486SLC or DLC w/o DEVID */
 337                         dir0_msn = 0;
 338                         p = Cx486_name[!!boot_cpu_has(X86_FEATURE_FPU)];
 339                         break;
 340
 341                 case 0xe:  /* a 486S A step */
 342                         dir0_msn = 0;
 343                         p = Cx486S_name[0];
 344                         break;
 345                 }
 346                 break;
 347
 348         default:  /* unknown (shouldn't happen, we know everyone ;-) */
 349                 dir0_msn = 7;
 350                 break;
 351         }
 352         strcpy(buf, Cx86_model[dir0_msn & 7]);
 353         if (p)
 354                 strcat(buf, p);
 355         return;
 356 }
 357
 358 /*
 359  * Handle National Semiconductor branded processors
 360  */
 361 static void init_nsc(struct cpuinfo_x86 *c)
 362 {
 363         /*
 364          * There may be GX1 processors in the wild that are branded
 365          * NSC and not Cyrix.
 366          *
 367          * This function only handles the GX processor, and kicks every
 368          * thing else to the Cyrix init function above - that should
 369          * cover any processors that might have been branded differently
 370          * after NSC acquired Cyrix.
 371          *
 372          * If this breaks your GX1 horribly, please e-mail
 373          * info-linux@ldcmail.amd.com to tell us.
 374          */
 375
 376         /* Handle the GX (Formally known as the GX2) */
 377
 378         if (c->x86 == 5 && c->x86_model == 5)
 379                 cpu_detect_cache_sizes(c);
 380         else
 381                 init_cyrix(c);
 382 }
 383
 384 /*
 385  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
 386  * by the fact that they preserve the flags across the division of 5/2.
 387  * PII and PPro exhibit this behavior too, but they have cpuid available.
 388  */
 389
 390 /*
 391  * Perform the Cyrix 5/2 test. A Cyrix won't change
 392  * the flags, while other 486 chips will.
 393  */
 394 static inline int test_cyrix_52div(void)
 395 {
 396         unsigned int test;
 397
 398         __asm__ __volatile__(
 399              "sahf\n\t"         /* clear flags (%eax = 0x0005) */
 400              "div %b2\n\t"      /* divide 5 by 2 */
 401              "lahf"             /* store flags into %ah */
 402              : "=a" (test)
 403              : "0" (5), "q" (2)
 404              : "cc");
 405
 406         /* AH is 0x02 on Cyrix after the divide.. */
 407         return (unsigned char) (test >> 8) == 0x02;
 408 }
 409
 410 static void cyrix_identify(struct cpuinfo_x86 *c)
 411 {
 412         /* Detect Cyrix with disabled CPUID */
 413         if (c->x86 == 4 && test_cyrix_52div()) {
 414                 unsigned char dir0, dir1;
 415
 416                 strcpy(c->x86_vendor_id, "CyrixInstead");
 417                 c->x86_vendor = X86_VENDOR_CYRIX;
 418
 419                 /* Actually enable cpuid on the older cyrix */
 420
 421                 /* Retrieve CPU revisions */
 422
 423                 do_cyrix_devid(&dir0, &dir1);
 424
 425                 dir0 >>= 4;
 426
 427                 /* Check it is an affected model */
 428
 429                 if (dir0 == 5 || dir0 == 3) {
 430                         unsigned char ccr3;
 431                         unsigned long flags;
 432                         pr_info("Enabling CPUID on Cyrix processor.\n");
 433                         local_irq_save(flags);
 434                         ccr3 = getCx86(CX86_CCR3);
 435                         /* enable MAPEN  */
 436                         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
 437                         /* enable cpuid  */
 438                         setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80);
 439                         /* disable MAPEN */
 440                         setCx86(CX86_CCR3, ccr3);
 441                         local_irq_restore(flags);
 442                 }
 443         }
 444 }
 445
 446 static const struct cpu_dev cyrix_cpu_dev = {
 447         .c_vendor       = "Cyrix",
 448         .c_ident        = { "CyrixInstead" },
 449         .c_early_init   = early_init_cyrix,
 450         .c_init         = init_cyrix,
 451         .c_identify     = cyrix_identify,
 452         .c_x86_vendor   = X86_VENDOR_CYRIX,
 453 };
 454
 455 cpu_dev_register(cyrix_cpu_dev);
 456
 457 static const struct cpu_dev nsc_cpu_dev = {
 458         .c_vendor       = "NSC",
 459         .c_ident        = { "Geode by NSC" },
 460         .c_init         = init_nsc,
 461         .c_x86_vendor   = X86_VENDOR_NSC,
 462 };
 463
 464 cpu_dev_register(nsc_cpu_dev);