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Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi into...
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / intel.c
1 #include <linux/kernel.h>
2
3 #include <linux/string.h>
4 #include <linux/bitops.h>
5 #include <linux/smp.h>
6 #include <linux/sched.h>
7 #include <linux/sched/clock.h>
8 #include <linux/thread_info.h>
9 #include <linux/init.h>
10 #include <linux/uaccess.h>
11
12 #include <asm/cpufeature.h>
13 #include <asm/pgtable.h>
14 #include <asm/msr.h>
15 #include <asm/bugs.h>
16 #include <asm/cpu.h>
17 #include <asm/intel-family.h>
18 #include <asm/microcode_intel.h>
19 #include <asm/hwcap2.h>
20 #include <asm/elf.h>
21
22 #ifdef CONFIG_X86_64
23 #include <linux/topology.h>
24 #endif
25
26 #include "cpu.h"
27
28 #ifdef CONFIG_X86_LOCAL_APIC
29 #include <asm/mpspec.h>
30 #include <asm/apic.h>
31 #endif
32
33 /*
34 * Just in case our CPU detection goes bad, or you have a weird system,
35 * allow a way to override the automatic disabling of MPX.
36 */
37 static int forcempx;
38
39 static int __init forcempx_setup(char *__unused)
40 {
41 forcempx = 1;
42
43 return 1;
44 }
45 __setup("intel-skd-046-workaround=disable", forcempx_setup);
46
47 void check_mpx_erratum(struct cpuinfo_x86 *c)
48 {
49 if (forcempx)
50 return;
51 /*
52 * Turn off the MPX feature on CPUs where SMEP is not
53 * available or disabled.
54 *
55 * Works around Intel Erratum SKD046: "Branch Instructions
56 * May Initialize MPX Bound Registers Incorrectly".
57 *
58 * This might falsely disable MPX on systems without
59 * SMEP, like Atom processors without SMEP. But there
60 * is no such hardware known at the moment.
61 */
62 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
63 setup_clear_cpu_cap(X86_FEATURE_MPX);
64 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
65 }
66 }
67
68 static bool ring3mwait_disabled __read_mostly;
69
70 static int __init ring3mwait_disable(char *__unused)
71 {
72 ring3mwait_disabled = true;
73 return 0;
74 }
75 __setup("ring3mwait=disable", ring3mwait_disable);
76
77 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
78 {
79 /*
80 * Ring 3 MONITOR/MWAIT feature cannot be detected without
81 * cpu model and family comparison.
82 */
83 if (c->x86 != 6)
84 return;
85 switch (c->x86_model) {
86 case INTEL_FAM6_XEON_PHI_KNL:
87 case INTEL_FAM6_XEON_PHI_KNM:
88 break;
89 default:
90 return;
91 }
92
93 if (ring3mwait_disabled) {
94 msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
95 MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
96 return;
97 }
98
99 msr_set_bit(MSR_MISC_FEATURE_ENABLES,
100 MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
101
102 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
103
104 if (c == &boot_cpu_data)
105 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
106 }
107
108 static void early_init_intel(struct cpuinfo_x86 *c)
109 {
110 u64 misc_enable;
111
112 /* Unmask CPUID levels if masked: */
113 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
114 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
115 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
116 c->cpuid_level = cpuid_eax(0);
117 get_cpu_cap(c);
118 }
119 }
120
121 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
122 (c->x86 == 0x6 && c->x86_model >= 0x0e))
123 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
124
125 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
126 c->microcode = intel_get_microcode_revision();
127
128 /*
129 * Atom erratum AAE44/AAF40/AAG38/AAH41:
130 *
131 * A race condition between speculative fetches and invalidating
132 * a large page. This is worked around in microcode, but we
133 * need the microcode to have already been loaded... so if it is
134 * not, recommend a BIOS update and disable large pages.
135 */
136 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
137 c->microcode < 0x20e) {
138 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
139 clear_cpu_cap(c, X86_FEATURE_PSE);
140 }
141
142 #ifdef CONFIG_X86_64
143 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
144 #else
145 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
146 if (c->x86 == 15 && c->x86_cache_alignment == 64)
147 c->x86_cache_alignment = 128;
148 #endif
149
150 /* CPUID workaround for 0F33/0F34 CPU */
151 if (c->x86 == 0xF && c->x86_model == 0x3
152 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
153 c->x86_phys_bits = 36;
154
155 /*
156 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
157 * with P/T states and does not stop in deep C-states.
158 *
159 * It is also reliable across cores and sockets. (but not across
160 * cabinets - we turn it off in that case explicitly.)
161 */
162 if (c->x86_power & (1 << 8)) {
163 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
164 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
165 }
166
167 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
168 if (c->x86 == 6) {
169 switch (c->x86_model) {
170 case 0x27: /* Penwell */
171 case 0x35: /* Cloverview */
172 case 0x4a: /* Merrifield */
173 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
174 break;
175 default:
176 break;
177 }
178 }
179
180 /*
181 * There is a known erratum on Pentium III and Core Solo
182 * and Core Duo CPUs.
183 * " Page with PAT set to WC while associated MTRR is UC
184 * may consolidate to UC "
185 * Because of this erratum, it is better to stick with
186 * setting WC in MTRR rather than using PAT on these CPUs.
187 *
188 * Enable PAT WC only on P4, Core 2 or later CPUs.
189 */
190 if (c->x86 == 6 && c->x86_model < 15)
191 clear_cpu_cap(c, X86_FEATURE_PAT);
192
193 #ifdef CONFIG_KMEMCHECK
194 /*
195 * P4s have a "fast strings" feature which causes single-
196 * stepping REP instructions to only generate a #DB on
197 * cache-line boundaries.
198 *
199 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
200 * (model 2) with the same problem.
201 */
202 if (c->x86 == 15)
203 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
204 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
205 pr_info("kmemcheck: Disabling fast string operations\n");
206 #endif
207
208 /*
209 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
210 * clear the fast string and enhanced fast string CPU capabilities.
211 */
212 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
213 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
214 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
215 pr_info("Disabled fast string operations\n");
216 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
217 setup_clear_cpu_cap(X86_FEATURE_ERMS);
218 }
219 }
220
221 /*
222 * Intel Quark Core DevMan_001.pdf section 6.4.11
223 * "The operating system also is required to invalidate (i.e., flush)
224 * the TLB when any changes are made to any of the page table entries.
225 * The operating system must reload CR3 to cause the TLB to be flushed"
226 *
227 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
228 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
229 * to be modified.
230 */
231 if (c->x86 == 5 && c->x86_model == 9) {
232 pr_info("Disabling PGE capability bit\n");
233 setup_clear_cpu_cap(X86_FEATURE_PGE);
234 }
235
236 if (c->cpuid_level >= 0x00000001) {
237 u32 eax, ebx, ecx, edx;
238
239 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
240 /*
241 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
242 * apicids which are reserved per package. Store the resulting
243 * shift value for the package management code.
244 */
245 if (edx & (1U << 28))
246 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
247 }
248
249 check_mpx_erratum(c);
250 }
251
252 #ifdef CONFIG_X86_32
253 /*
254 * Early probe support logic for ppro memory erratum #50
255 *
256 * This is called before we do cpu ident work
257 */
258
259 int ppro_with_ram_bug(void)
260 {
261 /* Uses data from early_cpu_detect now */
262 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
263 boot_cpu_data.x86 == 6 &&
264 boot_cpu_data.x86_model == 1 &&
265 boot_cpu_data.x86_mask < 8) {
266 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
267 return 1;
268 }
269 return 0;
270 }
271
272 static void intel_smp_check(struct cpuinfo_x86 *c)
273 {
274 /* calling is from identify_secondary_cpu() ? */
275 if (!c->cpu_index)
276 return;
277
278 /*
279 * Mask B, Pentium, but not Pentium MMX
280 */
281 if (c->x86 == 5 &&
282 c->x86_mask >= 1 && c->x86_mask <= 4 &&
283 c->x86_model <= 3) {
284 /*
285 * Remember we have B step Pentia with bugs
286 */
287 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
288 "with B stepping processors.\n");
289 }
290 }
291
292 static int forcepae;
293 static int __init forcepae_setup(char *__unused)
294 {
295 forcepae = 1;
296 return 1;
297 }
298 __setup("forcepae", forcepae_setup);
299
300 static void intel_workarounds(struct cpuinfo_x86 *c)
301 {
302 #ifdef CONFIG_X86_F00F_BUG
303 /*
304 * All models of Pentium and Pentium with MMX technology CPUs
305 * have the F0 0F bug, which lets nonprivileged users lock up the
306 * system. Announce that the fault handler will be checking for it.
307 * The Quark is also family 5, but does not have the same bug.
308 */
309 clear_cpu_bug(c, X86_BUG_F00F);
310 if (c->x86 == 5 && c->x86_model < 9) {
311 static int f00f_workaround_enabled;
312
313 set_cpu_bug(c, X86_BUG_F00F);
314 if (!f00f_workaround_enabled) {
315 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
316 f00f_workaround_enabled = 1;
317 }
318 }
319 #endif
320
321 /*
322 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
323 * model 3 mask 3
324 */
325 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
326 clear_cpu_cap(c, X86_FEATURE_SEP);
327
328 /*
329 * PAE CPUID issue: many Pentium M report no PAE but may have a
330 * functionally usable PAE implementation.
331 * Forcefully enable PAE if kernel parameter "forcepae" is present.
332 */
333 if (forcepae) {
334 pr_warn("PAE forced!\n");
335 set_cpu_cap(c, X86_FEATURE_PAE);
336 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
337 }
338
339 /*
340 * P4 Xeon erratum 037 workaround.
341 * Hardware prefetcher may cause stale data to be loaded into the cache.
342 */
343 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
344 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
345 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
346 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
347 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
348 }
349 }
350
351 /*
352 * See if we have a good local APIC by checking for buggy Pentia,
353 * i.e. all B steppings and the C2 stepping of P54C when using their
354 * integrated APIC (see 11AP erratum in "Pentium Processor
355 * Specification Update").
356 */
357 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
358 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
359 set_cpu_bug(c, X86_BUG_11AP);
360
361
362 #ifdef CONFIG_X86_INTEL_USERCOPY
363 /*
364 * Set up the preferred alignment for movsl bulk memory moves
365 */
366 switch (c->x86) {
367 case 4: /* 486: untested */
368 break;
369 case 5: /* Old Pentia: untested */
370 break;
371 case 6: /* PII/PIII only like movsl with 8-byte alignment */
372 movsl_mask.mask = 7;
373 break;
374 case 15: /* P4 is OK down to 8-byte alignment */
375 movsl_mask.mask = 7;
376 break;
377 }
378 #endif
379
380 intel_smp_check(c);
381 }
382 #else
383 static void intel_workarounds(struct cpuinfo_x86 *c)
384 {
385 }
386 #endif
387
388 static void srat_detect_node(struct cpuinfo_x86 *c)
389 {
390 #ifdef CONFIG_NUMA
391 unsigned node;
392 int cpu = smp_processor_id();
393
394 /* Don't do the funky fallback heuristics the AMD version employs
395 for now. */
396 node = numa_cpu_node(cpu);
397 if (node == NUMA_NO_NODE || !node_online(node)) {
398 /* reuse the value from init_cpu_to_node() */
399 node = cpu_to_node(cpu);
400 }
401 numa_set_node(cpu, node);
402 #endif
403 }
404
405 /*
406 * find out the number of processor cores on the die
407 */
408 static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
409 {
410 unsigned int eax, ebx, ecx, edx;
411
412 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
413 return 1;
414
415 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
416 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
417 if (eax & 0x1f)
418 return (eax >> 26) + 1;
419 else
420 return 1;
421 }
422
423 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
424 {
425 /* Intel VMX MSR indicated features */
426 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
427 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
428 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
429 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
430 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
431 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
432
433 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
434
435 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
436 clear_cpu_cap(c, X86_FEATURE_VNMI);
437 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
438 clear_cpu_cap(c, X86_FEATURE_EPT);
439 clear_cpu_cap(c, X86_FEATURE_VPID);
440
441 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
442 msr_ctl = vmx_msr_high | vmx_msr_low;
443 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
444 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
445 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
446 set_cpu_cap(c, X86_FEATURE_VNMI);
447 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
448 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
449 vmx_msr_low, vmx_msr_high);
450 msr_ctl2 = vmx_msr_high | vmx_msr_low;
451 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
452 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
453 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
454 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
455 set_cpu_cap(c, X86_FEATURE_EPT);
456 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
457 set_cpu_cap(c, X86_FEATURE_VPID);
458 }
459 }
460
461 static void init_intel_energy_perf(struct cpuinfo_x86 *c)
462 {
463 u64 epb;
464
465 /*
466 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
467 * (x86_energy_perf_policy(8) is available to change it at run-time.)
468 */
469 if (!cpu_has(c, X86_FEATURE_EPB))
470 return;
471
472 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
473 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
474 return;
475
476 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
477 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
478 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
479 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
480 }
481
482 static void intel_bsp_resume(struct cpuinfo_x86 *c)
483 {
484 /*
485 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
486 * so reinitialize it properly like during bootup:
487 */
488 init_intel_energy_perf(c);
489 }
490
491 static void init_intel(struct cpuinfo_x86 *c)
492 {
493 unsigned int l2 = 0;
494
495 early_init_intel(c);
496
497 intel_workarounds(c);
498
499 /*
500 * Detect the extended topology information if available. This
501 * will reinitialise the initial_apicid which will be used
502 * in init_intel_cacheinfo()
503 */
504 detect_extended_topology(c);
505
506 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
507 /*
508 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
509 * detection.
510 */
511 c->x86_max_cores = intel_num_cpu_cores(c);
512 #ifdef CONFIG_X86_32
513 detect_ht(c);
514 #endif
515 }
516
517 l2 = init_intel_cacheinfo(c);
518
519 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
520 if (l2 == 0) {
521 cpu_detect_cache_sizes(c);
522 l2 = c->x86_cache_size;
523 }
524
525 if (c->cpuid_level > 9) {
526 unsigned eax = cpuid_eax(10);
527 /* Check for version and the number of counters */
528 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
529 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
530 }
531
532 if (cpu_has(c, X86_FEATURE_XMM2))
533 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
534
535 if (boot_cpu_has(X86_FEATURE_DS)) {
536 unsigned int l1;
537 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
538 if (!(l1 & (1<<11)))
539 set_cpu_cap(c, X86_FEATURE_BTS);
540 if (!(l1 & (1<<12)))
541 set_cpu_cap(c, X86_FEATURE_PEBS);
542 }
543
544 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
545 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
546 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
547
548 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
549 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
550 set_cpu_bug(c, X86_BUG_MONITOR);
551
552 #ifdef CONFIG_X86_64
553 if (c->x86 == 15)
554 c->x86_cache_alignment = c->x86_clflush_size * 2;
555 if (c->x86 == 6)
556 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
557 #else
558 /*
559 * Names for the Pentium II/Celeron processors
560 * detectable only by also checking the cache size.
561 * Dixon is NOT a Celeron.
562 */
563 if (c->x86 == 6) {
564 char *p = NULL;
565
566 switch (c->x86_model) {
567 case 5:
568 if (l2 == 0)
569 p = "Celeron (Covington)";
570 else if (l2 == 256)
571 p = "Mobile Pentium II (Dixon)";
572 break;
573
574 case 6:
575 if (l2 == 128)
576 p = "Celeron (Mendocino)";
577 else if (c->x86_mask == 0 || c->x86_mask == 5)
578 p = "Celeron-A";
579 break;
580
581 case 8:
582 if (l2 == 128)
583 p = "Celeron (Coppermine)";
584 break;
585 }
586
587 if (p)
588 strcpy(c->x86_model_id, p);
589 }
590
591 if (c->x86 == 15)
592 set_cpu_cap(c, X86_FEATURE_P4);
593 if (c->x86 == 6)
594 set_cpu_cap(c, X86_FEATURE_P3);
595 #endif
596
597 /* Work around errata */
598 srat_detect_node(c);
599
600 if (cpu_has(c, X86_FEATURE_VMX))
601 detect_vmx_virtcap(c);
602
603 init_intel_energy_perf(c);
604
605 probe_xeon_phi_r3mwait(c);
606 }
607
608 #ifdef CONFIG_X86_32
609 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
610 {
611 /*
612 * Intel PIII Tualatin. This comes in two flavours.
613 * One has 256kb of cache, the other 512. We have no way
614 * to determine which, so we use a boottime override
615 * for the 512kb model, and assume 256 otherwise.
616 */
617 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
618 size = 256;
619
620 /*
621 * Intel Quark SoC X1000 contains a 4-way set associative
622 * 16K cache with a 16 byte cache line and 256 lines per tag
623 */
624 if ((c->x86 == 5) && (c->x86_model == 9))
625 size = 16;
626 return size;
627 }
628 #endif
629
630 #define TLB_INST_4K 0x01
631 #define TLB_INST_4M 0x02
632 #define TLB_INST_2M_4M 0x03
633
634 #define TLB_INST_ALL 0x05
635 #define TLB_INST_1G 0x06
636
637 #define TLB_DATA_4K 0x11
638 #define TLB_DATA_4M 0x12
639 #define TLB_DATA_2M_4M 0x13
640 #define TLB_DATA_4K_4M 0x14
641
642 #define TLB_DATA_1G 0x16
643
644 #define TLB_DATA0_4K 0x21
645 #define TLB_DATA0_4M 0x22
646 #define TLB_DATA0_2M_4M 0x23
647
648 #define STLB_4K 0x41
649 #define STLB_4K_2M 0x42
650
651 static const struct _tlb_table intel_tlb_table[] = {
652 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
653 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
654 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
655 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
656 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
657 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
658 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
659 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
660 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
661 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
662 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
663 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
664 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
665 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
666 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
667 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
668 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
669 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
670 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
671 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
672 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
673 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
674 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
675 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
676 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
677 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
678 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
679 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
680 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
681 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
682 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
683 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
684 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
685 { 0x00, 0, 0 }
686 };
687
688 static void intel_tlb_lookup(const unsigned char desc)
689 {
690 unsigned char k;
691 if (desc == 0)
692 return;
693
694 /* look up this descriptor in the table */
695 for (k = 0; intel_tlb_table[k].descriptor != desc && \
696 intel_tlb_table[k].descriptor != 0; k++)
697 ;
698
699 if (intel_tlb_table[k].tlb_type == 0)
700 return;
701
702 switch (intel_tlb_table[k].tlb_type) {
703 case STLB_4K:
704 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
705 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
706 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
707 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
708 break;
709 case STLB_4K_2M:
710 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
711 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
712 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
713 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
714 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
715 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
716 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
717 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
718 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
719 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
720 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
721 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
722 break;
723 case TLB_INST_ALL:
724 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
725 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
726 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
727 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
728 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
729 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
730 break;
731 case TLB_INST_4K:
732 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
733 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
734 break;
735 case TLB_INST_4M:
736 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
737 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
738 break;
739 case TLB_INST_2M_4M:
740 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
741 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
742 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
743 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
744 break;
745 case TLB_DATA_4K:
746 case TLB_DATA0_4K:
747 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
748 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
749 break;
750 case TLB_DATA_4M:
751 case TLB_DATA0_4M:
752 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
753 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
754 break;
755 case TLB_DATA_2M_4M:
756 case TLB_DATA0_2M_4M:
757 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
758 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
759 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
760 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
761 break;
762 case TLB_DATA_4K_4M:
763 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
764 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
765 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
766 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
767 break;
768 case TLB_DATA_1G:
769 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
770 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
771 break;
772 }
773 }
774
775 static void intel_detect_tlb(struct cpuinfo_x86 *c)
776 {
777 int i, j, n;
778 unsigned int regs[4];
779 unsigned char *desc = (unsigned char *)regs;
780
781 if (c->cpuid_level < 2)
782 return;
783
784 /* Number of times to iterate */
785 n = cpuid_eax(2) & 0xFF;
786
787 for (i = 0 ; i < n ; i++) {
788 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
789
790 /* If bit 31 is set, this is an unknown format */
791 for (j = 0 ; j < 3 ; j++)
792 if (regs[j] & (1 << 31))
793 regs[j] = 0;
794
795 /* Byte 0 is level count, not a descriptor */
796 for (j = 1 ; j < 16 ; j++)
797 intel_tlb_lookup(desc[j]);
798 }
799 }
800
801 static const struct cpu_dev intel_cpu_dev = {
802 .c_vendor = "Intel",
803 .c_ident = { "GenuineIntel" },
804 #ifdef CONFIG_X86_32
805 .legacy_models = {
806 { .family = 4, .model_names =
807 {
808 [0] = "486 DX-25/33",
809 [1] = "486 DX-50",
810 [2] = "486 SX",
811 [3] = "486 DX/2",
812 [4] = "486 SL",
813 [5] = "486 SX/2",
814 [7] = "486 DX/2-WB",
815 [8] = "486 DX/4",
816 [9] = "486 DX/4-WB"
817 }
818 },
819 { .family = 5, .model_names =
820 {
821 [0] = "Pentium 60/66 A-step",
822 [1] = "Pentium 60/66",
823 [2] = "Pentium 75 - 200",
824 [3] = "OverDrive PODP5V83",
825 [4] = "Pentium MMX",
826 [7] = "Mobile Pentium 75 - 200",
827 [8] = "Mobile Pentium MMX",
828 [9] = "Quark SoC X1000",
829 }
830 },
831 { .family = 6, .model_names =
832 {
833 [0] = "Pentium Pro A-step",
834 [1] = "Pentium Pro",
835 [3] = "Pentium II (Klamath)",
836 [4] = "Pentium II (Deschutes)",
837 [5] = "Pentium II (Deschutes)",
838 [6] = "Mobile Pentium II",
839 [7] = "Pentium III (Katmai)",
840 [8] = "Pentium III (Coppermine)",
841 [10] = "Pentium III (Cascades)",
842 [11] = "Pentium III (Tualatin)",
843 }
844 },
845 { .family = 15, .model_names =
846 {
847 [0] = "Pentium 4 (Unknown)",
848 [1] = "Pentium 4 (Willamette)",
849 [2] = "Pentium 4 (Northwood)",
850 [4] = "Pentium 4 (Foster)",
851 [5] = "Pentium 4 (Foster)",
852 }
853 },
854 },
855 .legacy_cache_size = intel_size_cache,
856 #endif
857 .c_detect_tlb = intel_detect_tlb,
858 .c_early_init = early_init_intel,
859 .c_init = init_intel,
860 .c_bsp_resume = intel_bsp_resume,
861 .c_x86_vendor = X86_VENDOR_INTEL,
862 };
863
864 cpu_dev_register(intel_cpu_dev);
865
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