arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/sched.h>
   8 #include <linux/thread_info.h>
   9 #include <linux/module.h>
  10 #include <linux/uaccess.h>
  11
  12 #include <asm/processor.h>
  13 #include <asm/pgtable.h>
  14 #include <asm/msr.h>
  15 #include <asm/ds.h>
  16 #include <asm/bugs.h>
  17 #include <asm/cpu.h>
  18
  19 #ifdef CONFIG_X86_64
  20 #include <linux/topology.h>
  21 #include <asm/numa_64.h>
  22 #endif
  23
  24 #include "cpu.h"
  25
  26 #ifdef CONFIG_X86_LOCAL_APIC
  27 #include <asm/mpspec.h>
  28 #include <asm/apic.h>
  29 #endif
  30
  31 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  32 {
  33         /* Unmask CPUID levels if masked: */
  34         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
  35                 u64 misc_enable;
  36
  37                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  38
  39                 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
  40                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
  41                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  42                         c->cpuid_level = cpuid_eax(0);
  43                 }
  44         }
  45
  46         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  47                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  48                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  49
  50 #ifdef CONFIG_X86_64
  51         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
  52 #else
  53         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  54         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  55                 c->x86_cache_alignment = 128;
  56 #endif
  57
  58         /* CPUID workaround for 0F33/0F34 CPU */
  59         if (c->x86 == 0xF && c->x86_model == 0x3
  60             && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
  61                 c->x86_phys_bits = 36;
  62
  63         /*
  64          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
  65          * with P/T states and does not stop in deep C-states.
  66          *
  67          * It is also reliable across cores and sockets. (but not across
  68          * cabinets - we turn it off in that case explicitly.)
  69          */
  70         if (c->x86_power & (1 << 8)) {
  71                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  72                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
  73                 set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
  74                 sched_clock_stable = 1;
  75         }
  76
  77         /*
  78          * There is a known erratum on Pentium III and Core Solo
  79          * and Core Duo CPUs.
  80          * " Page with PAT set to WC while associated MTRR is UC
  81          *   may consolidate to UC "
  82          * Because of this erratum, it is better to stick with
  83          * setting WC in MTRR rather than using PAT on these CPUs.
  84          *
  85          * Enable PAT WC only on P4, Core 2 or later CPUs.
  86          */
  87         if (c->x86 == 6 && c->x86_model < 15)
  88                 clear_cpu_cap(c, X86_FEATURE_PAT);
  89
  90 #ifdef CONFIG_KMEMCHECK
  91         /*
  92          * P4s have a "fast strings" feature which causes single-
  93          * stepping REP instructions to only generate a #DB on
  94          * cache-line boundaries.
  95          *
  96          * Ingo Molnar reported a Pentium D (model 6) and a Xeon
  97          * (model 2) with the same problem.
  98          */
  99         if (c->x86 == 15) {
 100                 u64 misc_enable;
 101
 102                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 103
 104                 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
 105                         printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
 106
 107                         misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
 108                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 109                 }
 110         }
 111 #endif
 112 }
 113
 114 #ifdef CONFIG_X86_32
 115 /*
 116  *      Early probe support logic for ppro memory erratum #50
 117  *
 118  *      This is called before we do cpu ident work
 119  */
 120
 121 int __cpuinit ppro_with_ram_bug(void)
 122 {
 123         /* Uses data from early_cpu_detect now */
 124         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 125             boot_cpu_data.x86 == 6 &&
 126             boot_cpu_data.x86_model == 1 &&
 127             boot_cpu_data.x86_mask < 8) {
 128                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
 129                 return 1;
 130         }
 131         return 0;
 132 }
 133
 134 #ifdef CONFIG_X86_F00F_BUG
 135 static void __cpuinit trap_init_f00f_bug(void)
 136 {
 137         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
 138
 139         /*
 140          * Update the IDT descriptor and reload the IDT so that
 141          * it uses the read-only mapped virtual address.
 142          */
 143         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
 144         load_idt(&idt_descr);
 145 }
 146 #endif
 147
 148 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
 149 {
 150 #ifdef CONFIG_SMP
 151         /* calling is from identify_secondary_cpu() ? */
 152         if (c->cpu_index == boot_cpu_id)
 153                 return;
 154
 155         /*
 156          * Mask B, Pentium, but not Pentium MMX
 157          */
 158         if (c->x86 == 5 &&
 159             c->x86_mask >= 1 && c->x86_mask <= 4 &&
 160             c->x86_model <= 3) {
 161                 /*
 162                  * Remember we have B step Pentia with bugs
 163                  */
 164                 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
 165                                     "with B stepping processors.\n");
 166         }
 167 #endif
 168 }
 169
 170 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 171 {
 172         unsigned long lo, hi;
 173
 174 #ifdef CONFIG_X86_F00F_BUG
 175         /*
 176          * All current models of Pentium and Pentium with MMX technology CPUs
 177          * have the F0 0F bug, which lets nonprivileged users lock up the
 178          * system.
 179          * Note that the workaround only should be initialized once...
 180          */
 181         c->f00f_bug = 0;
 182         if (!paravirt_enabled() && c->x86 == 5) {
 183                 static int f00f_workaround_enabled;
 184
 185                 c->f00f_bug = 1;
 186                 if (!f00f_workaround_enabled) {
 187                         trap_init_f00f_bug();
 188                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 189                         f00f_workaround_enabled = 1;
 190                 }
 191         }
 192 #endif
 193
 194         /*
 195          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
 196          * model 3 mask 3
 197          */
 198         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 199                 clear_cpu_cap(c, X86_FEATURE_SEP);
 200
 201         /*
 202          * P4 Xeon errata 037 workaround.
 203          * Hardware prefetcher may cause stale data to be loaded into the cache.
 204          */
 205         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 206                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 207                 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
 208                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 209                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
 210                         lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
 211                         wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 212                 }
 213         }
 214
 215         /*
 216          * See if we have a good local APIC by checking for buggy Pentia,
 217          * i.e. all B steppings and the C2 stepping of P54C when using their
 218          * integrated APIC (see 11AP erratum in "Pentium Processor
 219          * Specification Update").
 220          */
 221         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 222             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 223                 set_cpu_cap(c, X86_FEATURE_11AP);
 224
 225
 226 #ifdef CONFIG_X86_INTEL_USERCOPY
 227         /*
 228          * Set up the preferred alignment for movsl bulk memory moves
 229          */
 230         switch (c->x86) {
 231         case 4:         /* 486: untested */
 232                 break;
 233         case 5:         /* Old Pentia: untested */
 234                 break;
 235         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 236                 movsl_mask.mask = 7;
 237                 break;
 238         case 15:        /* P4 is OK down to 8-byte alignment */
 239                 movsl_mask.mask = 7;
 240                 break;
 241         }
 242 #endif
 243
 244 #ifdef CONFIG_X86_NUMAQ
 245         numaq_tsc_disable();
 246 #endif
 247
 248         intel_smp_check(c);
 249 }
 250 #else
 251 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 252 {
 253 }
 254 #endif
 255
 256 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 257 {
 258 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 259         unsigned node;
 260         int cpu = smp_processor_id();
 261         int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
 262
 263         /* Don't do the funky fallback heuristics the AMD version employs
 264            for now. */
 265         node = apicid_to_node[apicid];
 266         if (node == NUMA_NO_NODE)
 267                 node = first_node(node_online_map);
 268         else if (!node_online(node)) {
 269                 /* reuse the value from init_cpu_to_node() */
 270                 node = cpu_to_node(cpu);
 271         }
 272         numa_set_node(cpu, node);
 273 #endif
 274 }
 275
 276 /*
 277  * find out the number of processor cores on the die
 278  */
 279 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 280 {
 281         unsigned int eax, ebx, ecx, edx;
 282
 283         if (c->cpuid_level < 4)
 284                 return 1;
 285
 286         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
 287         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
 288         if (eax & 0x1f)
 289                 return (eax >> 26) + 1;
 290         else
 291                 return 1;
 292 }
 293
 294 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 295 {
 296         /* Intel VMX MSR indicated features */
 297 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
 298 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
 299 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
 300 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
 301 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
 302 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
 303
 304         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
 305
 306         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 307         clear_cpu_cap(c, X86_FEATURE_VNMI);
 308         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 309         clear_cpu_cap(c, X86_FEATURE_EPT);
 310         clear_cpu_cap(c, X86_FEATURE_VPID);
 311
 312         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
 313         msr_ctl = vmx_msr_high | vmx_msr_low;
 314         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
 315                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 316         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
 317                 set_cpu_cap(c, X86_FEATURE_VNMI);
 318         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
 319                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
 320                       vmx_msr_low, vmx_msr_high);
 321                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
 322                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
 323                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
 324                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 325                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
 326                         set_cpu_cap(c, X86_FEATURE_EPT);
 327                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
 328                         set_cpu_cap(c, X86_FEATURE_VPID);
 329         }
 330 }
 331
 332 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 333 {
 334         unsigned int l2 = 0;
 335
 336         early_init_intel(c);
 337
 338         intel_workarounds(c);
 339
 340         /*
 341          * Detect the extended topology information if available. This
 342          * will reinitialise the initial_apicid which will be used
 343          * in init_intel_cacheinfo()
 344          */
 345         detect_extended_topology(c);
 346
 347         l2 = init_intel_cacheinfo(c);
 348         if (c->cpuid_level > 9) {
 349                 unsigned eax = cpuid_eax(10);
 350                 /* Check for version and the number of counters */
 351                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 352                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 353         }
 354
 355         if (c->cpuid_level > 6) {
 356                 unsigned ecx = cpuid_ecx(6);
 357                 if (ecx & 0x01)
 358                         set_cpu_cap(c, X86_FEATURE_APERFMPERF);
 359         }
 360
 361         if (cpu_has_xmm2)
 362                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 363         if (cpu_has_ds) {
 364                 unsigned int l1;
 365                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 366                 if (!(l1 & (1<<11)))
 367                         set_cpu_cap(c, X86_FEATURE_BTS);
 368                 if (!(l1 & (1<<12)))
 369                         set_cpu_cap(c, X86_FEATURE_PEBS);
 370                 ds_init_intel(c);
 371         }
 372
 373         if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
 374                 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
 375
 376 #ifdef CONFIG_X86_64
 377         if (c->x86 == 15)
 378                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 379         if (c->x86 == 6)
 380                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 381 #else
 382         /*
 383          * Names for the Pentium II/Celeron processors
 384          * detectable only by also checking the cache size.
 385          * Dixon is NOT a Celeron.
 386          */
 387         if (c->x86 == 6) {
 388                 char *p = NULL;
 389
 390                 switch (c->x86_model) {
 391                 case 5:
 392                         if (c->x86_mask == 0) {
 393                                 if (l2 == 0)
 394                                         p = "Celeron (Covington)";
 395                                 else if (l2 == 256)
 396                                         p = "Mobile Pentium II (Dixon)";
 397                         }
 398                         break;
 399
 400                 case 6:
 401                         if (l2 == 128)
 402                                 p = "Celeron (Mendocino)";
 403                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 404                                 p = "Celeron-A";
 405                         break;
 406
 407                 case 8:
 408                         if (l2 == 128)
 409                                 p = "Celeron (Coppermine)";
 410                         break;
 411                 }
 412
 413                 if (p)
 414                         strcpy(c->x86_model_id, p);
 415         }
 416
 417         if (c->x86 == 15)
 418                 set_cpu_cap(c, X86_FEATURE_P4);
 419         if (c->x86 == 6)
 420                 set_cpu_cap(c, X86_FEATURE_P3);
 421 #endif
 422
 423         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
 424                 /*
 425                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 426                  * detection.
 427                  */
 428                 c->x86_max_cores = intel_num_cpu_cores(c);
 429 #ifdef CONFIG_X86_32
 430                 detect_ht(c);
 431 #endif
 432         }
 433
 434         /* Work around errata */
 435         srat_detect_node(c);
 436
 437         if (cpu_has(c, X86_FEATURE_VMX))
 438                 detect_vmx_virtcap(c);
 439 }
 440
 441 #ifdef CONFIG_X86_32
 442 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 443 {
 444         /*
 445          * Intel PIII Tualatin. This comes in two flavours.
 446          * One has 256kb of cache, the other 512. We have no way
 447          * to determine which, so we use a boottime override
 448          * for the 512kb model, and assume 256 otherwise.
 449          */
 450         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 451                 size = 256;
 452         return size;
 453 }
 454 #endif
 455
 456 static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
 457         .c_vendor       = "Intel",
 458         .c_ident        = { "GenuineIntel" },
 459 #ifdef CONFIG_X86_32
 460         .c_models = {
 461                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 462                   {
 463                           [0] = "486 DX-25/33",
 464                           [1] = "486 DX-50",
 465                           [2] = "486 SX",
 466                           [3] = "486 DX/2",
 467                           [4] = "486 SL",
 468                           [5] = "486 SX/2",
 469                           [7] = "486 DX/2-WB",
 470                           [8] = "486 DX/4",
 471                           [9] = "486 DX/4-WB"
 472                   }
 473                 },
 474                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 475                   {
 476                           [0] = "Pentium 60/66 A-step",
 477                           [1] = "Pentium 60/66",
 478                           [2] = "Pentium 75 - 200",
 479                           [3] = "OverDrive PODP5V83",
 480                           [4] = "Pentium MMX",
 481                           [7] = "Mobile Pentium 75 - 200",
 482                           [8] = "Mobile Pentium MMX"
 483                   }
 484                 },
 485                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 486                   {
 487                           [0] = "Pentium Pro A-step",
 488                           [1] = "Pentium Pro",
 489                           [3] = "Pentium II (Klamath)",
 490                           [4] = "Pentium II (Deschutes)",
 491                           [5] = "Pentium II (Deschutes)",
 492                           [6] = "Mobile Pentium II",
 493                           [7] = "Pentium III (Katmai)",
 494                           [8] = "Pentium III (Coppermine)",
 495                           [10] = "Pentium III (Cascades)",
 496                           [11] = "Pentium III (Tualatin)",
 497                   }
 498                 },
 499                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 500                   {
 501                           [0] = "Pentium 4 (Unknown)",
 502                           [1] = "Pentium 4 (Willamette)",
 503                           [2] = "Pentium 4 (Northwood)",
 504                           [4] = "Pentium 4 (Foster)",
 505                           [5] = "Pentium 4 (Foster)",
 506                   }
 507                 },
 508         },
 509         .c_size_cache   = intel_size_cache,
 510 #endif
 511         .c_early_init   = early_init_intel,
 512         .c_init         = init_intel,
 513         .c_x86_vendor   = X86_VENDOR_INTEL,
 514 };
 515
 516 cpu_dev_register(intel_cpu_dev);
 517