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1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3
4 #include <linux/string.h>
5 #include <linux/bitops.h>
6 #include <linux/smp.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/thread_info.h>
10 #include <linux/init.h>
11 #include <linux/uaccess.h>
12
13 #include <asm/cpufeature.h>
14 #include <asm/pgtable.h>
15 #include <asm/msr.h>
16 #include <asm/bugs.h>
17 #include <asm/cpu.h>
18 #include <asm/intel-family.h>
19 #include <asm/microcode_intel.h>
20 #include <asm/hwcap2.h>
21 #include <asm/elf.h>
22
23 #ifdef CONFIG_X86_64
24 #include <linux/topology.h>
25 #endif
26
27 #include "cpu.h"
28
29 #ifdef CONFIG_X86_LOCAL_APIC
30 #include <asm/mpspec.h>
31 #include <asm/apic.h>
32 #endif
33
34 /*
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
37 */
38 static int forcempx;
39
40 static int __init forcempx_setup(char *__unused)
41 {
42 forcempx = 1;
43
44 return 1;
45 }
46 __setup("intel-skd-046-workaround=disable", forcempx_setup);
47
48 void check_mpx_erratum(struct cpuinfo_x86 *c)
49 {
50 if (forcempx)
51 return;
52 /*
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
55 *
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
58 *
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
62 */
63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
66 }
67 }
68
69 static bool ring3mwait_disabled __read_mostly;
70
71 static int __init ring3mwait_disable(char *__unused)
72 {
73 ring3mwait_disabled = true;
74 return 0;
75 }
76 __setup("ring3mwait=disable", ring3mwait_disable);
77
78 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
79 {
80 /*
81 * Ring 3 MONITOR/MWAIT feature cannot be detected without
82 * cpu model and family comparison.
83 */
84 if (c->x86 != 6)
85 return;
86 switch (c->x86_model) {
87 case INTEL_FAM6_XEON_PHI_KNL:
88 case INTEL_FAM6_XEON_PHI_KNM:
89 break;
90 default:
91 return;
92 }
93
94 if (ring3mwait_disabled)
95 return;
96
97 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
98 this_cpu_or(msr_misc_features_shadow,
99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
100
101 if (c == &boot_cpu_data)
102 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
103 }
104
105 static void early_init_intel(struct cpuinfo_x86 *c)
106 {
107 u64 misc_enable;
108
109 /* Unmask CPUID levels if masked: */
110 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
111 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
112 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
113 c->cpuid_level = cpuid_eax(0);
114 get_cpu_cap(c);
115 }
116 }
117
118 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
119 (c->x86 == 0x6 && c->x86_model >= 0x0e))
120 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
121
122 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
123 c->microcode = intel_get_microcode_revision();
124
125 /*
126 * Atom erratum AAE44/AAF40/AAG38/AAH41:
127 *
128 * A race condition between speculative fetches and invalidating
129 * a large page. This is worked around in microcode, but we
130 * need the microcode to have already been loaded... so if it is
131 * not, recommend a BIOS update and disable large pages.
132 */
133 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
134 c->microcode < 0x20e) {
135 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
136 clear_cpu_cap(c, X86_FEATURE_PSE);
137 }
138
139 #ifdef CONFIG_X86_64
140 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
141 #else
142 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
143 if (c->x86 == 15 && c->x86_cache_alignment == 64)
144 c->x86_cache_alignment = 128;
145 #endif
146
147 /* CPUID workaround for 0F33/0F34 CPU */
148 if (c->x86 == 0xF && c->x86_model == 0x3
149 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
150 c->x86_phys_bits = 36;
151
152 /*
153 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
154 * with P/T states and does not stop in deep C-states.
155 *
156 * It is also reliable across cores and sockets. (but not across
157 * cabinets - we turn it off in that case explicitly.)
158 */
159 if (c->x86_power & (1 << 8)) {
160 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
161 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
162 }
163
164 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
165 if (c->x86 == 6) {
166 switch (c->x86_model) {
167 case 0x27: /* Penwell */
168 case 0x35: /* Cloverview */
169 case 0x4a: /* Merrifield */
170 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
171 break;
172 default:
173 break;
174 }
175 }
176
177 /*
178 * There is a known erratum on Pentium III and Core Solo
179 * and Core Duo CPUs.
180 * " Page with PAT set to WC while associated MTRR is UC
181 * may consolidate to UC "
182 * Because of this erratum, it is better to stick with
183 * setting WC in MTRR rather than using PAT on these CPUs.
184 *
185 * Enable PAT WC only on P4, Core 2 or later CPUs.
186 */
187 if (c->x86 == 6 && c->x86_model < 15)
188 clear_cpu_cap(c, X86_FEATURE_PAT);
189
190 /*
191 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
192 * clear the fast string and enhanced fast string CPU capabilities.
193 */
194 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
195 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
196 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
197 pr_info("Disabled fast string operations\n");
198 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
199 setup_clear_cpu_cap(X86_FEATURE_ERMS);
200 }
201 }
202
203 /*
204 * Intel Quark Core DevMan_001.pdf section 6.4.11
205 * "The operating system also is required to invalidate (i.e., flush)
206 * the TLB when any changes are made to any of the page table entries.
207 * The operating system must reload CR3 to cause the TLB to be flushed"
208 *
209 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
210 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
211 * to be modified.
212 */
213 if (c->x86 == 5 && c->x86_model == 9) {
214 pr_info("Disabling PGE capability bit\n");
215 setup_clear_cpu_cap(X86_FEATURE_PGE);
216 }
217
218 if (c->cpuid_level >= 0x00000001) {
219 u32 eax, ebx, ecx, edx;
220
221 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
222 /*
223 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
224 * apicids which are reserved per package. Store the resulting
225 * shift value for the package management code.
226 */
227 if (edx & (1U << 28))
228 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
229 }
230
231 check_mpx_erratum(c);
232 }
233
234 #ifdef CONFIG_X86_32
235 /*
236 * Early probe support logic for ppro memory erratum #50
237 *
238 * This is called before we do cpu ident work
239 */
240
241 int ppro_with_ram_bug(void)
242 {
243 /* Uses data from early_cpu_detect now */
244 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
245 boot_cpu_data.x86 == 6 &&
246 boot_cpu_data.x86_model == 1 &&
247 boot_cpu_data.x86_mask < 8) {
248 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
249 return 1;
250 }
251 return 0;
252 }
253
254 static void intel_smp_check(struct cpuinfo_x86 *c)
255 {
256 /* calling is from identify_secondary_cpu() ? */
257 if (!c->cpu_index)
258 return;
259
260 /*
261 * Mask B, Pentium, but not Pentium MMX
262 */
263 if (c->x86 == 5 &&
264 c->x86_mask >= 1 && c->x86_mask <= 4 &&
265 c->x86_model <= 3) {
266 /*
267 * Remember we have B step Pentia with bugs
268 */
269 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
270 "with B stepping processors.\n");
271 }
272 }
273
274 static int forcepae;
275 static int __init forcepae_setup(char *__unused)
276 {
277 forcepae = 1;
278 return 1;
279 }
280 __setup("forcepae", forcepae_setup);
281
282 static void intel_workarounds(struct cpuinfo_x86 *c)
283 {
284 #ifdef CONFIG_X86_F00F_BUG
285 /*
286 * All models of Pentium and Pentium with MMX technology CPUs
287 * have the F0 0F bug, which lets nonprivileged users lock up the
288 * system. Announce that the fault handler will be checking for it.
289 * The Quark is also family 5, but does not have the same bug.
290 */
291 clear_cpu_bug(c, X86_BUG_F00F);
292 if (c->x86 == 5 && c->x86_model < 9) {
293 static int f00f_workaround_enabled;
294
295 set_cpu_bug(c, X86_BUG_F00F);
296 if (!f00f_workaround_enabled) {
297 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
298 f00f_workaround_enabled = 1;
299 }
300 }
301 #endif
302
303 /*
304 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
305 * model 3 mask 3
306 */
307 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
308 clear_cpu_cap(c, X86_FEATURE_SEP);
309
310 /*
311 * PAE CPUID issue: many Pentium M report no PAE but may have a
312 * functionally usable PAE implementation.
313 * Forcefully enable PAE if kernel parameter "forcepae" is present.
314 */
315 if (forcepae) {
316 pr_warn("PAE forced!\n");
317 set_cpu_cap(c, X86_FEATURE_PAE);
318 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
319 }
320
321 /*
322 * P4 Xeon erratum 037 workaround.
323 * Hardware prefetcher may cause stale data to be loaded into the cache.
324 */
325 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
326 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
327 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
328 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
329 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
330 }
331 }
332
333 /*
334 * See if we have a good local APIC by checking for buggy Pentia,
335 * i.e. all B steppings and the C2 stepping of P54C when using their
336 * integrated APIC (see 11AP erratum in "Pentium Processor
337 * Specification Update").
338 */
339 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
340 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
341 set_cpu_bug(c, X86_BUG_11AP);
342
343
344 #ifdef CONFIG_X86_INTEL_USERCOPY
345 /*
346 * Set up the preferred alignment for movsl bulk memory moves
347 */
348 switch (c->x86) {
349 case 4: /* 486: untested */
350 break;
351 case 5: /* Old Pentia: untested */
352 break;
353 case 6: /* PII/PIII only like movsl with 8-byte alignment */
354 movsl_mask.mask = 7;
355 break;
356 case 15: /* P4 is OK down to 8-byte alignment */
357 movsl_mask.mask = 7;
358 break;
359 }
360 #endif
361
362 intel_smp_check(c);
363 }
364 #else
365 static void intel_workarounds(struct cpuinfo_x86 *c)
366 {
367 }
368 #endif
369
370 static void srat_detect_node(struct cpuinfo_x86 *c)
371 {
372 #ifdef CONFIG_NUMA
373 unsigned node;
374 int cpu = smp_processor_id();
375
376 /* Don't do the funky fallback heuristics the AMD version employs
377 for now. */
378 node = numa_cpu_node(cpu);
379 if (node == NUMA_NO_NODE || !node_online(node)) {
380 /* reuse the value from init_cpu_to_node() */
381 node = cpu_to_node(cpu);
382 }
383 numa_set_node(cpu, node);
384 #endif
385 }
386
387 /*
388 * find out the number of processor cores on the die
389 */
390 static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
391 {
392 unsigned int eax, ebx, ecx, edx;
393
394 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
395 return 1;
396
397 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
398 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
399 if (eax & 0x1f)
400 return (eax >> 26) + 1;
401 else
402 return 1;
403 }
404
405 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
406 {
407 /* Intel VMX MSR indicated features */
408 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
409 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
410 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
411 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
412 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
413 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
414
415 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
416
417 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
418 clear_cpu_cap(c, X86_FEATURE_VNMI);
419 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
420 clear_cpu_cap(c, X86_FEATURE_EPT);
421 clear_cpu_cap(c, X86_FEATURE_VPID);
422
423 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
424 msr_ctl = vmx_msr_high | vmx_msr_low;
425 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
426 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
427 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
428 set_cpu_cap(c, X86_FEATURE_VNMI);
429 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
430 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
431 vmx_msr_low, vmx_msr_high);
432 msr_ctl2 = vmx_msr_high | vmx_msr_low;
433 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
434 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
435 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
436 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
437 set_cpu_cap(c, X86_FEATURE_EPT);
438 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
439 set_cpu_cap(c, X86_FEATURE_VPID);
440 }
441 }
442
443 static void init_intel_energy_perf(struct cpuinfo_x86 *c)
444 {
445 u64 epb;
446
447 /*
448 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
449 * (x86_energy_perf_policy(8) is available to change it at run-time.)
450 */
451 if (!cpu_has(c, X86_FEATURE_EPB))
452 return;
453
454 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
455 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
456 return;
457
458 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
459 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
460 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
461 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
462 }
463
464 static void intel_bsp_resume(struct cpuinfo_x86 *c)
465 {
466 /*
467 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
468 * so reinitialize it properly like during bootup:
469 */
470 init_intel_energy_perf(c);
471 }
472
473 static void init_cpuid_fault(struct cpuinfo_x86 *c)
474 {
475 u64 msr;
476
477 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
478 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
479 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
480 }
481 }
482
483 static void init_intel_misc_features(struct cpuinfo_x86 *c)
484 {
485 u64 msr;
486
487 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
488 return;
489
490 /* Clear all MISC features */
491 this_cpu_write(msr_misc_features_shadow, 0);
492
493 /* Check features and update capabilities and shadow control bits */
494 init_cpuid_fault(c);
495 probe_xeon_phi_r3mwait(c);
496
497 msr = this_cpu_read(msr_misc_features_shadow);
498 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
499 }
500
501 static void init_intel(struct cpuinfo_x86 *c)
502 {
503 unsigned int l2 = 0;
504
505 early_init_intel(c);
506
507 intel_workarounds(c);
508
509 /*
510 * Detect the extended topology information if available. This
511 * will reinitialise the initial_apicid which will be used
512 * in init_intel_cacheinfo()
513 */
514 detect_extended_topology(c);
515
516 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
517 /*
518 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
519 * detection.
520 */
521 c->x86_max_cores = intel_num_cpu_cores(c);
522 #ifdef CONFIG_X86_32
523 detect_ht(c);
524 #endif
525 }
526
527 l2 = init_intel_cacheinfo(c);
528
529 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
530 if (l2 == 0) {
531 cpu_detect_cache_sizes(c);
532 l2 = c->x86_cache_size;
533 }
534
535 if (c->cpuid_level > 9) {
536 unsigned eax = cpuid_eax(10);
537 /* Check for version and the number of counters */
538 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
539 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
540 }
541
542 if (cpu_has(c, X86_FEATURE_XMM2))
543 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
544
545 if (boot_cpu_has(X86_FEATURE_DS)) {
546 unsigned int l1;
547 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
548 if (!(l1 & (1<<11)))
549 set_cpu_cap(c, X86_FEATURE_BTS);
550 if (!(l1 & (1<<12)))
551 set_cpu_cap(c, X86_FEATURE_PEBS);
552 }
553
554 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
555 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
556 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
557
558 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
559 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
560 set_cpu_bug(c, X86_BUG_MONITOR);
561
562 #ifdef CONFIG_X86_64
563 if (c->x86 == 15)
564 c->x86_cache_alignment = c->x86_clflush_size * 2;
565 if (c->x86 == 6)
566 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
567 #else
568 /*
569 * Names for the Pentium II/Celeron processors
570 * detectable only by also checking the cache size.
571 * Dixon is NOT a Celeron.
572 */
573 if (c->x86 == 6) {
574 char *p = NULL;
575
576 switch (c->x86_model) {
577 case 5:
578 if (l2 == 0)
579 p = "Celeron (Covington)";
580 else if (l2 == 256)
581 p = "Mobile Pentium II (Dixon)";
582 break;
583
584 case 6:
585 if (l2 == 128)
586 p = "Celeron (Mendocino)";
587 else if (c->x86_mask == 0 || c->x86_mask == 5)
588 p = "Celeron-A";
589 break;
590
591 case 8:
592 if (l2 == 128)
593 p = "Celeron (Coppermine)";
594 break;
595 }
596
597 if (p)
598 strcpy(c->x86_model_id, p);
599 }
600
601 if (c->x86 == 15)
602 set_cpu_cap(c, X86_FEATURE_P4);
603 if (c->x86 == 6)
604 set_cpu_cap(c, X86_FEATURE_P3);
605 #endif
606
607 /* Work around errata */
608 srat_detect_node(c);
609
610 if (cpu_has(c, X86_FEATURE_VMX))
611 detect_vmx_virtcap(c);
612
613 init_intel_energy_perf(c);
614
615 init_intel_misc_features(c);
616 }
617
618 #ifdef CONFIG_X86_32
619 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
620 {
621 /*
622 * Intel PIII Tualatin. This comes in two flavours.
623 * One has 256kb of cache, the other 512. We have no way
624 * to determine which, so we use a boottime override
625 * for the 512kb model, and assume 256 otherwise.
626 */
627 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
628 size = 256;
629
630 /*
631 * Intel Quark SoC X1000 contains a 4-way set associative
632 * 16K cache with a 16 byte cache line and 256 lines per tag
633 */
634 if ((c->x86 == 5) && (c->x86_model == 9))
635 size = 16;
636 return size;
637 }
638 #endif
639
640 #define TLB_INST_4K 0x01
641 #define TLB_INST_4M 0x02
642 #define TLB_INST_2M_4M 0x03
643
644 #define TLB_INST_ALL 0x05
645 #define TLB_INST_1G 0x06
646
647 #define TLB_DATA_4K 0x11
648 #define TLB_DATA_4M 0x12
649 #define TLB_DATA_2M_4M 0x13
650 #define TLB_DATA_4K_4M 0x14
651
652 #define TLB_DATA_1G 0x16
653
654 #define TLB_DATA0_4K 0x21
655 #define TLB_DATA0_4M 0x22
656 #define TLB_DATA0_2M_4M 0x23
657
658 #define STLB_4K 0x41
659 #define STLB_4K_2M 0x42
660
661 static const struct _tlb_table intel_tlb_table[] = {
662 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
663 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
664 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
665 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
666 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
667 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
668 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
669 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
670 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
671 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
672 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
673 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
674 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
675 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
676 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
677 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
678 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
679 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
680 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
681 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
682 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
683 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
684 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
685 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
686 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
687 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
688 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
689 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
690 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
691 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
692 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
693 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
694 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
695 { 0x00, 0, 0 }
696 };
697
698 static void intel_tlb_lookup(const unsigned char desc)
699 {
700 unsigned char k;
701 if (desc == 0)
702 return;
703
704 /* look up this descriptor in the table */
705 for (k = 0; intel_tlb_table[k].descriptor != desc && \
706 intel_tlb_table[k].descriptor != 0; k++)
707 ;
708
709 if (intel_tlb_table[k].tlb_type == 0)
710 return;
711
712 switch (intel_tlb_table[k].tlb_type) {
713 case STLB_4K:
714 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
715 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
716 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
717 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
718 break;
719 case STLB_4K_2M:
720 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
721 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
722 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
723 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
724 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
725 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
726 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
727 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
728 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
729 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
730 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
731 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
732 break;
733 case TLB_INST_ALL:
734 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
735 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
736 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
737 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
738 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
739 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
740 break;
741 case TLB_INST_4K:
742 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
743 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
744 break;
745 case TLB_INST_4M:
746 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
747 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
748 break;
749 case TLB_INST_2M_4M:
750 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
751 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
752 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
753 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
754 break;
755 case TLB_DATA_4K:
756 case TLB_DATA0_4K:
757 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
758 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
759 break;
760 case TLB_DATA_4M:
761 case TLB_DATA0_4M:
762 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
763 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
764 break;
765 case TLB_DATA_2M_4M:
766 case TLB_DATA0_2M_4M:
767 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
768 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
769 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
770 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
771 break;
772 case TLB_DATA_4K_4M:
773 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
774 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
775 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
776 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
777 break;
778 case TLB_DATA_1G:
779 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
780 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
781 break;
782 }
783 }
784
785 static void intel_detect_tlb(struct cpuinfo_x86 *c)
786 {
787 int i, j, n;
788 unsigned int regs[4];
789 unsigned char *desc = (unsigned char *)regs;
790
791 if (c->cpuid_level < 2)
792 return;
793
794 /* Number of times to iterate */
795 n = cpuid_eax(2) & 0xFF;
796
797 for (i = 0 ; i < n ; i++) {
798 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
799
800 /* If bit 31 is set, this is an unknown format */
801 for (j = 0 ; j < 3 ; j++)
802 if (regs[j] & (1 << 31))
803 regs[j] = 0;
804
805 /* Byte 0 is level count, not a descriptor */
806 for (j = 1 ; j < 16 ; j++)
807 intel_tlb_lookup(desc[j]);
808 }
809 }
810
811 static const struct cpu_dev intel_cpu_dev = {
812 .c_vendor = "Intel",
813 .c_ident = { "GenuineIntel" },
814 #ifdef CONFIG_X86_32
815 .legacy_models = {
816 { .family = 4, .model_names =
817 {
818 [0] = "486 DX-25/33",
819 [1] = "486 DX-50",
820 [2] = "486 SX",
821 [3] = "486 DX/2",
822 [4] = "486 SL",
823 [5] = "486 SX/2",
824 [7] = "486 DX/2-WB",
825 [8] = "486 DX/4",
826 [9] = "486 DX/4-WB"
827 }
828 },
829 { .family = 5, .model_names =
830 {
831 [0] = "Pentium 60/66 A-step",
832 [1] = "Pentium 60/66",
833 [2] = "Pentium 75 - 200",
834 [3] = "OverDrive PODP5V83",
835 [4] = "Pentium MMX",
836 [7] = "Mobile Pentium 75 - 200",
837 [8] = "Mobile Pentium MMX",
838 [9] = "Quark SoC X1000",
839 }
840 },
841 { .family = 6, .model_names =
842 {
843 [0] = "Pentium Pro A-step",
844 [1] = "Pentium Pro",
845 [3] = "Pentium II (Klamath)",
846 [4] = "Pentium II (Deschutes)",
847 [5] = "Pentium II (Deschutes)",
848 [6] = "Mobile Pentium II",
849 [7] = "Pentium III (Katmai)",
850 [8] = "Pentium III (Coppermine)",
851 [10] = "Pentium III (Cascades)",
852 [11] = "Pentium III (Tualatin)",
853 }
854 },
855 { .family = 15, .model_names =
856 {
857 [0] = "Pentium 4 (Unknown)",
858 [1] = "Pentium 4 (Willamette)",
859 [2] = "Pentium 4 (Northwood)",
860 [4] = "Pentium 4 (Foster)",
861 [5] = "Pentium 4 (Foster)",
862 }
863 },
864 },
865 .legacy_cache_size = intel_size_cache,
866 #endif
867 .c_detect_tlb = intel_detect_tlb,
868 .c_early_init = early_init_intel,
869 .c_init = init_intel,
870 .c_bsp_resume = intel_bsp_resume,
871 .c_x86_vendor = X86_VENDOR_INTEL,
872 };
873
874 cpu_dev_register(intel_cpu_dev);
875
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