1 #include <linux/kernel.h>
3 #include <linux/string.h>
4 #include <linux/bitops.h>
6 #include <linux/sched.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
9 #include <linux/uaccess.h>
11 #include <asm/processor.h>
12 #include <asm/pgtable.h>
18 #include <linux/topology.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
28 static void early_init_intel(struct cpuinfo_x86
*c
)
32 /* Unmask CPUID levels if masked: */
33 if (c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xd)) {
34 if (msr_clear_bit(MSR_IA32_MISC_ENABLE
,
35 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT
) > 0) {
36 c
->cpuid_level
= cpuid_eax(0);
41 if ((c
->x86
== 0xf && c
->x86_model
>= 0x03) ||
42 (c
->x86
== 0x6 && c
->x86_model
>= 0x0e))
43 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
45 if (c
->x86
>= 6 && !cpu_has(c
, X86_FEATURE_IA64
)) {
48 wrmsr(MSR_IA32_UCODE_REV
, 0, 0);
49 /* Required by the SDM */
51 rdmsr(MSR_IA32_UCODE_REV
, lower_word
, c
->microcode
);
55 * Atom erratum AAE44/AAF40/AAG38/AAH41:
57 * A race condition between speculative fetches and invalidating
58 * a large page. This is worked around in microcode, but we
59 * need the microcode to have already been loaded... so if it is
60 * not, recommend a BIOS update and disable large pages.
62 if (c
->x86
== 6 && c
->x86_model
== 0x1c && c
->x86_mask
<= 2 &&
63 c
->microcode
< 0x20e) {
64 printk(KERN_WARNING
"Atom PSE erratum detected, BIOS microcode update recommended\n");
65 clear_cpu_cap(c
, X86_FEATURE_PSE
);
69 set_cpu_cap(c
, X86_FEATURE_SYSENTER32
);
71 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
72 if (c
->x86
== 15 && c
->x86_cache_alignment
== 64)
73 c
->x86_cache_alignment
= 128;
76 /* CPUID workaround for 0F33/0F34 CPU */
77 if (c
->x86
== 0xF && c
->x86_model
== 0x3
78 && (c
->x86_mask
== 0x3 || c
->x86_mask
== 0x4))
79 c
->x86_phys_bits
= 36;
82 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83 * with P/T states and does not stop in deep C-states.
85 * It is also reliable across cores and sockets. (but not across
86 * cabinets - we turn it off in that case explicitly.)
88 if (c
->x86_power
& (1 << 8)) {
89 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
90 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC
);
91 if (!check_tsc_unstable())
92 set_sched_clock_stable();
95 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
97 switch (c
->x86_model
) {
98 case 0x27: /* Penwell */
99 case 0x35: /* Cloverview */
100 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC_S3
);
108 * There is a known erratum on Pentium III and Core Solo
110 * " Page with PAT set to WC while associated MTRR is UC
111 * may consolidate to UC "
112 * Because of this erratum, it is better to stick with
113 * setting WC in MTRR rather than using PAT on these CPUs.
115 * Enable PAT WC only on P4, Core 2 or later CPUs.
117 if (c
->x86
== 6 && c
->x86_model
< 15)
118 clear_cpu_cap(c
, X86_FEATURE_PAT
);
120 #ifdef CONFIG_KMEMCHECK
122 * P4s have a "fast strings" feature which causes single-
123 * stepping REP instructions to only generate a #DB on
124 * cache-line boundaries.
126 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
127 * (model 2) with the same problem.
130 if (msr_clear_bit(MSR_IA32_MISC_ENABLE
,
131 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT
) > 0)
132 pr_info("kmemcheck: Disabling fast string operations\n");
136 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
137 * clear the fast string and enhanced fast string CPU capabilities.
139 if (c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xd)) {
140 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_enable
);
141 if (!(misc_enable
& MSR_IA32_MISC_ENABLE_FAST_STRING
)) {
142 printk(KERN_INFO
"Disabled fast string operations\n");
143 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD
);
144 setup_clear_cpu_cap(X86_FEATURE_ERMS
);
151 * Early probe support logic for ppro memory erratum #50
153 * This is called before we do cpu ident work
156 int ppro_with_ram_bug(void)
158 /* Uses data from early_cpu_detect now */
159 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&&
160 boot_cpu_data
.x86
== 6 &&
161 boot_cpu_data
.x86_model
== 1 &&
162 boot_cpu_data
.x86_mask
< 8) {
163 printk(KERN_INFO
"Pentium Pro with Errata#50 detected. Taking evasive action.\n");
169 static void intel_smp_check(struct cpuinfo_x86
*c
)
171 /* calling is from identify_secondary_cpu() ? */
176 * Mask B, Pentium, but not Pentium MMX
179 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
182 * Remember we have B step Pentia with bugs
184 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
185 "with B stepping processors.\n");
190 static int __init
forcepae_setup(char *__unused
)
195 __setup("forcepae", forcepae_setup
);
197 static void intel_workarounds(struct cpuinfo_x86
*c
)
199 #ifdef CONFIG_X86_F00F_BUG
201 * All current models of Pentium and Pentium with MMX technology CPUs
202 * have the F0 0F bug, which lets nonprivileged users lock up the
203 * system. Announce that the fault handler will be checking for it.
205 clear_cpu_bug(c
, X86_BUG_F00F
);
206 if (!paravirt_enabled() && c
->x86
== 5) {
207 static int f00f_workaround_enabled
;
209 set_cpu_bug(c
, X86_BUG_F00F
);
210 if (!f00f_workaround_enabled
) {
211 printk(KERN_NOTICE
"Intel Pentium with F0 0F bug - workaround enabled.\n");
212 f00f_workaround_enabled
= 1;
218 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
221 if ((c
->x86
<<8 | c
->x86_model
<<4 | c
->x86_mask
) < 0x633)
222 clear_cpu_cap(c
, X86_FEATURE_SEP
);
225 * PAE CPUID issue: many Pentium M report no PAE but may have a
226 * functionally usable PAE implementation.
227 * Forcefully enable PAE if kernel parameter "forcepae" is present.
230 printk(KERN_WARNING
"PAE forced!\n");
231 set_cpu_cap(c
, X86_FEATURE_PAE
);
232 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_NOW_UNRELIABLE
);
236 * P4 Xeon errata 037 workaround.
237 * Hardware prefetcher may cause stale data to be loaded into the cache.
239 if ((c
->x86
== 15) && (c
->x86_model
== 1) && (c
->x86_mask
== 1)) {
240 if (msr_set_bit(MSR_IA32_MISC_ENABLE
,
241 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT
)
243 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
244 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
249 * See if we have a good local APIC by checking for buggy Pentia,
250 * i.e. all B steppings and the C2 stepping of P54C when using their
251 * integrated APIC (see 11AP erratum in "Pentium Processor
252 * Specification Update").
254 if (cpu_has_apic
&& (c
->x86
<<8 | c
->x86_model
<<4) == 0x520 &&
255 (c
->x86_mask
< 0x6 || c
->x86_mask
== 0xb))
256 set_cpu_cap(c
, X86_FEATURE_11AP
);
259 #ifdef CONFIG_X86_INTEL_USERCOPY
261 * Set up the preferred alignment for movsl bulk memory moves
264 case 4: /* 486: untested */
266 case 5: /* Old Pentia: untested */
268 case 6: /* PII/PIII only like movsl with 8-byte alignment */
271 case 15: /* P4 is OK down to 8-byte alignment */
280 static void intel_workarounds(struct cpuinfo_x86
*c
)
285 static void srat_detect_node(struct cpuinfo_x86
*c
)
289 int cpu
= smp_processor_id();
291 /* Don't do the funky fallback heuristics the AMD version employs
293 node
= numa_cpu_node(cpu
);
294 if (node
== NUMA_NO_NODE
|| !node_online(node
)) {
295 /* reuse the value from init_cpu_to_node() */
296 node
= cpu_to_node(cpu
);
298 numa_set_node(cpu
, node
);
303 * find out the number of processor cores on the die
305 static int intel_num_cpu_cores(struct cpuinfo_x86
*c
)
307 unsigned int eax
, ebx
, ecx
, edx
;
309 if (c
->cpuid_level
< 4)
312 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
313 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
315 return (eax
>> 26) + 1;
320 static void detect_vmx_virtcap(struct cpuinfo_x86
*c
)
322 /* Intel VMX MSR indicated features */
323 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
324 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
325 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
326 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
327 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
328 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
330 u32 vmx_msr_low
, vmx_msr_high
, msr_ctl
, msr_ctl2
;
332 clear_cpu_cap(c
, X86_FEATURE_TPR_SHADOW
);
333 clear_cpu_cap(c
, X86_FEATURE_VNMI
);
334 clear_cpu_cap(c
, X86_FEATURE_FLEXPRIORITY
);
335 clear_cpu_cap(c
, X86_FEATURE_EPT
);
336 clear_cpu_cap(c
, X86_FEATURE_VPID
);
338 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
, vmx_msr_low
, vmx_msr_high
);
339 msr_ctl
= vmx_msr_high
| vmx_msr_low
;
340 if (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW
)
341 set_cpu_cap(c
, X86_FEATURE_TPR_SHADOW
);
342 if (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_VNMI
)
343 set_cpu_cap(c
, X86_FEATURE_VNMI
);
344 if (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS
) {
345 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
346 vmx_msr_low
, vmx_msr_high
);
347 msr_ctl2
= vmx_msr_high
| vmx_msr_low
;
348 if ((msr_ctl2
& X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC
) &&
349 (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW
))
350 set_cpu_cap(c
, X86_FEATURE_FLEXPRIORITY
);
351 if (msr_ctl2
& X86_VMX_FEATURE_PROC_CTLS2_EPT
)
352 set_cpu_cap(c
, X86_FEATURE_EPT
);
353 if (msr_ctl2
& X86_VMX_FEATURE_PROC_CTLS2_VPID
)
354 set_cpu_cap(c
, X86_FEATURE_VPID
);
358 static void init_intel(struct cpuinfo_x86
*c
)
364 intel_workarounds(c
);
367 * Detect the extended topology information if available. This
368 * will reinitialise the initial_apicid which will be used
369 * in init_intel_cacheinfo()
371 detect_extended_topology(c
);
373 if (!cpu_has(c
, X86_FEATURE_XTOPOLOGY
)) {
375 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
378 c
->x86_max_cores
= intel_num_cpu_cores(c
);
384 l2
= init_intel_cacheinfo(c
);
385 if (c
->cpuid_level
> 9) {
386 unsigned eax
= cpuid_eax(10);
387 /* Check for version and the number of counters */
388 if ((eax
& 0xff) && (((eax
>>8) & 0xff) > 1))
389 set_cpu_cap(c
, X86_FEATURE_ARCH_PERFMON
);
393 set_cpu_cap(c
, X86_FEATURE_LFENCE_RDTSC
);
396 rdmsr(MSR_IA32_MISC_ENABLE
, l1
, l2
);
398 set_cpu_cap(c
, X86_FEATURE_BTS
);
400 set_cpu_cap(c
, X86_FEATURE_PEBS
);
403 if (c
->x86
== 6 && cpu_has_clflush
&&
404 (c
->x86_model
== 29 || c
->x86_model
== 46 || c
->x86_model
== 47))
405 set_cpu_cap(c
, X86_FEATURE_CLFLUSH_MONITOR
);
409 c
->x86_cache_alignment
= c
->x86_clflush_size
* 2;
411 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
414 * Names for the Pentium II/Celeron processors
415 * detectable only by also checking the cache size.
416 * Dixon is NOT a Celeron.
421 switch (c
->x86_model
) {
424 p
= "Celeron (Covington)";
426 p
= "Mobile Pentium II (Dixon)";
431 p
= "Celeron (Mendocino)";
432 else if (c
->x86_mask
== 0 || c
->x86_mask
== 5)
438 p
= "Celeron (Coppermine)";
443 strcpy(c
->x86_model_id
, p
);
447 set_cpu_cap(c
, X86_FEATURE_P4
);
449 set_cpu_cap(c
, X86_FEATURE_P3
);
452 /* Work around errata */
455 if (cpu_has(c
, X86_FEATURE_VMX
))
456 detect_vmx_virtcap(c
);
459 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
460 * x86_energy_perf_policy(8) is available to change it at run-time
462 if (cpu_has(c
, X86_FEATURE_EPB
)) {
465 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS
, epb
);
466 if ((epb
& 0xF) == ENERGY_PERF_BIAS_PERFORMANCE
) {
467 printk_once(KERN_WARNING
"ENERGY_PERF_BIAS:"
468 " Set to 'normal', was 'performance'\n"
469 "ENERGY_PERF_BIAS: View and update with"
470 " x86_energy_perf_policy(8)\n");
471 epb
= (epb
& ~0xF) | ENERGY_PERF_BIAS_NORMAL
;
472 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS
, epb
);
478 static unsigned int intel_size_cache(struct cpuinfo_x86
*c
, unsigned int size
)
481 * Intel PIII Tualatin. This comes in two flavours.
482 * One has 256kb of cache, the other 512. We have no way
483 * to determine which, so we use a boottime override
484 * for the 512kb model, and assume 256 otherwise.
486 if ((c
->x86
== 6) && (c
->x86_model
== 11) && (size
== 0))
492 #define TLB_INST_4K 0x01
493 #define TLB_INST_4M 0x02
494 #define TLB_INST_2M_4M 0x03
496 #define TLB_INST_ALL 0x05
497 #define TLB_INST_1G 0x06
499 #define TLB_DATA_4K 0x11
500 #define TLB_DATA_4M 0x12
501 #define TLB_DATA_2M_4M 0x13
502 #define TLB_DATA_4K_4M 0x14
504 #define TLB_DATA_1G 0x16
506 #define TLB_DATA0_4K 0x21
507 #define TLB_DATA0_4M 0x22
508 #define TLB_DATA0_2M_4M 0x23
511 #define STLB_4K_2M 0x42
513 static const struct _tlb_table intel_tlb_table
[] = {
514 { 0x01, TLB_INST_4K
, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
515 { 0x02, TLB_INST_4M
, 2, " TLB_INST 4 MByte pages, full associative" },
516 { 0x03, TLB_DATA_4K
, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
517 { 0x04, TLB_DATA_4M
, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
518 { 0x05, TLB_DATA_4M
, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
519 { 0x0b, TLB_INST_4M
, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
520 { 0x4f, TLB_INST_4K
, 32, " TLB_INST 4 KByte pages */" },
521 { 0x50, TLB_INST_ALL
, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
522 { 0x51, TLB_INST_ALL
, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
523 { 0x52, TLB_INST_ALL
, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
524 { 0x55, TLB_INST_2M_4M
, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
525 { 0x56, TLB_DATA0_4M
, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
526 { 0x57, TLB_DATA0_4K
, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
527 { 0x59, TLB_DATA0_4K
, 16, " TLB_DATA0 4 KByte pages, fully associative" },
528 { 0x5a, TLB_DATA0_2M_4M
, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
529 { 0x5b, TLB_DATA_4K_4M
, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
530 { 0x5c, TLB_DATA_4K_4M
, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
531 { 0x5d, TLB_DATA_4K_4M
, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
532 { 0x61, TLB_INST_4K
, 48, " TLB_INST 4 KByte pages, full associative" },
533 { 0x63, TLB_DATA_1G
, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
534 { 0x76, TLB_INST_2M_4M
, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
535 { 0xb0, TLB_INST_4K
, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
536 { 0xb1, TLB_INST_2M_4M
, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
537 { 0xb2, TLB_INST_4K
, 64, " TLB_INST 4KByte pages, 4-way set associative" },
538 { 0xb3, TLB_DATA_4K
, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
539 { 0xb4, TLB_DATA_4K
, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
540 { 0xb5, TLB_INST_4K
, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" },
541 { 0xb6, TLB_INST_4K
, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" },
542 { 0xba, TLB_DATA_4K
, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
543 { 0xc0, TLB_DATA_4K_4M
, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
544 { 0xc1, STLB_4K_2M
, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
545 { 0xc2, TLB_DATA_2M_4M
, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
546 { 0xca, STLB_4K
, 512, " STLB 4 KByte pages, 4-way associative" },
550 static void intel_tlb_lookup(const unsigned char desc
)
556 /* look up this descriptor in the table */
557 for (k
= 0; intel_tlb_table
[k
].descriptor
!= desc
&& \
558 intel_tlb_table
[k
].descriptor
!= 0; k
++)
561 if (intel_tlb_table
[k
].tlb_type
== 0)
564 switch (intel_tlb_table
[k
].tlb_type
) {
566 if (tlb_lli_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
567 tlb_lli_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
568 if (tlb_lld_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
569 tlb_lld_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
572 if (tlb_lli_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
573 tlb_lli_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
574 if (tlb_lld_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
575 tlb_lld_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
576 if (tlb_lli_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
577 tlb_lli_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
578 if (tlb_lld_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
579 tlb_lld_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
580 if (tlb_lli_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
581 tlb_lli_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
582 if (tlb_lld_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
583 tlb_lld_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
586 if (tlb_lli_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
587 tlb_lli_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
588 if (tlb_lli_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
589 tlb_lli_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
590 if (tlb_lli_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
591 tlb_lli_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
594 if (tlb_lli_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
595 tlb_lli_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
598 if (tlb_lli_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
599 tlb_lli_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
602 if (tlb_lli_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
603 tlb_lli_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
604 if (tlb_lli_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
605 tlb_lli_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
609 if (tlb_lld_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
610 tlb_lld_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
614 if (tlb_lld_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
615 tlb_lld_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
618 case TLB_DATA0_2M_4M
:
619 if (tlb_lld_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
620 tlb_lld_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
621 if (tlb_lld_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
622 tlb_lld_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
625 if (tlb_lld_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
626 tlb_lld_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
627 if (tlb_lld_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
628 tlb_lld_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
631 if (tlb_lld_1g
[ENTRIES
] < intel_tlb_table
[k
].entries
)
632 tlb_lld_1g
[ENTRIES
] = intel_tlb_table
[k
].entries
;
637 static void intel_tlb_flushall_shift_set(struct cpuinfo_x86
*c
)
639 switch ((c
->x86
<< 8) + c
->x86_model
) {
640 case 0x60f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
641 case 0x616: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
642 case 0x617: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
643 case 0x61d: /* six-core 45 nm xeon "Dunnington" */
644 tlb_flushall_shift
= -1;
646 case 0x63a: /* Ivybridge */
647 tlb_flushall_shift
= 2;
649 case 0x61a: /* 45 nm nehalem, "Bloomfield" */
650 case 0x61e: /* 45 nm nehalem, "Lynnfield" */
651 case 0x625: /* 32 nm nehalem, "Clarkdale" */
652 case 0x62c: /* 32 nm nehalem, "Gulftown" */
653 case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
654 case 0x62f: /* 32 nm Xeon E7 */
655 case 0x62a: /* SandyBridge */
656 case 0x62d: /* SandyBridge, "Romely-EP" */
658 tlb_flushall_shift
= 6;
662 static void intel_detect_tlb(struct cpuinfo_x86
*c
)
665 unsigned int regs
[4];
666 unsigned char *desc
= (unsigned char *)regs
;
668 if (c
->cpuid_level
< 2)
671 /* Number of times to iterate */
672 n
= cpuid_eax(2) & 0xFF;
674 for (i
= 0 ; i
< n
; i
++) {
675 cpuid(2, ®s
[0], ®s
[1], ®s
[2], ®s
[3]);
677 /* If bit 31 is set, this is an unknown format */
678 for (j
= 0 ; j
< 3 ; j
++)
679 if (regs
[j
] & (1 << 31))
682 /* Byte 0 is level count, not a descriptor */
683 for (j
= 1 ; j
< 16 ; j
++)
684 intel_tlb_lookup(desc
[j
]);
686 intel_tlb_flushall_shift_set(c
);
689 static const struct cpu_dev intel_cpu_dev
= {
691 .c_ident
= { "GenuineIntel" },
694 { .family
= 4, .model_names
=
696 [0] = "486 DX-25/33",
707 { .family
= 5, .model_names
=
709 [0] = "Pentium 60/66 A-step",
710 [1] = "Pentium 60/66",
711 [2] = "Pentium 75 - 200",
712 [3] = "OverDrive PODP5V83",
714 [7] = "Mobile Pentium 75 - 200",
715 [8] = "Mobile Pentium MMX"
718 { .family
= 6, .model_names
=
720 [0] = "Pentium Pro A-step",
722 [3] = "Pentium II (Klamath)",
723 [4] = "Pentium II (Deschutes)",
724 [5] = "Pentium II (Deschutes)",
725 [6] = "Mobile Pentium II",
726 [7] = "Pentium III (Katmai)",
727 [8] = "Pentium III (Coppermine)",
728 [10] = "Pentium III (Cascades)",
729 [11] = "Pentium III (Tualatin)",
732 { .family
= 15, .model_names
=
734 [0] = "Pentium 4 (Unknown)",
735 [1] = "Pentium 4 (Willamette)",
736 [2] = "Pentium 4 (Northwood)",
737 [4] = "Pentium 4 (Foster)",
738 [5] = "Pentium 4 (Foster)",
742 .legacy_cache_size
= intel_size_cache
,
744 .c_detect_tlb
= intel_detect_tlb
,
745 .c_early_init
= early_init_intel
,
746 .c_init
= init_intel
,
747 .c_x86_vendor
= X86_VENDOR_INTEL
,
750 cpu_dev_register(intel_cpu_dev
);