1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/thread_info.h>
10 #include <linux/init.h>
11 #include <linux/uaccess.h>
13 #include <asm/cpufeature.h>
14 #include <asm/pgtable.h>
18 #include <asm/intel-family.h>
19 #include <asm/microcode_intel.h>
20 #include <asm/hwcap2.h>
24 #include <linux/topology.h>
29 #ifdef CONFIG_X86_LOCAL_APIC
30 #include <asm/mpspec.h>
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
40 static int __init
forcempx_setup(char *__unused
)
46 __setup("intel-skd-046-workaround=disable", forcempx_setup
);
48 void check_mpx_erratum(struct cpuinfo_x86
*c
)
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
63 if (cpu_has(c
, X86_FEATURE_MPX
) && !cpu_has(c
, X86_FEATURE_SMEP
)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX
);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
69 static bool ring3mwait_disabled __read_mostly
;
71 static int __init
ring3mwait_disable(char *__unused
)
73 ring3mwait_disabled
= true;
76 __setup("ring3mwait=disable", ring3mwait_disable
);
78 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86
*c
)
81 * Ring 3 MONITOR/MWAIT feature cannot be detected without
82 * cpu model and family comparison.
86 switch (c
->x86_model
) {
87 case INTEL_FAM6_XEON_PHI_KNL
:
88 case INTEL_FAM6_XEON_PHI_KNM
:
94 if (ring3mwait_disabled
)
97 set_cpu_cap(c
, X86_FEATURE_RING3MWAIT
);
98 this_cpu_or(msr_misc_features_shadow
,
99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT
);
101 if (c
== &boot_cpu_data
)
102 ELF_HWCAP2
|= HWCAP2_RING3MWAIT
;
105 static void early_init_intel(struct cpuinfo_x86
*c
)
109 /* Unmask CPUID levels if masked: */
110 if (c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xd)) {
111 if (msr_clear_bit(MSR_IA32_MISC_ENABLE
,
112 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT
) > 0) {
113 c
->cpuid_level
= cpuid_eax(0);
118 if ((c
->x86
== 0xf && c
->x86_model
>= 0x03) ||
119 (c
->x86
== 0x6 && c
->x86_model
>= 0x0e))
120 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
122 if (c
->x86
>= 6 && !cpu_has(c
, X86_FEATURE_IA64
))
123 c
->microcode
= intel_get_microcode_revision();
126 * Atom erratum AAE44/AAF40/AAG38/AAH41:
128 * A race condition between speculative fetches and invalidating
129 * a large page. This is worked around in microcode, but we
130 * need the microcode to have already been loaded... so if it is
131 * not, recommend a BIOS update and disable large pages.
133 if (c
->x86
== 6 && c
->x86_model
== 0x1c && c
->x86_mask
<= 2 &&
134 c
->microcode
< 0x20e) {
135 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
136 clear_cpu_cap(c
, X86_FEATURE_PSE
);
140 set_cpu_cap(c
, X86_FEATURE_SYSENTER32
);
142 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
143 if (c
->x86
== 15 && c
->x86_cache_alignment
== 64)
144 c
->x86_cache_alignment
= 128;
147 /* CPUID workaround for 0F33/0F34 CPU */
148 if (c
->x86
== 0xF && c
->x86_model
== 0x3
149 && (c
->x86_mask
== 0x3 || c
->x86_mask
== 0x4))
150 c
->x86_phys_bits
= 36;
153 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
154 * with P/T states and does not stop in deep C-states.
156 * It is also reliable across cores and sockets. (but not across
157 * cabinets - we turn it off in that case explicitly.)
159 if (c
->x86_power
& (1 << 8)) {
160 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
161 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC
);
164 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
166 switch (c
->x86_model
) {
167 case 0x27: /* Penwell */
168 case 0x35: /* Cloverview */
169 case 0x4a: /* Merrifield */
170 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC_S3
);
178 * There is a known erratum on Pentium III and Core Solo
180 * " Page with PAT set to WC while associated MTRR is UC
181 * may consolidate to UC "
182 * Because of this erratum, it is better to stick with
183 * setting WC in MTRR rather than using PAT on these CPUs.
185 * Enable PAT WC only on P4, Core 2 or later CPUs.
187 if (c
->x86
== 6 && c
->x86_model
< 15)
188 clear_cpu_cap(c
, X86_FEATURE_PAT
);
190 #ifdef CONFIG_KMEMCHECK
192 * P4s have a "fast strings" feature which causes single-
193 * stepping REP instructions to only generate a #DB on
194 * cache-line boundaries.
196 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
197 * (model 2) with the same problem.
200 if (msr_clear_bit(MSR_IA32_MISC_ENABLE
,
201 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT
) > 0)
202 pr_info("kmemcheck: Disabling fast string operations\n");
206 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
207 * clear the fast string and enhanced fast string CPU capabilities.
209 if (c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xd)) {
210 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_enable
);
211 if (!(misc_enable
& MSR_IA32_MISC_ENABLE_FAST_STRING
)) {
212 pr_info("Disabled fast string operations\n");
213 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD
);
214 setup_clear_cpu_cap(X86_FEATURE_ERMS
);
219 * Intel Quark Core DevMan_001.pdf section 6.4.11
220 * "The operating system also is required to invalidate (i.e., flush)
221 * the TLB when any changes are made to any of the page table entries.
222 * The operating system must reload CR3 to cause the TLB to be flushed"
224 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
225 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
228 if (c
->x86
== 5 && c
->x86_model
== 9) {
229 pr_info("Disabling PGE capability bit\n");
230 setup_clear_cpu_cap(X86_FEATURE_PGE
);
233 if (c
->cpuid_level
>= 0x00000001) {
234 u32 eax
, ebx
, ecx
, edx
;
236 cpuid(0x00000001, &eax
, &ebx
, &ecx
, &edx
);
238 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
239 * apicids which are reserved per package. Store the resulting
240 * shift value for the package management code.
242 if (edx
& (1U << 28))
243 c
->x86_coreid_bits
= get_count_order((ebx
>> 16) & 0xff);
246 check_mpx_erratum(c
);
251 * Early probe support logic for ppro memory erratum #50
253 * This is called before we do cpu ident work
256 int ppro_with_ram_bug(void)
258 /* Uses data from early_cpu_detect now */
259 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&&
260 boot_cpu_data
.x86
== 6 &&
261 boot_cpu_data
.x86_model
== 1 &&
262 boot_cpu_data
.x86_mask
< 8) {
263 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
269 static void intel_smp_check(struct cpuinfo_x86
*c
)
271 /* calling is from identify_secondary_cpu() ? */
276 * Mask B, Pentium, but not Pentium MMX
279 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
282 * Remember we have B step Pentia with bugs
284 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
285 "with B stepping processors.\n");
290 static int __init
forcepae_setup(char *__unused
)
295 __setup("forcepae", forcepae_setup
);
297 static void intel_workarounds(struct cpuinfo_x86
*c
)
299 #ifdef CONFIG_X86_F00F_BUG
301 * All models of Pentium and Pentium with MMX technology CPUs
302 * have the F0 0F bug, which lets nonprivileged users lock up the
303 * system. Announce that the fault handler will be checking for it.
304 * The Quark is also family 5, but does not have the same bug.
306 clear_cpu_bug(c
, X86_BUG_F00F
);
307 if (c
->x86
== 5 && c
->x86_model
< 9) {
308 static int f00f_workaround_enabled
;
310 set_cpu_bug(c
, X86_BUG_F00F
);
311 if (!f00f_workaround_enabled
) {
312 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
313 f00f_workaround_enabled
= 1;
319 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
322 if ((c
->x86
<<8 | c
->x86_model
<<4 | c
->x86_mask
) < 0x633)
323 clear_cpu_cap(c
, X86_FEATURE_SEP
);
326 * PAE CPUID issue: many Pentium M report no PAE but may have a
327 * functionally usable PAE implementation.
328 * Forcefully enable PAE if kernel parameter "forcepae" is present.
331 pr_warn("PAE forced!\n");
332 set_cpu_cap(c
, X86_FEATURE_PAE
);
333 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_NOW_UNRELIABLE
);
337 * P4 Xeon erratum 037 workaround.
338 * Hardware prefetcher may cause stale data to be loaded into the cache.
340 if ((c
->x86
== 15) && (c
->x86_model
== 1) && (c
->x86_mask
== 1)) {
341 if (msr_set_bit(MSR_IA32_MISC_ENABLE
,
342 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT
) > 0) {
343 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
344 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
349 * See if we have a good local APIC by checking for buggy Pentia,
350 * i.e. all B steppings and the C2 stepping of P54C when using their
351 * integrated APIC (see 11AP erratum in "Pentium Processor
352 * Specification Update").
354 if (boot_cpu_has(X86_FEATURE_APIC
) && (c
->x86
<<8 | c
->x86_model
<<4) == 0x520 &&
355 (c
->x86_mask
< 0x6 || c
->x86_mask
== 0xb))
356 set_cpu_bug(c
, X86_BUG_11AP
);
359 #ifdef CONFIG_X86_INTEL_USERCOPY
361 * Set up the preferred alignment for movsl bulk memory moves
364 case 4: /* 486: untested */
366 case 5: /* Old Pentia: untested */
368 case 6: /* PII/PIII only like movsl with 8-byte alignment */
371 case 15: /* P4 is OK down to 8-byte alignment */
380 static void intel_workarounds(struct cpuinfo_x86
*c
)
385 static void srat_detect_node(struct cpuinfo_x86
*c
)
389 int cpu
= smp_processor_id();
391 /* Don't do the funky fallback heuristics the AMD version employs
393 node
= numa_cpu_node(cpu
);
394 if (node
== NUMA_NO_NODE
|| !node_online(node
)) {
395 /* reuse the value from init_cpu_to_node() */
396 node
= cpu_to_node(cpu
);
398 numa_set_node(cpu
, node
);
403 * find out the number of processor cores on the die
405 static int intel_num_cpu_cores(struct cpuinfo_x86
*c
)
407 unsigned int eax
, ebx
, ecx
, edx
;
409 if (!IS_ENABLED(CONFIG_SMP
) || c
->cpuid_level
< 4)
412 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
413 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
415 return (eax
>> 26) + 1;
420 static void detect_vmx_virtcap(struct cpuinfo_x86
*c
)
422 /* Intel VMX MSR indicated features */
423 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
424 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
425 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
426 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
427 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
428 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
430 u32 vmx_msr_low
, vmx_msr_high
, msr_ctl
, msr_ctl2
;
432 clear_cpu_cap(c
, X86_FEATURE_TPR_SHADOW
);
433 clear_cpu_cap(c
, X86_FEATURE_VNMI
);
434 clear_cpu_cap(c
, X86_FEATURE_FLEXPRIORITY
);
435 clear_cpu_cap(c
, X86_FEATURE_EPT
);
436 clear_cpu_cap(c
, X86_FEATURE_VPID
);
438 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
, vmx_msr_low
, vmx_msr_high
);
439 msr_ctl
= vmx_msr_high
| vmx_msr_low
;
440 if (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW
)
441 set_cpu_cap(c
, X86_FEATURE_TPR_SHADOW
);
442 if (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_VNMI
)
443 set_cpu_cap(c
, X86_FEATURE_VNMI
);
444 if (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS
) {
445 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
446 vmx_msr_low
, vmx_msr_high
);
447 msr_ctl2
= vmx_msr_high
| vmx_msr_low
;
448 if ((msr_ctl2
& X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC
) &&
449 (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW
))
450 set_cpu_cap(c
, X86_FEATURE_FLEXPRIORITY
);
451 if (msr_ctl2
& X86_VMX_FEATURE_PROC_CTLS2_EPT
)
452 set_cpu_cap(c
, X86_FEATURE_EPT
);
453 if (msr_ctl2
& X86_VMX_FEATURE_PROC_CTLS2_VPID
)
454 set_cpu_cap(c
, X86_FEATURE_VPID
);
458 static void init_intel_energy_perf(struct cpuinfo_x86
*c
)
463 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
464 * (x86_energy_perf_policy(8) is available to change it at run-time.)
466 if (!cpu_has(c
, X86_FEATURE_EPB
))
469 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS
, epb
);
470 if ((epb
& 0xF) != ENERGY_PERF_BIAS_PERFORMANCE
)
473 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
474 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
475 epb
= (epb
& ~0xF) | ENERGY_PERF_BIAS_NORMAL
;
476 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS
, epb
);
479 static void intel_bsp_resume(struct cpuinfo_x86
*c
)
482 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
483 * so reinitialize it properly like during bootup:
485 init_intel_energy_perf(c
);
488 static void init_cpuid_fault(struct cpuinfo_x86
*c
)
492 if (!rdmsrl_safe(MSR_PLATFORM_INFO
, &msr
)) {
493 if (msr
& MSR_PLATFORM_INFO_CPUID_FAULT
)
494 set_cpu_cap(c
, X86_FEATURE_CPUID_FAULT
);
498 static void init_intel_misc_features(struct cpuinfo_x86
*c
)
502 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES
, &msr
))
505 /* Clear all MISC features */
506 this_cpu_write(msr_misc_features_shadow
, 0);
508 /* Check features and update capabilities and shadow control bits */
510 probe_xeon_phi_r3mwait(c
);
512 msr
= this_cpu_read(msr_misc_features_shadow
);
513 wrmsrl(MSR_MISC_FEATURES_ENABLES
, msr
);
516 static void init_intel(struct cpuinfo_x86
*c
)
522 intel_workarounds(c
);
525 * Detect the extended topology information if available. This
526 * will reinitialise the initial_apicid which will be used
527 * in init_intel_cacheinfo()
529 detect_extended_topology(c
);
531 if (!cpu_has(c
, X86_FEATURE_XTOPOLOGY
)) {
533 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
536 c
->x86_max_cores
= intel_num_cpu_cores(c
);
542 l2
= init_intel_cacheinfo(c
);
544 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
546 cpu_detect_cache_sizes(c
);
547 l2
= c
->x86_cache_size
;
550 if (c
->cpuid_level
> 9) {
551 unsigned eax
= cpuid_eax(10);
552 /* Check for version and the number of counters */
553 if ((eax
& 0xff) && (((eax
>>8) & 0xff) > 1))
554 set_cpu_cap(c
, X86_FEATURE_ARCH_PERFMON
);
557 if (cpu_has(c
, X86_FEATURE_XMM2
))
558 set_cpu_cap(c
, X86_FEATURE_LFENCE_RDTSC
);
560 if (boot_cpu_has(X86_FEATURE_DS
)) {
562 rdmsr(MSR_IA32_MISC_ENABLE
, l1
, l2
);
564 set_cpu_cap(c
, X86_FEATURE_BTS
);
566 set_cpu_cap(c
, X86_FEATURE_PEBS
);
569 if (c
->x86
== 6 && boot_cpu_has(X86_FEATURE_CLFLUSH
) &&
570 (c
->x86_model
== 29 || c
->x86_model
== 46 || c
->x86_model
== 47))
571 set_cpu_bug(c
, X86_BUG_CLFLUSH_MONITOR
);
573 if (c
->x86
== 6 && boot_cpu_has(X86_FEATURE_MWAIT
) &&
574 ((c
->x86_model
== INTEL_FAM6_ATOM_GOLDMONT
)))
575 set_cpu_bug(c
, X86_BUG_MONITOR
);
579 c
->x86_cache_alignment
= c
->x86_clflush_size
* 2;
581 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
584 * Names for the Pentium II/Celeron processors
585 * detectable only by also checking the cache size.
586 * Dixon is NOT a Celeron.
591 switch (c
->x86_model
) {
594 p
= "Celeron (Covington)";
596 p
= "Mobile Pentium II (Dixon)";
601 p
= "Celeron (Mendocino)";
602 else if (c
->x86_mask
== 0 || c
->x86_mask
== 5)
608 p
= "Celeron (Coppermine)";
613 strcpy(c
->x86_model_id
, p
);
617 set_cpu_cap(c
, X86_FEATURE_P4
);
619 set_cpu_cap(c
, X86_FEATURE_P3
);
622 /* Work around errata */
625 if (cpu_has(c
, X86_FEATURE_VMX
))
626 detect_vmx_virtcap(c
);
628 init_intel_energy_perf(c
);
630 init_intel_misc_features(c
);
634 static unsigned int intel_size_cache(struct cpuinfo_x86
*c
, unsigned int size
)
637 * Intel PIII Tualatin. This comes in two flavours.
638 * One has 256kb of cache, the other 512. We have no way
639 * to determine which, so we use a boottime override
640 * for the 512kb model, and assume 256 otherwise.
642 if ((c
->x86
== 6) && (c
->x86_model
== 11) && (size
== 0))
646 * Intel Quark SoC X1000 contains a 4-way set associative
647 * 16K cache with a 16 byte cache line and 256 lines per tag
649 if ((c
->x86
== 5) && (c
->x86_model
== 9))
655 #define TLB_INST_4K 0x01
656 #define TLB_INST_4M 0x02
657 #define TLB_INST_2M_4M 0x03
659 #define TLB_INST_ALL 0x05
660 #define TLB_INST_1G 0x06
662 #define TLB_DATA_4K 0x11
663 #define TLB_DATA_4M 0x12
664 #define TLB_DATA_2M_4M 0x13
665 #define TLB_DATA_4K_4M 0x14
667 #define TLB_DATA_1G 0x16
669 #define TLB_DATA0_4K 0x21
670 #define TLB_DATA0_4M 0x22
671 #define TLB_DATA0_2M_4M 0x23
674 #define STLB_4K_2M 0x42
676 static const struct _tlb_table intel_tlb_table
[] = {
677 { 0x01, TLB_INST_4K
, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
678 { 0x02, TLB_INST_4M
, 2, " TLB_INST 4 MByte pages, full associative" },
679 { 0x03, TLB_DATA_4K
, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
680 { 0x04, TLB_DATA_4M
, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
681 { 0x05, TLB_DATA_4M
, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
682 { 0x0b, TLB_INST_4M
, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
683 { 0x4f, TLB_INST_4K
, 32, " TLB_INST 4 KByte pages */" },
684 { 0x50, TLB_INST_ALL
, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
685 { 0x51, TLB_INST_ALL
, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
686 { 0x52, TLB_INST_ALL
, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
687 { 0x55, TLB_INST_2M_4M
, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
688 { 0x56, TLB_DATA0_4M
, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
689 { 0x57, TLB_DATA0_4K
, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
690 { 0x59, TLB_DATA0_4K
, 16, " TLB_DATA0 4 KByte pages, fully associative" },
691 { 0x5a, TLB_DATA0_2M_4M
, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
692 { 0x5b, TLB_DATA_4K_4M
, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
693 { 0x5c, TLB_DATA_4K_4M
, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
694 { 0x5d, TLB_DATA_4K_4M
, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
695 { 0x61, TLB_INST_4K
, 48, " TLB_INST 4 KByte pages, full associative" },
696 { 0x63, TLB_DATA_1G
, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
697 { 0x76, TLB_INST_2M_4M
, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
698 { 0xb0, TLB_INST_4K
, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
699 { 0xb1, TLB_INST_2M_4M
, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
700 { 0xb2, TLB_INST_4K
, 64, " TLB_INST 4KByte pages, 4-way set associative" },
701 { 0xb3, TLB_DATA_4K
, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
702 { 0xb4, TLB_DATA_4K
, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
703 { 0xb5, TLB_INST_4K
, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
704 { 0xb6, TLB_INST_4K
, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
705 { 0xba, TLB_DATA_4K
, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
706 { 0xc0, TLB_DATA_4K_4M
, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
707 { 0xc1, STLB_4K_2M
, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
708 { 0xc2, TLB_DATA_2M_4M
, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
709 { 0xca, STLB_4K
, 512, " STLB 4 KByte pages, 4-way associative" },
713 static void intel_tlb_lookup(const unsigned char desc
)
719 /* look up this descriptor in the table */
720 for (k
= 0; intel_tlb_table
[k
].descriptor
!= desc
&& \
721 intel_tlb_table
[k
].descriptor
!= 0; k
++)
724 if (intel_tlb_table
[k
].tlb_type
== 0)
727 switch (intel_tlb_table
[k
].tlb_type
) {
729 if (tlb_lli_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
730 tlb_lli_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
731 if (tlb_lld_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
732 tlb_lld_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
735 if (tlb_lli_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
736 tlb_lli_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
737 if (tlb_lld_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
738 tlb_lld_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
739 if (tlb_lli_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
740 tlb_lli_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
741 if (tlb_lld_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
742 tlb_lld_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
743 if (tlb_lli_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
744 tlb_lli_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
745 if (tlb_lld_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
746 tlb_lld_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
749 if (tlb_lli_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
750 tlb_lli_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
751 if (tlb_lli_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
752 tlb_lli_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
753 if (tlb_lli_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
754 tlb_lli_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
757 if (tlb_lli_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
758 tlb_lli_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
761 if (tlb_lli_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
762 tlb_lli_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
765 if (tlb_lli_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
766 tlb_lli_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
767 if (tlb_lli_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
768 tlb_lli_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
772 if (tlb_lld_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
773 tlb_lld_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
777 if (tlb_lld_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
778 tlb_lld_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
781 case TLB_DATA0_2M_4M
:
782 if (tlb_lld_2m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
783 tlb_lld_2m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
784 if (tlb_lld_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
785 tlb_lld_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
788 if (tlb_lld_4k
[ENTRIES
] < intel_tlb_table
[k
].entries
)
789 tlb_lld_4k
[ENTRIES
] = intel_tlb_table
[k
].entries
;
790 if (tlb_lld_4m
[ENTRIES
] < intel_tlb_table
[k
].entries
)
791 tlb_lld_4m
[ENTRIES
] = intel_tlb_table
[k
].entries
;
794 if (tlb_lld_1g
[ENTRIES
] < intel_tlb_table
[k
].entries
)
795 tlb_lld_1g
[ENTRIES
] = intel_tlb_table
[k
].entries
;
800 static void intel_detect_tlb(struct cpuinfo_x86
*c
)
803 unsigned int regs
[4];
804 unsigned char *desc
= (unsigned char *)regs
;
806 if (c
->cpuid_level
< 2)
809 /* Number of times to iterate */
810 n
= cpuid_eax(2) & 0xFF;
812 for (i
= 0 ; i
< n
; i
++) {
813 cpuid(2, ®s
[0], ®s
[1], ®s
[2], ®s
[3]);
815 /* If bit 31 is set, this is an unknown format */
816 for (j
= 0 ; j
< 3 ; j
++)
817 if (regs
[j
] & (1 << 31))
820 /* Byte 0 is level count, not a descriptor */
821 for (j
= 1 ; j
< 16 ; j
++)
822 intel_tlb_lookup(desc
[j
]);
826 static const struct cpu_dev intel_cpu_dev
= {
828 .c_ident
= { "GenuineIntel" },
831 { .family
= 4, .model_names
=
833 [0] = "486 DX-25/33",
844 { .family
= 5, .model_names
=
846 [0] = "Pentium 60/66 A-step",
847 [1] = "Pentium 60/66",
848 [2] = "Pentium 75 - 200",
849 [3] = "OverDrive PODP5V83",
851 [7] = "Mobile Pentium 75 - 200",
852 [8] = "Mobile Pentium MMX",
853 [9] = "Quark SoC X1000",
856 { .family
= 6, .model_names
=
858 [0] = "Pentium Pro A-step",
860 [3] = "Pentium II (Klamath)",
861 [4] = "Pentium II (Deschutes)",
862 [5] = "Pentium II (Deschutes)",
863 [6] = "Mobile Pentium II",
864 [7] = "Pentium III (Katmai)",
865 [8] = "Pentium III (Coppermine)",
866 [10] = "Pentium III (Cascades)",
867 [11] = "Pentium III (Tualatin)",
870 { .family
= 15, .model_names
=
872 [0] = "Pentium 4 (Unknown)",
873 [1] = "Pentium 4 (Willamette)",
874 [2] = "Pentium 4 (Northwood)",
875 [4] = "Pentium 4 (Foster)",
876 [5] = "Pentium 4 (Foster)",
880 .legacy_cache_size
= intel_size_cache
,
882 .c_detect_tlb
= intel_detect_tlb
,
883 .c_early_init
= early_init_intel
,
884 .c_init
= init_intel
,
885 .c_bsp_resume
= intel_bsp_resume
,
886 .c_x86_vendor
= X86_VENDOR_INTEL
,
889 cpu_dev_register(intel_cpu_dev
);