2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #include <linux/thread_info.h>
12 #include <linux/capability.h>
13 #include <linux/miscdevice.h>
14 #include <linux/ratelimit.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/device.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/ras.h>
36 #include <linux/smp.h>
39 #include <linux/debugfs.h>
40 #include <linux/irq_work.h>
41 #include <linux/export.h>
42 #include <linux/jump_label.h>
43 #include <linux/set_memory.h>
45 #include <asm/intel-family.h>
46 #include <asm/processor.h>
47 #include <asm/traps.h>
48 #include <asm/tlbflush.h>
51 #include <asm/reboot.h>
55 static DEFINE_MUTEX(mce_log_mutex
);
57 /* sysfs synchronization */
58 static DEFINE_MUTEX(mce_sysfs_mutex
);
60 #define CREATE_TRACE_POINTS
61 #include <trace/events/mce.h>
63 #define SPINUNIT 100 /* 100ns */
65 DEFINE_PER_CPU(unsigned, mce_exception_count
);
67 struct mce_bank
*mce_banks __read_mostly
;
68 struct mce_vendor_flags mce_flags __read_mostly
;
70 struct mca_config mca_cfg __read_mostly
= {
74 * 0: always panic on uncorrected errors, log corrected errors
75 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
76 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
77 * 3: never panic or SIGBUS, log all errors (for testing only)
83 static DEFINE_PER_CPU(struct mce
, mces_seen
);
84 static unsigned long mce_need_notify
;
85 static int cpu_missing
;
88 * MCA banks polled by the period polling timer for corrected events.
89 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
91 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
92 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
96 * MCA banks controlled through firmware first for corrected errors.
97 * This is a global list of banks for which we won't enable CMCI and we
98 * won't poll. Firmware controls these banks and is responsible for
99 * reporting corrected errors through GHES. Uncorrected/recoverable
100 * errors are still notified through a machine check.
102 mce_banks_t mce_banks_ce_disabled
;
104 static struct work_struct mce_work
;
105 static struct irq_work mce_irq_work
;
107 static void (*quirk_no_way_out
)(int bank
, struct mce
*m
, struct pt_regs
*regs
);
110 * CPU/chipset specific EDAC code can register a notifier call here to print
111 * MCE errors in a human-readable form.
113 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain
);
115 /* Do initial initialization of a struct mce */
116 void mce_setup(struct mce
*m
)
118 memset(m
, 0, sizeof(struct mce
));
119 m
->cpu
= m
->extcpu
= smp_processor_id();
120 /* need the internal __ version to avoid deadlocks */
121 m
->time
= __ktime_get_real_seconds();
122 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
123 m
->cpuid
= cpuid_eax(1);
124 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
125 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
126 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
128 if (this_cpu_has(X86_FEATURE_INTEL_PPIN
))
129 rdmsrl(MSR_PPIN
, m
->ppin
);
131 m
->microcode
= boot_cpu_data
.microcode
;
134 DEFINE_PER_CPU(struct mce
, injectm
);
135 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
137 void mce_log(struct mce
*m
)
139 if (!mce_gen_pool_add(m
))
140 irq_work_queue(&mce_irq_work
);
143 void mce_inject_log(struct mce
*m
)
145 mutex_lock(&mce_log_mutex
);
147 mutex_unlock(&mce_log_mutex
);
149 EXPORT_SYMBOL_GPL(mce_inject_log
);
151 static struct notifier_block mce_srao_nb
;
154 * We run the default notifier if we have only the SRAO, the first and the
155 * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
156 * notifiers registered on the chain.
158 #define NUM_DEFAULT_NOTIFIERS 3
159 static atomic_t num_notifiers
;
161 void mce_register_decode_chain(struct notifier_block
*nb
)
163 if (WARN_ON(nb
->priority
> MCE_PRIO_MCELOG
&& nb
->priority
< MCE_PRIO_EDAC
))
166 atomic_inc(&num_notifiers
);
168 blocking_notifier_chain_register(&x86_mce_decoder_chain
, nb
);
170 EXPORT_SYMBOL_GPL(mce_register_decode_chain
);
172 void mce_unregister_decode_chain(struct notifier_block
*nb
)
174 atomic_dec(&num_notifiers
);
176 blocking_notifier_chain_unregister(&x86_mce_decoder_chain
, nb
);
178 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain
);
180 static inline u32
ctl_reg(int bank
)
182 return MSR_IA32_MCx_CTL(bank
);
185 static inline u32
status_reg(int bank
)
187 return MSR_IA32_MCx_STATUS(bank
);
190 static inline u32
addr_reg(int bank
)
192 return MSR_IA32_MCx_ADDR(bank
);
195 static inline u32
misc_reg(int bank
)
197 return MSR_IA32_MCx_MISC(bank
);
200 static inline u32
smca_ctl_reg(int bank
)
202 return MSR_AMD64_SMCA_MCx_CTL(bank
);
205 static inline u32
smca_status_reg(int bank
)
207 return MSR_AMD64_SMCA_MCx_STATUS(bank
);
210 static inline u32
smca_addr_reg(int bank
)
212 return MSR_AMD64_SMCA_MCx_ADDR(bank
);
215 static inline u32
smca_misc_reg(int bank
)
217 return MSR_AMD64_SMCA_MCx_MISC(bank
);
220 struct mca_msr_regs msr_ops
= {
222 .status
= status_reg
,
227 static void __print_mce(struct mce
*m
)
229 pr_emerg(HW_ERR
"CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
231 (m
->mcgstatus
& MCG_STATUS_MCIP
? " Exception" : ""),
232 m
->mcgstatus
, m
->bank
, m
->status
);
235 pr_emerg(HW_ERR
"RIP%s %02x:<%016Lx> ",
236 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
239 if (m
->cs
== __KERNEL_CS
)
240 pr_cont("{%pS}", (void *)(unsigned long)m
->ip
);
244 pr_emerg(HW_ERR
"TSC %llx ", m
->tsc
);
246 pr_cont("ADDR %llx ", m
->addr
);
248 pr_cont("MISC %llx ", m
->misc
);
250 if (mce_flags
.smca
) {
252 pr_cont("SYND %llx ", m
->synd
);
254 pr_cont("IPID %llx ", m
->ipid
);
259 * Note this output is parsed by external tools and old fields
260 * should not be changed.
262 pr_emerg(HW_ERR
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
263 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
,
267 static void print_mce(struct mce
*m
)
271 if (m
->cpuvendor
!= X86_VENDOR_AMD
&& m
->cpuvendor
!= X86_VENDOR_HYGON
)
272 pr_emerg_ratelimited(HW_ERR
"Run the above through 'mcelog --ascii'\n");
275 #define PANIC_TIMEOUT 5 /* 5 seconds */
277 static atomic_t mce_panicked
;
279 static int fake_panic
;
280 static atomic_t mce_fake_panicked
;
282 /* Panic in progress. Enable interrupts and wait for final IPI */
283 static void wait_for_panic(void)
285 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
289 while (timeout
-- > 0)
291 if (panic_timeout
== 0)
292 panic_timeout
= mca_cfg
.panic_timeout
;
293 panic("Panicing machine check CPU died");
296 static void mce_panic(const char *msg
, struct mce
*final
, char *exp
)
299 struct llist_node
*pending
;
300 struct mce_evt_llist
*l
;
304 * Make sure only one CPU runs in machine check panic
306 if (atomic_inc_return(&mce_panicked
) > 1)
313 /* Don't log too much for fake panic */
314 if (atomic_inc_return(&mce_fake_panicked
) > 1)
317 pending
= mce_gen_pool_prepare_records();
318 /* First print corrected ones that are still unlogged */
319 llist_for_each_entry(l
, pending
, llnode
) {
320 struct mce
*m
= &l
->mce
;
321 if (!(m
->status
& MCI_STATUS_UC
)) {
324 apei_err
= apei_write_mce(m
);
327 /* Now print uncorrected but with the final one last */
328 llist_for_each_entry(l
, pending
, llnode
) {
329 struct mce
*m
= &l
->mce
;
330 if (!(m
->status
& MCI_STATUS_UC
))
332 if (!final
|| mce_cmp(m
, final
)) {
335 apei_err
= apei_write_mce(m
);
341 apei_err
= apei_write_mce(final
);
344 pr_emerg(HW_ERR
"Some CPUs didn't answer in synchronization\n");
346 pr_emerg(HW_ERR
"Machine check: %s\n", exp
);
348 if (panic_timeout
== 0)
349 panic_timeout
= mca_cfg
.panic_timeout
;
352 pr_emerg(HW_ERR
"Fake kernel panic: %s\n", msg
);
355 /* Support code for software error injection */
357 static int msr_to_offset(u32 msr
)
359 unsigned bank
= __this_cpu_read(injectm
.bank
);
361 if (msr
== mca_cfg
.rip_msr
)
362 return offsetof(struct mce
, ip
);
363 if (msr
== msr_ops
.status(bank
))
364 return offsetof(struct mce
, status
);
365 if (msr
== msr_ops
.addr(bank
))
366 return offsetof(struct mce
, addr
);
367 if (msr
== msr_ops
.misc(bank
))
368 return offsetof(struct mce
, misc
);
369 if (msr
== MSR_IA32_MCG_STATUS
)
370 return offsetof(struct mce
, mcgstatus
);
374 /* MSR access wrappers used for error injection */
375 static u64
mce_rdmsrl(u32 msr
)
379 if (__this_cpu_read(injectm
.finished
)) {
380 int offset
= msr_to_offset(msr
);
384 return *(u64
*)((char *)this_cpu_ptr(&injectm
) + offset
);
387 if (rdmsrl_safe(msr
, &v
)) {
388 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr
);
390 * Return zero in case the access faulted. This should
391 * not happen normally but can happen if the CPU does
392 * something weird, or if the code is buggy.
400 static void mce_wrmsrl(u32 msr
, u64 v
)
402 if (__this_cpu_read(injectm
.finished
)) {
403 int offset
= msr_to_offset(msr
);
406 *(u64
*)((char *)this_cpu_ptr(&injectm
) + offset
) = v
;
413 * Collect all global (w.r.t. this processor) status about this machine
414 * check into our "mce" struct so that we can use it later to assess
415 * the severity of the problem as we read per-bank specific details.
417 static inline void mce_gather_info(struct mce
*m
, struct pt_regs
*regs
)
421 m
->mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
424 * Get the address of the instruction at the time of
425 * the machine check error.
427 if (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
)) {
432 * When in VM86 mode make the cs look like ring 3
433 * always. This is a lie, but it's better than passing
434 * the additional vm86 bit around everywhere.
436 if (v8086_mode(regs
))
439 /* Use accurate RIP reporting if available. */
441 m
->ip
= mce_rdmsrl(mca_cfg
.rip_msr
);
445 int mce_available(struct cpuinfo_x86
*c
)
447 if (mca_cfg
.disabled
)
449 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
452 static void mce_schedule_work(void)
454 if (!mce_gen_pool_empty())
455 schedule_work(&mce_work
);
458 static void mce_irq_work_cb(struct irq_work
*entry
)
463 static void mce_report_event(struct pt_regs
*regs
)
465 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
468 * Triggering the work queue here is just an insurance
469 * policy in case the syscall exit notify handler
470 * doesn't run soon enough or ends up running on the
471 * wrong CPU (can happen when audit sleeps)
477 irq_work_queue(&mce_irq_work
);
481 * Check if the address reported by the CPU is in a format we can parse.
482 * It would be possible to add code for most other cases, but all would
483 * be somewhat complicated (e.g. segment offset would require an instruction
484 * parser). So only support physical addresses up to page granuality for now.
486 int mce_usable_address(struct mce
*m
)
488 if (!(m
->status
& MCI_STATUS_ADDRV
))
491 /* Checks after this one are Intel-specific: */
492 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
495 if (!(m
->status
& MCI_STATUS_MISCV
))
498 if (MCI_MISC_ADDR_LSB(m
->misc
) > PAGE_SHIFT
)
501 if (MCI_MISC_ADDR_MODE(m
->misc
) != MCI_MISC_ADDR_PHYS
)
506 EXPORT_SYMBOL_GPL(mce_usable_address
);
508 bool mce_is_memory_error(struct mce
*m
)
510 if (m
->cpuvendor
== X86_VENDOR_AMD
||
511 m
->cpuvendor
== X86_VENDOR_HYGON
) {
512 return amd_mce_is_memory_error(m
);
513 } else if (m
->cpuvendor
== X86_VENDOR_INTEL
) {
515 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
517 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
518 * indicating a memory error. Bit 8 is used for indicating a
519 * cache hierarchy error. The combination of bit 2 and bit 3
520 * is used for indicating a `generic' cache hierarchy error
521 * But we can't just blindly check the above bits, because if
522 * bit 11 is set, then it is a bus/interconnect error - and
523 * either way the above bits just gives more detail on what
524 * bus/interconnect error happened. Note that bit 12 can be
525 * ignored, as it's the "filter" bit.
527 return (m
->status
& 0xef80) == BIT(7) ||
528 (m
->status
& 0xef00) == BIT(8) ||
529 (m
->status
& 0xeffc) == 0xc;
534 EXPORT_SYMBOL_GPL(mce_is_memory_error
);
536 bool mce_is_correctable(struct mce
*m
)
538 if (m
->cpuvendor
== X86_VENDOR_AMD
&& m
->status
& MCI_STATUS_DEFERRED
)
541 if (m
->cpuvendor
== X86_VENDOR_HYGON
&& m
->status
& MCI_STATUS_DEFERRED
)
544 if (m
->status
& MCI_STATUS_UC
)
549 EXPORT_SYMBOL_GPL(mce_is_correctable
);
551 static bool cec_add_mce(struct mce
*m
)
556 /* We eat only correctable DRAM errors with usable addresses. */
557 if (mce_is_memory_error(m
) &&
558 mce_is_correctable(m
) &&
559 mce_usable_address(m
))
560 if (!cec_add_elem(m
->addr
>> PAGE_SHIFT
))
566 static int mce_first_notifier(struct notifier_block
*nb
, unsigned long val
,
569 struct mce
*m
= (struct mce
*)data
;
577 /* Emit the trace record: */
580 set_bit(0, &mce_need_notify
);
587 static struct notifier_block first_nb
= {
588 .notifier_call
= mce_first_notifier
,
589 .priority
= MCE_PRIO_FIRST
,
592 static int srao_decode_notifier(struct notifier_block
*nb
, unsigned long val
,
595 struct mce
*mce
= (struct mce
*)data
;
601 if (mce_usable_address(mce
) && (mce
->severity
== MCE_AO_SEVERITY
)) {
602 pfn
= mce
->addr
>> PAGE_SHIFT
;
603 if (!memory_failure(pfn
, 0))
609 static struct notifier_block mce_srao_nb
= {
610 .notifier_call
= srao_decode_notifier
,
611 .priority
= MCE_PRIO_SRAO
,
614 static int mce_default_notifier(struct notifier_block
*nb
, unsigned long val
,
617 struct mce
*m
= (struct mce
*)data
;
622 if (atomic_read(&num_notifiers
) > NUM_DEFAULT_NOTIFIERS
)
630 static struct notifier_block mce_default_nb
= {
631 .notifier_call
= mce_default_notifier
,
632 /* lowest prio, we want it to run last. */
633 .priority
= MCE_PRIO_LOWEST
,
637 * Read ADDR and MISC registers.
639 static void mce_read_aux(struct mce
*m
, int i
)
641 if (m
->status
& MCI_STATUS_MISCV
)
642 m
->misc
= mce_rdmsrl(msr_ops
.misc(i
));
644 if (m
->status
& MCI_STATUS_ADDRV
) {
645 m
->addr
= mce_rdmsrl(msr_ops
.addr(i
));
648 * Mask the reported address by the reported granularity.
650 if (mca_cfg
.ser
&& (m
->status
& MCI_STATUS_MISCV
)) {
651 u8 shift
= MCI_MISC_ADDR_LSB(m
->misc
);
657 * Extract [55:<lsb>] where lsb is the least significant
658 * *valid* bit of the address bits.
660 if (mce_flags
.smca
) {
661 u8 lsb
= (m
->addr
>> 56) & 0x3f;
663 m
->addr
&= GENMASK_ULL(55, lsb
);
667 if (mce_flags
.smca
) {
668 m
->ipid
= mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i
));
670 if (m
->status
& MCI_STATUS_SYNDV
)
671 m
->synd
= mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i
));
675 DEFINE_PER_CPU(unsigned, mce_poll_count
);
678 * Poll for corrected events or events that happened before reset.
679 * Those are just logged through /dev/mcelog.
681 * This is executed in standard interrupt context.
683 * Note: spec recommends to panic for fatal unsignalled
684 * errors here. However this would be quite problematic --
685 * we would need to reimplement the Monarch handling and
686 * it would mess up the exclusion between exception handler
687 * and poll handler -- * so we skip this for now.
688 * These cases should not happen anyways, or only when the CPU
689 * is already totally * confused. In this case it's likely it will
690 * not fully execute the machine check handler either.
692 bool machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
694 bool error_seen
= false;
698 this_cpu_inc(mce_poll_count
);
700 mce_gather_info(&m
, NULL
);
702 if (flags
& MCP_TIMESTAMP
)
705 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
706 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
714 m
.status
= mce_rdmsrl(msr_ops
.status(i
));
716 /* If this entry is not valid, ignore it */
717 if (!(m
.status
& MCI_STATUS_VAL
))
721 * If we are logging everything (at CPU online) or this
722 * is a corrected error, then we must log it.
724 if ((flags
& MCP_UC
) || !(m
.status
& MCI_STATUS_UC
))
728 * Newer Intel systems that support software error
729 * recovery need to make additional checks. Other
730 * CPUs should skip over uncorrected errors, but log
734 if (m
.status
& MCI_STATUS_UC
)
739 /* Log "not enabled" (speculative) errors */
740 if (!(m
.status
& MCI_STATUS_EN
))
744 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
745 * UC == 1 && PCC == 0 && S == 0
747 if (!(m
.status
& MCI_STATUS_PCC
) && !(m
.status
& MCI_STATUS_S
))
751 * Skip anything else. Presumption is that our read of this
752 * bank is racing with a machine check. Leave the log alone
753 * for do_machine_check() to deal with it.
762 m
.severity
= mce_severity(&m
, mca_cfg
.tolerant
, NULL
, false);
765 * Don't get the IP here because it's unlikely to
766 * have anything to do with the actual error location.
768 if (!(flags
& MCP_DONTLOG
) && !mca_cfg
.dont_log_ce
)
770 else if (mce_usable_address(&m
)) {
772 * Although we skipped logging this, we still want
773 * to take action. Add to the pool so the registered
774 * notifiers will see it.
776 if (!mce_gen_pool_add(&m
))
781 * Clear state for this bank.
783 mce_wrmsrl(msr_ops
.status(i
), 0);
787 * Don't clear MCG_STATUS here because it's only defined for
795 EXPORT_SYMBOL_GPL(machine_check_poll
);
798 * Do a quick check if any of the events requires a panic.
799 * This decides if we keep the events around or clear them.
801 static int mce_no_way_out(struct mce
*m
, char **msg
, unsigned long *validp
,
802 struct pt_regs
*regs
)
807 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
808 m
->status
= mce_rdmsrl(msr_ops
.status(i
));
809 if (!(m
->status
& MCI_STATUS_VAL
))
812 __set_bit(i
, validp
);
813 if (quirk_no_way_out
)
814 quirk_no_way_out(i
, m
, regs
);
816 if (mce_severity(m
, mca_cfg
.tolerant
, &tmp
, true) >= MCE_PANIC_SEVERITY
) {
827 * Variable to establish order between CPUs while scanning.
828 * Each CPU spins initially until executing is equal its number.
830 static atomic_t mce_executing
;
833 * Defines order of CPUs on entry. First CPU becomes Monarch.
835 static atomic_t mce_callin
;
838 * Check if a timeout waiting for other CPUs happened.
840 static int mce_timed_out(u64
*t
, const char *msg
)
843 * The others already did panic for some reason.
844 * Bail out like in a timeout.
845 * rmb() to tell the compiler that system_state
846 * might have been modified by someone else.
849 if (atomic_read(&mce_panicked
))
851 if (!mca_cfg
.monarch_timeout
)
853 if ((s64
)*t
< SPINUNIT
) {
854 if (mca_cfg
.tolerant
<= 1)
855 mce_panic(msg
, NULL
, NULL
);
861 touch_nmi_watchdog();
866 * The Monarch's reign. The Monarch is the CPU who entered
867 * the machine check handler first. It waits for the others to
868 * raise the exception too and then grades them. When any
869 * error is fatal panic. Only then let the others continue.
871 * The other CPUs entering the MCE handler will be controlled by the
872 * Monarch. They are called Subjects.
874 * This way we prevent any potential data corruption in a unrecoverable case
875 * and also makes sure always all CPU's errors are examined.
877 * Also this detects the case of a machine check event coming from outer
878 * space (not detected by any CPUs) In this case some external agent wants
879 * us to shut down, so panic too.
881 * The other CPUs might still decide to panic if the handler happens
882 * in a unrecoverable place, but in this case the system is in a semi-stable
883 * state and won't corrupt anything by itself. It's ok to let the others
884 * continue for a bit first.
886 * All the spin loops have timeouts; when a timeout happens a CPU
887 * typically elects itself to be Monarch.
889 static void mce_reign(void)
892 struct mce
*m
= NULL
;
893 int global_worst
= 0;
898 * This CPU is the Monarch and the other CPUs have run
899 * through their handlers.
900 * Grade the severity of the errors of all the CPUs.
902 for_each_possible_cpu(cpu
) {
903 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
),
906 if (severity
> global_worst
) {
908 global_worst
= severity
;
909 m
= &per_cpu(mces_seen
, cpu
);
914 * Cannot recover? Panic here then.
915 * This dumps all the mces in the log buffer and stops the
918 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& mca_cfg
.tolerant
< 3)
919 mce_panic("Fatal machine check", m
, msg
);
922 * For UC somewhere we let the CPU who detects it handle it.
923 * Also must let continue the others, otherwise the handling
924 * CPU could deadlock on a lock.
928 * No machine check event found. Must be some external
929 * source or one CPU is hung. Panic.
931 if (global_worst
<= MCE_KEEP_SEVERITY
&& mca_cfg
.tolerant
< 3)
932 mce_panic("Fatal machine check from unknown source", NULL
, NULL
);
935 * Now clear all the mces_seen so that they don't reappear on
938 for_each_possible_cpu(cpu
)
939 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
942 static atomic_t global_nwo
;
945 * Start of Monarch synchronization. This waits until all CPUs have
946 * entered the exception handler and then determines if any of them
947 * saw a fatal event that requires panic. Then it executes them
948 * in the entry order.
949 * TBD double check parallel CPU hotunplug
951 static int mce_start(int *no_way_out
)
954 int cpus
= num_online_cpus();
955 u64 timeout
= (u64
)mca_cfg
.monarch_timeout
* NSEC_PER_USEC
;
960 atomic_add(*no_way_out
, &global_nwo
);
962 * Rely on the implied barrier below, such that global_nwo
963 * is updated before mce_callin.
965 order
= atomic_inc_return(&mce_callin
);
970 while (atomic_read(&mce_callin
) != cpus
) {
971 if (mce_timed_out(&timeout
,
972 "Timeout: Not all CPUs entered broadcast exception handler")) {
973 atomic_set(&global_nwo
, 0);
980 * mce_callin should be read before global_nwo
986 * Monarch: Starts executing now, the others wait.
988 atomic_set(&mce_executing
, 1);
991 * Subject: Now start the scanning loop one by one in
992 * the original callin order.
993 * This way when there are any shared banks it will be
994 * only seen by one CPU before cleared, avoiding duplicates.
996 while (atomic_read(&mce_executing
) < order
) {
997 if (mce_timed_out(&timeout
,
998 "Timeout: Subject CPUs unable to finish machine check processing")) {
999 atomic_set(&global_nwo
, 0);
1007 * Cache the global no_way_out state.
1009 *no_way_out
= atomic_read(&global_nwo
);
1015 * Synchronize between CPUs after main scanning loop.
1016 * This invokes the bulk of the Monarch processing.
1018 static int mce_end(int order
)
1021 u64 timeout
= (u64
)mca_cfg
.monarch_timeout
* NSEC_PER_USEC
;
1029 * Allow others to run.
1031 atomic_inc(&mce_executing
);
1034 /* CHECKME: Can this race with a parallel hotplug? */
1035 int cpus
= num_online_cpus();
1038 * Monarch: Wait for everyone to go through their scanning
1041 while (atomic_read(&mce_executing
) <= cpus
) {
1042 if (mce_timed_out(&timeout
,
1043 "Timeout: Monarch CPU unable to finish machine check processing"))
1053 * Subject: Wait for Monarch to finish.
1055 while (atomic_read(&mce_executing
) != 0) {
1056 if (mce_timed_out(&timeout
,
1057 "Timeout: Monarch CPU did not finish machine check processing"))
1063 * Don't reset anything. That's done by the Monarch.
1069 * Reset all global state.
1072 atomic_set(&global_nwo
, 0);
1073 atomic_set(&mce_callin
, 0);
1077 * Let others run again.
1079 atomic_set(&mce_executing
, 0);
1083 static void mce_clear_state(unsigned long *toclear
)
1087 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
1088 if (test_bit(i
, toclear
))
1089 mce_wrmsrl(msr_ops
.status(i
), 0);
1093 static int do_memory_failure(struct mce
*m
)
1095 int flags
= MF_ACTION_REQUIRED
;
1098 pr_err("Uncorrected hardware memory error in user-access at %llx", m
->addr
);
1099 if (!(m
->mcgstatus
& MCG_STATUS_RIPV
))
1100 flags
|= MF_MUST_KILL
;
1101 ret
= memory_failure(m
->addr
>> PAGE_SHIFT
, flags
);
1103 pr_err("Memory error not recovered");
1105 set_mce_nospec(m
->addr
>> PAGE_SHIFT
);
1111 * Cases where we avoid rendezvous handler timeout:
1112 * 1) If this CPU is offline.
1114 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1115 * skip those CPUs which remain looping in the 1st kernel - see
1116 * crash_nmi_callback().
1118 * Note: there still is a small window between kexec-ing and the new,
1119 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1120 * might not get handled properly.
1122 static bool __mc_check_crashing_cpu(int cpu
)
1124 if (cpu_is_offline(cpu
) ||
1125 (crashing_cpu
!= -1 && crashing_cpu
!= cpu
)) {
1128 mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
1129 if (mcgstatus
& MCG_STATUS_RIPV
) {
1130 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1137 static void __mc_scan_banks(struct mce
*m
, struct mce
*final
,
1138 unsigned long *toclear
, unsigned long *valid_banks
,
1139 int no_way_out
, int *worst
)
1141 struct mca_config
*cfg
= &mca_cfg
;
1144 for (i
= 0; i
< cfg
->banks
; i
++) {
1145 __clear_bit(i
, toclear
);
1146 if (!test_bit(i
, valid_banks
))
1149 if (!mce_banks
[i
].ctl
)
1156 m
->status
= mce_rdmsrl(msr_ops
.status(i
));
1157 if (!(m
->status
& MCI_STATUS_VAL
))
1161 * Corrected or non-signaled errors are handled by
1162 * machine_check_poll(). Leave them alone, unless this panics.
1164 if (!(m
->status
& (cfg
->ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
1168 /* Set taint even when machine check was not enabled. */
1169 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
1171 severity
= mce_severity(m
, cfg
->tolerant
, NULL
, true);
1174 * When machine check was for corrected/deferred handler don't
1175 * touch, unless we're panicking.
1177 if ((severity
== MCE_KEEP_SEVERITY
||
1178 severity
== MCE_UCNA_SEVERITY
) && !no_way_out
)
1181 __set_bit(i
, toclear
);
1183 /* Machine check event was not enabled. Clear, but ignore. */
1184 if (severity
== MCE_NO_SEVERITY
)
1189 /* assuming valid severity level != 0 */
1190 m
->severity
= severity
;
1194 if (severity
> *worst
) {
1200 /* mce_clear_state will clear *final, save locally for use later */
1205 * The actual machine check handler. This only handles real
1206 * exceptions when something got corrupted coming in through int 18.
1208 * This is executed in NMI context not subject to normal locking rules. This
1209 * implies that most kernel services cannot be safely used. Don't even
1210 * think about putting a printk in there!
1212 * On Intel systems this is entered on all CPUs in parallel through
1213 * MCE broadcast. However some CPUs might be broken beyond repair,
1214 * so be always careful when synchronizing with others.
1216 void do_machine_check(struct pt_regs
*regs
, long error_code
)
1218 DECLARE_BITMAP(valid_banks
, MAX_NR_BANKS
);
1219 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
1220 struct mca_config
*cfg
= &mca_cfg
;
1221 int cpu
= smp_processor_id();
1222 char *msg
= "Unknown";
1223 struct mce m
, *final
;
1227 * Establish sequential order between the CPUs entering the machine
1233 * If no_way_out gets set, there is no safe way to recover from this
1234 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1239 * If kill_it gets set, there might be a way to recover from this
1245 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1250 if (__mc_check_crashing_cpu(cpu
))
1255 this_cpu_inc(mce_exception_count
);
1257 mce_gather_info(&m
, regs
);
1260 final
= this_cpu_ptr(&mces_seen
);
1263 memset(valid_banks
, 0, sizeof(valid_banks
));
1264 no_way_out
= mce_no_way_out(&m
, &msg
, valid_banks
, regs
);
1269 * When no restart IP might need to kill or panic.
1270 * Assume the worst for now, but if we find the
1271 * severity is MCE_AR_SEVERITY we have other options.
1273 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
1277 * Check if this MCE is signaled to only this logical processor,
1280 if (m
.cpuvendor
== X86_VENDOR_INTEL
)
1281 lmce
= m
.mcgstatus
& MCG_STATUS_LMCES
;
1284 * Local machine check may already know that we have to panic.
1285 * Broadcast machine check begins rendezvous in mce_start()
1286 * Go through all banks in exclusion of the other CPUs. This way we
1287 * don't report duplicated events on shared banks because the first one
1288 * to see it will clear it.
1292 mce_panic("Fatal local machine check", &m
, msg
);
1294 order
= mce_start(&no_way_out
);
1297 __mc_scan_banks(&m
, final
, toclear
, valid_banks
, no_way_out
, &worst
);
1300 mce_clear_state(toclear
);
1303 * Do most of the synchronization with other CPUs.
1304 * When there's any problem use only local no_way_out state.
1307 if (mce_end(order
) < 0)
1308 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1311 * If there was a fatal machine check we should have
1312 * already called mce_panic earlier in this function.
1313 * Since we re-read the banks, we might have found
1314 * something new. Check again to see if we found a
1315 * fatal error. We call "mce_severity()" again to
1316 * make sure we have the right "msg".
1318 if (worst
>= MCE_PANIC_SEVERITY
&& mca_cfg
.tolerant
< 3) {
1319 mce_severity(&m
, cfg
->tolerant
, &msg
, true);
1320 mce_panic("Local fatal machine check!", &m
, msg
);
1325 * If tolerant is at an insane level we drop requests to kill
1326 * processes and continue even when there is no way out.
1328 if (cfg
->tolerant
== 3)
1330 else if (no_way_out
)
1331 mce_panic("Fatal machine check on current CPU", &m
, msg
);
1334 mce_report_event(regs
);
1335 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1339 if (worst
!= MCE_AR_SEVERITY
&& !kill_it
)
1342 /* Fault was in user mode and we need to take some action */
1343 if ((m
.cs
& 3) == 3) {
1344 ist_begin_non_atomic(regs
);
1347 if (kill_it
|| do_memory_failure(&m
))
1348 force_sig(SIGBUS
, current
);
1349 local_irq_disable();
1350 ist_end_non_atomic();
1352 if (!fixup_exception(regs
, X86_TRAP_MC
, error_code
, 0))
1353 mce_panic("Failed kernel mode recovery", &m
, NULL
);
1359 EXPORT_SYMBOL_GPL(do_machine_check
);
1361 #ifndef CONFIG_MEMORY_FAILURE
1362 int memory_failure(unsigned long pfn
, int flags
)
1364 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1365 BUG_ON(flags
& MF_ACTION_REQUIRED
);
1366 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1367 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1375 * Periodic polling timer for "silent" machine check errors. If the
1376 * poller finds an MCE, poll 2x faster. When the poller finds no more
1377 * errors, poll 2x slower (up to check_interval seconds).
1379 static unsigned long check_interval
= INITIAL_CHECK_INTERVAL
;
1381 static DEFINE_PER_CPU(unsigned long, mce_next_interval
); /* in jiffies */
1382 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1384 static unsigned long mce_adjust_timer_default(unsigned long interval
)
1389 static unsigned long (*mce_adjust_timer
)(unsigned long interval
) = mce_adjust_timer_default
;
1391 static void __start_timer(struct timer_list
*t
, unsigned long interval
)
1393 unsigned long when
= jiffies
+ interval
;
1394 unsigned long flags
;
1396 local_irq_save(flags
);
1398 if (!timer_pending(t
) || time_before(when
, t
->expires
))
1399 mod_timer(t
, round_jiffies(when
));
1401 local_irq_restore(flags
);
1404 static void mce_timer_fn(struct timer_list
*t
)
1406 struct timer_list
*cpu_t
= this_cpu_ptr(&mce_timer
);
1409 WARN_ON(cpu_t
!= t
);
1411 iv
= __this_cpu_read(mce_next_interval
);
1413 if (mce_available(this_cpu_ptr(&cpu_info
))) {
1414 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks
));
1416 if (mce_intel_cmci_poll()) {
1417 iv
= mce_adjust_timer(iv
);
1423 * Alert userspace if needed. If we logged an MCE, reduce the polling
1424 * interval, otherwise increase the polling interval.
1426 if (mce_notify_irq())
1427 iv
= max(iv
/ 2, (unsigned long) HZ
/100);
1429 iv
= min(iv
* 2, round_jiffies_relative(check_interval
* HZ
));
1432 __this_cpu_write(mce_next_interval
, iv
);
1433 __start_timer(t
, iv
);
1437 * Ensure that the timer is firing in @interval from now.
1439 void mce_timer_kick(unsigned long interval
)
1441 struct timer_list
*t
= this_cpu_ptr(&mce_timer
);
1442 unsigned long iv
= __this_cpu_read(mce_next_interval
);
1444 __start_timer(t
, interval
);
1447 __this_cpu_write(mce_next_interval
, interval
);
1450 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1451 static void mce_timer_delete_all(void)
1455 for_each_online_cpu(cpu
)
1456 del_timer_sync(&per_cpu(mce_timer
, cpu
));
1460 * Notify the user(s) about new machine check events.
1461 * Can be called from interrupt context, but not from machine check/NMI
1464 int mce_notify_irq(void)
1466 /* Not more than two messages every minute */
1467 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1469 if (test_and_clear_bit(0, &mce_need_notify
)) {
1472 if (__ratelimit(&ratelimit
))
1473 pr_info(HW_ERR
"Machine check events logged\n");
1479 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1481 static int __mcheck_cpu_mce_banks_init(void)
1485 mce_banks
= kcalloc(MAX_NR_BANKS
, sizeof(struct mce_bank
), GFP_KERNEL
);
1489 for (i
= 0; i
< MAX_NR_BANKS
; i
++) {
1490 struct mce_bank
*b
= &mce_banks
[i
];
1499 * Initialize Machine Checks for a CPU.
1501 static int __mcheck_cpu_cap_init(void)
1506 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1508 b
= cap
& MCG_BANKCNT_MASK
;
1509 if (WARN_ON_ONCE(b
> MAX_NR_BANKS
))
1512 mca_cfg
.banks
= max(mca_cfg
.banks
, b
);
1515 int err
= __mcheck_cpu_mce_banks_init();
1520 /* Use accurate RIP reporting if available. */
1521 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1522 mca_cfg
.rip_msr
= MSR_IA32_MCG_EIP
;
1524 if (cap
& MCG_SER_P
)
1530 static void __mcheck_cpu_init_generic(void)
1532 enum mcp_flags m_fl
= 0;
1533 mce_banks_t all_banks
;
1536 if (!mca_cfg
.bootlog
)
1540 * Log the machine checks left over from the previous reset.
1542 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1543 machine_check_poll(MCP_UC
| m_fl
, &all_banks
);
1545 cr4_set_bits(X86_CR4_MCE
);
1547 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1548 if (cap
& MCG_CTL_P
)
1549 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1552 static void __mcheck_cpu_init_clear_banks(void)
1556 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
1557 struct mce_bank
*b
= &mce_banks
[i
];
1561 wrmsrl(msr_ops
.ctl(i
), b
->ctl
);
1562 wrmsrl(msr_ops
.status(i
), 0);
1567 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1568 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1569 * Vol 3B Table 15-20). But this confuses both the code that determines
1570 * whether the machine check occurred in kernel or user mode, and also
1571 * the severity assessment code. Pretend that EIPV was set, and take the
1572 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1574 static void quirk_sandybridge_ifu(int bank
, struct mce
*m
, struct pt_regs
*regs
)
1578 if ((m
->mcgstatus
& (MCG_STATUS_EIPV
|MCG_STATUS_RIPV
)) != 0)
1580 if ((m
->status
& (MCI_STATUS_OVER
|MCI_STATUS_UC
|
1581 MCI_STATUS_EN
|MCI_STATUS_MISCV
|MCI_STATUS_ADDRV
|
1582 MCI_STATUS_PCC
|MCI_STATUS_S
|MCI_STATUS_AR
|
1584 (MCI_STATUS_UC
|MCI_STATUS_EN
|
1585 MCI_STATUS_MISCV
|MCI_STATUS_ADDRV
|MCI_STATUS_S
|
1586 MCI_STATUS_AR
|MCACOD_INSTR
))
1589 m
->mcgstatus
|= MCG_STATUS_EIPV
;
1594 /* Add per CPU specific workarounds here */
1595 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1597 struct mca_config
*cfg
= &mca_cfg
;
1599 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1600 pr_info("unknown CPU type - not enabling MCE support\n");
1604 /* This should be disabled by the BIOS, but isn't always */
1605 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1606 if (c
->x86
== 15 && cfg
->banks
> 4) {
1608 * disable GART TBL walk error reporting, which
1609 * trips off incorrectly with the IOMMU & 3ware
1612 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1614 if (c
->x86
< 0x11 && cfg
->bootlog
< 0) {
1616 * Lots of broken BIOS around that don't clear them
1617 * by default and leave crap in there. Don't log:
1622 * Various K7s with broken bank 0 around. Always disable
1625 if (c
->x86
== 6 && cfg
->banks
> 0)
1626 mce_banks
[0].ctl
= 0;
1629 * overflow_recov is supported for F15h Models 00h-0fh
1630 * even though we don't have a CPUID bit for it.
1632 if (c
->x86
== 0x15 && c
->x86_model
<= 0xf)
1633 mce_flags
.overflow_recov
= 1;
1637 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1639 * SDM documents that on family 6 bank 0 should not be written
1640 * because it aliases to another special BIOS controlled
1642 * But it's not aliased anymore on model 0x1a+
1643 * Don't ignore bank 0 completely because there could be a
1644 * valid event later, merely don't write CTL0.
1647 if (c
->x86
== 6 && c
->x86_model
< 0x1A && cfg
->banks
> 0)
1648 mce_banks
[0].init
= 0;
1651 * All newer Intel systems support MCE broadcasting. Enable
1652 * synchronization with a one second timeout.
1654 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1655 cfg
->monarch_timeout
< 0)
1656 cfg
->monarch_timeout
= USEC_PER_SEC
;
1659 * There are also broken BIOSes on some Pentium M and
1662 if (c
->x86
== 6 && c
->x86_model
<= 13 && cfg
->bootlog
< 0)
1665 if (c
->x86
== 6 && c
->x86_model
== 45)
1666 quirk_no_way_out
= quirk_sandybridge_ifu
;
1668 if (cfg
->monarch_timeout
< 0)
1669 cfg
->monarch_timeout
= 0;
1670 if (cfg
->bootlog
!= 0)
1671 cfg
->panic_timeout
= 30;
1676 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1681 switch (c
->x86_vendor
) {
1682 case X86_VENDOR_INTEL
:
1683 intel_p5_mcheck_init(c
);
1686 case X86_VENDOR_CENTAUR
:
1687 winchip_mcheck_init(c
);
1698 * Init basic CPU features needed for early decoding of MCEs.
1700 static void __mcheck_cpu_init_early(struct cpuinfo_x86
*c
)
1702 if (c
->x86_vendor
== X86_VENDOR_AMD
|| c
->x86_vendor
== X86_VENDOR_HYGON
) {
1703 mce_flags
.overflow_recov
= !!cpu_has(c
, X86_FEATURE_OVERFLOW_RECOV
);
1704 mce_flags
.succor
= !!cpu_has(c
, X86_FEATURE_SUCCOR
);
1705 mce_flags
.smca
= !!cpu_has(c
, X86_FEATURE_SMCA
);
1707 if (mce_flags
.smca
) {
1708 msr_ops
.ctl
= smca_ctl_reg
;
1709 msr_ops
.status
= smca_status_reg
;
1710 msr_ops
.addr
= smca_addr_reg
;
1711 msr_ops
.misc
= smca_misc_reg
;
1716 static void mce_centaur_feature_init(struct cpuinfo_x86
*c
)
1718 struct mca_config
*cfg
= &mca_cfg
;
1721 * All newer Centaur CPUs support MCE broadcasting. Enable
1722 * synchronization with a one second timeout.
1724 if ((c
->x86
== 6 && c
->x86_model
== 0xf && c
->x86_stepping
>= 0xe) ||
1726 if (cfg
->monarch_timeout
< 0)
1727 cfg
->monarch_timeout
= USEC_PER_SEC
;
1731 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1733 switch (c
->x86_vendor
) {
1734 case X86_VENDOR_INTEL
:
1735 mce_intel_feature_init(c
);
1736 mce_adjust_timer
= cmci_intel_adjust_timer
;
1739 case X86_VENDOR_AMD
: {
1740 mce_amd_feature_init(c
);
1744 case X86_VENDOR_HYGON
:
1745 mce_hygon_feature_init(c
);
1748 case X86_VENDOR_CENTAUR
:
1749 mce_centaur_feature_init(c
);
1757 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86
*c
)
1759 switch (c
->x86_vendor
) {
1760 case X86_VENDOR_INTEL
:
1761 mce_intel_feature_clear(c
);
1768 static void mce_start_timer(struct timer_list
*t
)
1770 unsigned long iv
= check_interval
* HZ
;
1772 if (mca_cfg
.ignore_ce
|| !iv
)
1775 this_cpu_write(mce_next_interval
, iv
);
1776 __start_timer(t
, iv
);
1779 static void __mcheck_cpu_setup_timer(void)
1781 struct timer_list
*t
= this_cpu_ptr(&mce_timer
);
1783 timer_setup(t
, mce_timer_fn
, TIMER_PINNED
);
1786 static void __mcheck_cpu_init_timer(void)
1788 struct timer_list
*t
= this_cpu_ptr(&mce_timer
);
1790 timer_setup(t
, mce_timer_fn
, TIMER_PINNED
);
1794 /* Handle unconfigured int18 (should never happen) */
1795 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1797 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1798 smp_processor_id());
1801 /* Call the installed machine check handler for this CPU setup. */
1802 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1803 unexpected_machine_check
;
1805 dotraplinkage
void do_mce(struct pt_regs
*regs
, long error_code
)
1807 machine_check_vector(regs
, error_code
);
1811 * Called for each booted CPU to set up machine checks.
1812 * Must be called with preempt off:
1814 void mcheck_cpu_init(struct cpuinfo_x86
*c
)
1816 if (mca_cfg
.disabled
)
1819 if (__mcheck_cpu_ancient_init(c
))
1822 if (!mce_available(c
))
1825 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1826 mca_cfg
.disabled
= 1;
1830 if (mce_gen_pool_init()) {
1831 mca_cfg
.disabled
= 1;
1832 pr_emerg("Couldn't allocate MCE records pool!\n");
1836 machine_check_vector
= do_machine_check
;
1838 __mcheck_cpu_init_early(c
);
1839 __mcheck_cpu_init_generic();
1840 __mcheck_cpu_init_vendor(c
);
1841 __mcheck_cpu_init_clear_banks();
1842 __mcheck_cpu_setup_timer();
1846 * Called for each booted CPU to clear some machine checks opt-ins
1848 void mcheck_cpu_clear(struct cpuinfo_x86
*c
)
1850 if (mca_cfg
.disabled
)
1853 if (!mce_available(c
))
1857 * Possibly to clear general settings generic to x86
1858 * __mcheck_cpu_clear_generic(c);
1860 __mcheck_cpu_clear_vendor(c
);
1864 static void __mce_disable_bank(void *arg
)
1866 int bank
= *((int *)arg
);
1867 __clear_bit(bank
, this_cpu_ptr(mce_poll_banks
));
1868 cmci_disable_bank(bank
);
1871 void mce_disable_bank(int bank
)
1873 if (bank
>= mca_cfg
.banks
) {
1875 "Ignoring request to disable invalid MCA bank %d.\n",
1879 set_bit(bank
, mce_banks_ce_disabled
);
1880 on_each_cpu(__mce_disable_bank
, &bank
, 1);
1884 * mce=off Disables machine check
1885 * mce=no_cmci Disables CMCI
1886 * mce=no_lmce Disables LMCE
1887 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1888 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1889 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1890 * monarchtimeout is how long to wait for other CPUs on machine
1891 * check, or 0 to not wait
1892 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
1894 * mce=nobootlog Don't log MCEs from before booting.
1895 * mce=bios_cmci_threshold Don't program the CMCI threshold
1896 * mce=recovery force enable memcpy_mcsafe()
1898 static int __init
mcheck_enable(char *str
)
1900 struct mca_config
*cfg
= &mca_cfg
;
1908 if (!strcmp(str
, "off"))
1910 else if (!strcmp(str
, "no_cmci"))
1911 cfg
->cmci_disabled
= true;
1912 else if (!strcmp(str
, "no_lmce"))
1913 cfg
->lmce_disabled
= 1;
1914 else if (!strcmp(str
, "dont_log_ce"))
1915 cfg
->dont_log_ce
= true;
1916 else if (!strcmp(str
, "ignore_ce"))
1917 cfg
->ignore_ce
= true;
1918 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1919 cfg
->bootlog
= (str
[0] == 'b');
1920 else if (!strcmp(str
, "bios_cmci_threshold"))
1921 cfg
->bios_cmci_threshold
= 1;
1922 else if (!strcmp(str
, "recovery"))
1924 else if (isdigit(str
[0])) {
1925 if (get_option(&str
, &cfg
->tolerant
) == 2)
1926 get_option(&str
, &(cfg
->monarch_timeout
));
1928 pr_info("mce argument %s ignored. Please use /sys\n", str
);
1933 __setup("mce", mcheck_enable
);
1935 int __init
mcheck_init(void)
1937 mcheck_intel_therm_init();
1938 mce_register_decode_chain(&first_nb
);
1939 mce_register_decode_chain(&mce_srao_nb
);
1940 mce_register_decode_chain(&mce_default_nb
);
1941 mcheck_vendor_init_severity();
1943 INIT_WORK(&mce_work
, mce_gen_pool_process
);
1944 init_irq_work(&mce_irq_work
, mce_irq_work_cb
);
1950 * mce_syscore: PM support
1954 * Disable machine checks on suspend and shutdown. We can't really handle
1957 static void mce_disable_error_reporting(void)
1961 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
1962 struct mce_bank
*b
= &mce_banks
[i
];
1965 wrmsrl(msr_ops
.ctl(i
), 0);
1970 static void vendor_disable_error_reporting(void)
1973 * Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
1975 * Disabling them for just a single offlined CPU is bad, since it will
1976 * inhibit reporting for all shared resources on the socket like the
1977 * last level cache (LLC), the integrated memory controller (iMC), etc.
1979 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
||
1980 boot_cpu_data
.x86_vendor
== X86_VENDOR_HYGON
||
1981 boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1984 mce_disable_error_reporting();
1987 static int mce_syscore_suspend(void)
1989 vendor_disable_error_reporting();
1993 static void mce_syscore_shutdown(void)
1995 vendor_disable_error_reporting();
1999 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2000 * Only one CPU is active at this time, the others get re-added later using
2003 static void mce_syscore_resume(void)
2005 __mcheck_cpu_init_generic();
2006 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info
));
2007 __mcheck_cpu_init_clear_banks();
2010 static struct syscore_ops mce_syscore_ops
= {
2011 .suspend
= mce_syscore_suspend
,
2012 .shutdown
= mce_syscore_shutdown
,
2013 .resume
= mce_syscore_resume
,
2017 * mce_device: Sysfs support
2020 static void mce_cpu_restart(void *data
)
2022 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2024 __mcheck_cpu_init_generic();
2025 __mcheck_cpu_init_clear_banks();
2026 __mcheck_cpu_init_timer();
2029 /* Reinit MCEs after user configuration changes */
2030 static void mce_restart(void)
2032 mce_timer_delete_all();
2033 on_each_cpu(mce_cpu_restart
, NULL
, 1);
2036 /* Toggle features for corrected errors */
2037 static void mce_disable_cmci(void *data
)
2039 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2044 static void mce_enable_ce(void *all
)
2046 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2051 __mcheck_cpu_init_timer();
2054 static struct bus_type mce_subsys
= {
2055 .name
= "machinecheck",
2056 .dev_name
= "machinecheck",
2059 DEFINE_PER_CPU(struct device
*, mce_device
);
2061 static inline struct mce_bank
*attr_to_bank(struct device_attribute
*attr
)
2063 return container_of(attr
, struct mce_bank
, attr
);
2066 static ssize_t
show_bank(struct device
*s
, struct device_attribute
*attr
,
2069 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
2072 static ssize_t
set_bank(struct device
*s
, struct device_attribute
*attr
,
2073 const char *buf
, size_t size
)
2077 if (kstrtou64(buf
, 0, &new) < 0)
2080 attr_to_bank(attr
)->ctl
= new;
2086 static ssize_t
set_ignore_ce(struct device
*s
,
2087 struct device_attribute
*attr
,
2088 const char *buf
, size_t size
)
2092 if (kstrtou64(buf
, 0, &new) < 0)
2095 mutex_lock(&mce_sysfs_mutex
);
2096 if (mca_cfg
.ignore_ce
^ !!new) {
2098 /* disable ce features */
2099 mce_timer_delete_all();
2100 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2101 mca_cfg
.ignore_ce
= true;
2103 /* enable ce features */
2104 mca_cfg
.ignore_ce
= false;
2105 on_each_cpu(mce_enable_ce
, (void *)1, 1);
2108 mutex_unlock(&mce_sysfs_mutex
);
2113 static ssize_t
set_cmci_disabled(struct device
*s
,
2114 struct device_attribute
*attr
,
2115 const char *buf
, size_t size
)
2119 if (kstrtou64(buf
, 0, &new) < 0)
2122 mutex_lock(&mce_sysfs_mutex
);
2123 if (mca_cfg
.cmci_disabled
^ !!new) {
2126 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2127 mca_cfg
.cmci_disabled
= true;
2130 mca_cfg
.cmci_disabled
= false;
2131 on_each_cpu(mce_enable_ce
, NULL
, 1);
2134 mutex_unlock(&mce_sysfs_mutex
);
2139 static ssize_t
store_int_with_restart(struct device
*s
,
2140 struct device_attribute
*attr
,
2141 const char *buf
, size_t size
)
2143 unsigned long old_check_interval
= check_interval
;
2144 ssize_t ret
= device_store_ulong(s
, attr
, buf
, size
);
2146 if (check_interval
== old_check_interval
)
2149 mutex_lock(&mce_sysfs_mutex
);
2151 mutex_unlock(&mce_sysfs_mutex
);
2156 static DEVICE_INT_ATTR(tolerant
, 0644, mca_cfg
.tolerant
);
2157 static DEVICE_INT_ATTR(monarch_timeout
, 0644, mca_cfg
.monarch_timeout
);
2158 static DEVICE_BOOL_ATTR(dont_log_ce
, 0644, mca_cfg
.dont_log_ce
);
2160 static struct dev_ext_attribute dev_attr_check_interval
= {
2161 __ATTR(check_interval
, 0644, device_show_int
, store_int_with_restart
),
2165 static struct dev_ext_attribute dev_attr_ignore_ce
= {
2166 __ATTR(ignore_ce
, 0644, device_show_bool
, set_ignore_ce
),
2170 static struct dev_ext_attribute dev_attr_cmci_disabled
= {
2171 __ATTR(cmci_disabled
, 0644, device_show_bool
, set_cmci_disabled
),
2172 &mca_cfg
.cmci_disabled
2175 static struct device_attribute
*mce_device_attrs
[] = {
2176 &dev_attr_tolerant
.attr
,
2177 &dev_attr_check_interval
.attr
,
2178 #ifdef CONFIG_X86_MCELOG_LEGACY
2181 &dev_attr_monarch_timeout
.attr
,
2182 &dev_attr_dont_log_ce
.attr
,
2183 &dev_attr_ignore_ce
.attr
,
2184 &dev_attr_cmci_disabled
.attr
,
2188 static cpumask_var_t mce_device_initialized
;
2190 static void mce_device_release(struct device
*dev
)
2195 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2196 static int mce_device_create(unsigned int cpu
)
2202 if (!mce_available(&boot_cpu_data
))
2205 dev
= per_cpu(mce_device
, cpu
);
2209 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
2213 dev
->bus
= &mce_subsys
;
2214 dev
->release
= &mce_device_release
;
2216 err
= device_register(dev
);
2222 for (i
= 0; mce_device_attrs
[i
]; i
++) {
2223 err
= device_create_file(dev
, mce_device_attrs
[i
]);
2227 for (j
= 0; j
< mca_cfg
.banks
; j
++) {
2228 err
= device_create_file(dev
, &mce_banks
[j
].attr
);
2232 cpumask_set_cpu(cpu
, mce_device_initialized
);
2233 per_cpu(mce_device
, cpu
) = dev
;
2238 device_remove_file(dev
, &mce_banks
[j
].attr
);
2241 device_remove_file(dev
, mce_device_attrs
[i
]);
2243 device_unregister(dev
);
2248 static void mce_device_remove(unsigned int cpu
)
2250 struct device
*dev
= per_cpu(mce_device
, cpu
);
2253 if (!cpumask_test_cpu(cpu
, mce_device_initialized
))
2256 for (i
= 0; mce_device_attrs
[i
]; i
++)
2257 device_remove_file(dev
, mce_device_attrs
[i
]);
2259 for (i
= 0; i
< mca_cfg
.banks
; i
++)
2260 device_remove_file(dev
, &mce_banks
[i
].attr
);
2262 device_unregister(dev
);
2263 cpumask_clear_cpu(cpu
, mce_device_initialized
);
2264 per_cpu(mce_device
, cpu
) = NULL
;
2267 /* Make sure there are no machine checks on offlined CPUs. */
2268 static void mce_disable_cpu(void)
2270 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2273 if (!cpuhp_tasks_frozen
)
2276 vendor_disable_error_reporting();
2279 static void mce_reenable_cpu(void)
2283 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2286 if (!cpuhp_tasks_frozen
)
2288 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
2289 struct mce_bank
*b
= &mce_banks
[i
];
2292 wrmsrl(msr_ops
.ctl(i
), b
->ctl
);
2296 static int mce_cpu_dead(unsigned int cpu
)
2298 mce_intel_hcpu_update(cpu
);
2300 /* intentionally ignoring frozen here */
2301 if (!cpuhp_tasks_frozen
)
2306 static int mce_cpu_online(unsigned int cpu
)
2308 struct timer_list
*t
= this_cpu_ptr(&mce_timer
);
2311 mce_device_create(cpu
);
2313 ret
= mce_threshold_create_device(cpu
);
2315 mce_device_remove(cpu
);
2323 static int mce_cpu_pre_down(unsigned int cpu
)
2325 struct timer_list
*t
= this_cpu_ptr(&mce_timer
);
2329 mce_threshold_remove_device(cpu
);
2330 mce_device_remove(cpu
);
2334 static __init
void mce_init_banks(void)
2338 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
2339 struct mce_bank
*b
= &mce_banks
[i
];
2340 struct device_attribute
*a
= &b
->attr
;
2342 sysfs_attr_init(&a
->attr
);
2343 a
->attr
.name
= b
->attrname
;
2344 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2346 a
->attr
.mode
= 0644;
2347 a
->show
= show_bank
;
2348 a
->store
= set_bank
;
2352 static __init
int mcheck_init_device(void)
2357 * Check if we have a spare virtual bit. This will only become
2358 * a problem if/when we move beyond 5-level page tables.
2360 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT
>= 63);
2362 if (!mce_available(&boot_cpu_data
)) {
2367 if (!zalloc_cpumask_var(&mce_device_initialized
, GFP_KERNEL
)) {
2374 err
= subsys_system_register(&mce_subsys
, NULL
);
2378 err
= cpuhp_setup_state(CPUHP_X86_MCE_DEAD
, "x86/mce:dead", NULL
,
2383 err
= cpuhp_setup_state(CPUHP_AP_ONLINE_DYN
, "x86/mce:online",
2384 mce_cpu_online
, mce_cpu_pre_down
);
2386 goto err_out_online
;
2388 register_syscore_ops(&mce_syscore_ops
);
2393 cpuhp_remove_state(CPUHP_X86_MCE_DEAD
);
2396 free_cpumask_var(mce_device_initialized
);
2399 pr_err("Unable to init MCE device (rc: %d)\n", err
);
2403 device_initcall_sync(mcheck_init_device
);
2406 * Old style boot options parsing. Only for compatibility.
2408 static int __init
mcheck_disable(char *str
)
2410 mca_cfg
.disabled
= 1;
2413 __setup("nomce", mcheck_disable
);
2415 #ifdef CONFIG_DEBUG_FS
2416 struct dentry
*mce_get_debugfs_dir(void)
2418 static struct dentry
*dmce
;
2421 dmce
= debugfs_create_dir("mce", NULL
);
2426 static void mce_reset(void)
2429 atomic_set(&mce_fake_panicked
, 0);
2430 atomic_set(&mce_executing
, 0);
2431 atomic_set(&mce_callin
, 0);
2432 atomic_set(&global_nwo
, 0);
2435 static int fake_panic_get(void *data
, u64
*val
)
2441 static int fake_panic_set(void *data
, u64 val
)
2448 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2449 fake_panic_set
, "%llu\n");
2451 static int __init
mcheck_debugfs_init(void)
2453 struct dentry
*dmce
, *ffake_panic
;
2455 dmce
= mce_get_debugfs_dir();
2458 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2466 static int __init
mcheck_debugfs_init(void) { return -EINVAL
; }
2469 DEFINE_STATIC_KEY_FALSE(mcsafe_key
);
2470 EXPORT_SYMBOL_GPL(mcsafe_key
);
2472 static int __init
mcheck_late_init(void)
2474 pr_info("Using %d MCE banks\n", mca_cfg
.banks
);
2476 if (mca_cfg
.recovery
)
2477 static_branch_inc(&mcsafe_key
);
2479 mcheck_debugfs_init();
2483 * Flush out everything that has been logged during early boot, now that
2484 * everything has been initialized (workqueues, decoders, ...).
2486 mce_schedule_work();
2490 late_initcall(mcheck_late_init
);