2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
44 #include <linux/jump_label.h>
46 #include <asm/processor.h>
47 #include <asm/traps.h>
48 #include <asm/tlbflush.h>
52 #include "mce-internal.h"
54 static DEFINE_MUTEX(mce_chrdev_read_mutex
);
56 #define mce_log_get_idx_check(p) \
58 RCU_LOCKDEP_WARN(!rcu_read_lock_sched_held() && \
59 !lockdep_is_held(&mce_chrdev_read_mutex), \
60 "suspicious mce_log_get_idx_check() usage"); \
61 smp_load_acquire(&(p)); \
64 #define CREATE_TRACE_POINTS
65 #include <trace/events/mce.h>
67 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count
);
71 struct mce_bank
*mce_banks __read_mostly
;
72 struct mce_vendor_flags mce_flags __read_mostly
;
74 struct mca_config mca_cfg __read_mostly
= {
78 * 0: always panic on uncorrected errors, log corrected errors
79 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
80 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
81 * 3: never panic or SIGBUS, log all errors (for testing only)
87 /* User mode helper program triggered by machine check event */
88 static unsigned long mce_need_notify
;
89 static char mce_helper
[128];
90 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
92 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait
);
94 static DEFINE_PER_CPU(struct mce
, mces_seen
);
95 static int cpu_missing
;
98 * MCA banks polled by the period polling timer for corrected events.
99 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
101 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
102 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
106 * MCA banks controlled through firmware first for corrected errors.
107 * This is a global list of banks for which we won't enable CMCI and we
108 * won't poll. Firmware controls these banks and is responsible for
109 * reporting corrected errors through GHES. Uncorrected/recoverable
110 * errors are still notified through a machine check.
112 mce_banks_t mce_banks_ce_disabled
;
114 static struct work_struct mce_work
;
115 static struct irq_work mce_irq_work
;
117 static void (*quirk_no_way_out
)(int bank
, struct mce
*m
, struct pt_regs
*regs
);
120 * CPU/chipset specific EDAC code can register a notifier call here to print
121 * MCE errors in a human-readable form.
123 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
125 /* Do initial initialization of a struct mce */
126 void mce_setup(struct mce
*m
)
128 memset(m
, 0, sizeof(struct mce
));
129 m
->cpu
= m
->extcpu
= smp_processor_id();
131 /* We hope get_seconds stays lockless */
132 m
->time
= get_seconds();
133 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
134 m
->cpuid
= cpuid_eax(1);
135 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
136 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
137 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
140 DEFINE_PER_CPU(struct mce
, injectm
);
141 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
144 * Lockless MCE logging infrastructure.
145 * This avoids deadlocks on printk locks without having to break locks. Also
146 * separate MCEs from kernel messages to avoid bogus bug reports.
149 static struct mce_log mcelog
= {
150 .signature
= MCE_LOG_SIGNATURE
,
152 .recordlen
= sizeof(struct mce
),
155 void mce_log(struct mce
*mce
)
157 unsigned next
, entry
;
159 /* Emit the trace record: */
160 trace_mce_record(mce
);
162 if (!mce_gen_pool_add(mce
))
163 irq_work_queue(&mce_irq_work
);
167 entry
= mce_log_get_idx_check(mcelog
.next
);
171 * When the buffer fills up discard new entries.
172 * Assume that the earlier errors are the more
175 if (entry
>= MCE_LOG_LEN
) {
176 set_bit(MCE_OVERFLOW
,
177 (unsigned long *)&mcelog
.flags
);
180 /* Old left over entry. Skip: */
181 if (mcelog
.entry
[entry
].finished
) {
189 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
192 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
194 mcelog
.entry
[entry
].finished
= 1;
197 set_bit(0, &mce_need_notify
);
200 void mce_inject_log(struct mce
*m
)
202 mutex_lock(&mce_chrdev_read_mutex
);
204 mutex_unlock(&mce_chrdev_read_mutex
);
206 EXPORT_SYMBOL_GPL(mce_inject_log
);
208 static struct notifier_block mce_srao_nb
;
210 void mce_register_decode_chain(struct notifier_block
*nb
)
212 /* Ensure SRAO notifier has the highest priority in the decode chain. */
213 if (nb
!= &mce_srao_nb
&& nb
->priority
== INT_MAX
)
216 atomic_notifier_chain_register(&x86_mce_decoder_chain
, nb
);
218 EXPORT_SYMBOL_GPL(mce_register_decode_chain
);
220 void mce_unregister_decode_chain(struct notifier_block
*nb
)
222 atomic_notifier_chain_unregister(&x86_mce_decoder_chain
, nb
);
224 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain
);
226 static inline u32
ctl_reg(int bank
)
228 return MSR_IA32_MCx_CTL(bank
);
231 static inline u32
status_reg(int bank
)
233 return MSR_IA32_MCx_STATUS(bank
);
236 static inline u32
addr_reg(int bank
)
238 return MSR_IA32_MCx_ADDR(bank
);
241 static inline u32
misc_reg(int bank
)
243 return MSR_IA32_MCx_MISC(bank
);
246 static inline u32
smca_ctl_reg(int bank
)
248 return MSR_AMD64_SMCA_MCx_CTL(bank
);
251 static inline u32
smca_status_reg(int bank
)
253 return MSR_AMD64_SMCA_MCx_STATUS(bank
);
256 static inline u32
smca_addr_reg(int bank
)
258 return MSR_AMD64_SMCA_MCx_ADDR(bank
);
261 static inline u32
smca_misc_reg(int bank
)
263 return MSR_AMD64_SMCA_MCx_MISC(bank
);
266 struct mca_msr_regs msr_ops
= {
268 .status
= status_reg
,
273 static void print_mce(struct mce
*m
)
277 pr_emerg(HW_ERR
"CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
278 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
281 pr_emerg(HW_ERR
"RIP%s %02x:<%016Lx> ",
282 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
285 if (m
->cs
== __KERNEL_CS
)
286 print_symbol("{%s}", m
->ip
);
290 pr_emerg(HW_ERR
"TSC %llx ", m
->tsc
);
292 pr_cont("ADDR %llx ", m
->addr
);
294 pr_cont("MISC %llx ", m
->misc
);
296 if (mce_flags
.smca
) {
298 pr_cont("SYND %llx ", m
->synd
);
300 pr_cont("IPID %llx ", m
->ipid
);
305 * Note this output is parsed by external tools and old fields
306 * should not be changed.
308 pr_emerg(HW_ERR
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
309 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
,
310 cpu_data(m
->extcpu
).microcode
);
313 * Print out human-readable details about the MCE error,
314 * (if the CPU has an implementation for that)
316 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
317 if (ret
== NOTIFY_STOP
)
320 pr_emerg_ratelimited(HW_ERR
"Run the above through 'mcelog --ascii'\n");
323 #define PANIC_TIMEOUT 5 /* 5 seconds */
325 static atomic_t mce_panicked
;
327 static int fake_panic
;
328 static atomic_t mce_fake_panicked
;
330 /* Panic in progress. Enable interrupts and wait for final IPI */
331 static void wait_for_panic(void)
333 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
337 while (timeout
-- > 0)
339 if (panic_timeout
== 0)
340 panic_timeout
= mca_cfg
.panic_timeout
;
341 panic("Panicing machine check CPU died");
344 static void mce_panic(const char *msg
, struct mce
*final
, char *exp
)
347 struct llist_node
*pending
;
348 struct mce_evt_llist
*l
;
352 * Make sure only one CPU runs in machine check panic
354 if (atomic_inc_return(&mce_panicked
) > 1)
361 /* Don't log too much for fake panic */
362 if (atomic_inc_return(&mce_fake_panicked
) > 1)
365 pending
= mce_gen_pool_prepare_records();
366 /* First print corrected ones that are still unlogged */
367 llist_for_each_entry(l
, pending
, llnode
) {
368 struct mce
*m
= &l
->mce
;
369 if (!(m
->status
& MCI_STATUS_UC
)) {
372 apei_err
= apei_write_mce(m
);
375 /* Now print uncorrected but with the final one last */
376 llist_for_each_entry(l
, pending
, llnode
) {
377 struct mce
*m
= &l
->mce
;
378 if (!(m
->status
& MCI_STATUS_UC
))
380 if (!final
|| mce_cmp(m
, final
)) {
383 apei_err
= apei_write_mce(m
);
389 apei_err
= apei_write_mce(final
);
392 pr_emerg(HW_ERR
"Some CPUs didn't answer in synchronization\n");
394 pr_emerg(HW_ERR
"Machine check: %s\n", exp
);
396 if (panic_timeout
== 0)
397 panic_timeout
= mca_cfg
.panic_timeout
;
400 pr_emerg(HW_ERR
"Fake kernel panic: %s\n", msg
);
403 /* Support code for software error injection */
405 static int msr_to_offset(u32 msr
)
407 unsigned bank
= __this_cpu_read(injectm
.bank
);
409 if (msr
== mca_cfg
.rip_msr
)
410 return offsetof(struct mce
, ip
);
411 if (msr
== msr_ops
.status(bank
))
412 return offsetof(struct mce
, status
);
413 if (msr
== msr_ops
.addr(bank
))
414 return offsetof(struct mce
, addr
);
415 if (msr
== msr_ops
.misc(bank
))
416 return offsetof(struct mce
, misc
);
417 if (msr
== MSR_IA32_MCG_STATUS
)
418 return offsetof(struct mce
, mcgstatus
);
422 /* MSR access wrappers used for error injection */
423 static u64
mce_rdmsrl(u32 msr
)
427 if (__this_cpu_read(injectm
.finished
)) {
428 int offset
= msr_to_offset(msr
);
432 return *(u64
*)((char *)this_cpu_ptr(&injectm
) + offset
);
435 if (rdmsrl_safe(msr
, &v
)) {
436 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr
);
438 * Return zero in case the access faulted. This should
439 * not happen normally but can happen if the CPU does
440 * something weird, or if the code is buggy.
448 static void mce_wrmsrl(u32 msr
, u64 v
)
450 if (__this_cpu_read(injectm
.finished
)) {
451 int offset
= msr_to_offset(msr
);
454 *(u64
*)((char *)this_cpu_ptr(&injectm
) + offset
) = v
;
461 * Collect all global (w.r.t. this processor) status about this machine
462 * check into our "mce" struct so that we can use it later to assess
463 * the severity of the problem as we read per-bank specific details.
465 static inline void mce_gather_info(struct mce
*m
, struct pt_regs
*regs
)
469 m
->mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
472 * Get the address of the instruction at the time of
473 * the machine check error.
475 if (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
)) {
480 * When in VM86 mode make the cs look like ring 3
481 * always. This is a lie, but it's better than passing
482 * the additional vm86 bit around everywhere.
484 if (v8086_mode(regs
))
487 /* Use accurate RIP reporting if available. */
489 m
->ip
= mce_rdmsrl(mca_cfg
.rip_msr
);
493 int mce_available(struct cpuinfo_x86
*c
)
495 if (mca_cfg
.disabled
)
497 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
500 static void mce_schedule_work(void)
502 if (!mce_gen_pool_empty() && keventd_up())
503 schedule_work(&mce_work
);
506 static void mce_irq_work_cb(struct irq_work
*entry
)
512 static void mce_report_event(struct pt_regs
*regs
)
514 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
517 * Triggering the work queue here is just an insurance
518 * policy in case the syscall exit notify handler
519 * doesn't run soon enough or ends up running on the
520 * wrong CPU (can happen when audit sleeps)
526 irq_work_queue(&mce_irq_work
);
530 * Check if the address reported by the CPU is in a format we can parse.
531 * It would be possible to add code for most other cases, but all would
532 * be somewhat complicated (e.g. segment offset would require an instruction
533 * parser). So only support physical addresses up to page granuality for now.
535 static int mce_usable_address(struct mce
*m
)
537 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
540 /* Checks after this one are Intel-specific: */
541 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
544 if (MCI_MISC_ADDR_LSB(m
->misc
) > PAGE_SHIFT
)
546 if (MCI_MISC_ADDR_MODE(m
->misc
) != MCI_MISC_ADDR_PHYS
)
551 static int srao_decode_notifier(struct notifier_block
*nb
, unsigned long val
,
554 struct mce
*mce
= (struct mce
*)data
;
560 if (mce_usable_address(mce
) && (mce
->severity
== MCE_AO_SEVERITY
)) {
561 pfn
= mce
->addr
>> PAGE_SHIFT
;
562 memory_failure(pfn
, MCE_VECTOR
, 0);
567 static struct notifier_block mce_srao_nb
= {
568 .notifier_call
= srao_decode_notifier
,
573 * Read ADDR and MISC registers.
575 static void mce_read_aux(struct mce
*m
, int i
)
577 if (m
->status
& MCI_STATUS_MISCV
)
578 m
->misc
= mce_rdmsrl(msr_ops
.misc(i
));
580 if (m
->status
& MCI_STATUS_ADDRV
) {
581 m
->addr
= mce_rdmsrl(msr_ops
.addr(i
));
584 * Mask the reported address by the reported granularity.
586 if (mca_cfg
.ser
&& (m
->status
& MCI_STATUS_MISCV
)) {
587 u8 shift
= MCI_MISC_ADDR_LSB(m
->misc
);
593 * Extract [55:<lsb>] where lsb is the least significant
594 * *valid* bit of the address bits.
596 if (mce_flags
.smca
) {
597 u8 lsb
= (m
->addr
>> 56) & 0x3f;
599 m
->addr
&= GENMASK_ULL(55, lsb
);
603 if (mce_flags
.smca
) {
604 m
->ipid
= mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i
));
606 if (m
->status
& MCI_STATUS_SYNDV
)
607 m
->synd
= mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i
));
611 static bool memory_error(struct mce
*m
)
613 struct cpuinfo_x86
*c
= &boot_cpu_data
;
615 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
616 /* ErrCodeExt[20:16] */
617 u8 xec
= (m
->status
>> 16) & 0x1f;
619 return (xec
== 0x0 || xec
== 0x8);
620 } else if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
622 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
624 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
625 * indicating a memory error. Bit 8 is used for indicating a
626 * cache hierarchy error. The combination of bit 2 and bit 3
627 * is used for indicating a `generic' cache hierarchy error
628 * But we can't just blindly check the above bits, because if
629 * bit 11 is set, then it is a bus/interconnect error - and
630 * either way the above bits just gives more detail on what
631 * bus/interconnect error happened. Note that bit 12 can be
632 * ignored, as it's the "filter" bit.
634 return (m
->status
& 0xef80) == BIT(7) ||
635 (m
->status
& 0xef00) == BIT(8) ||
636 (m
->status
& 0xeffc) == 0xc;
642 DEFINE_PER_CPU(unsigned, mce_poll_count
);
645 * Poll for corrected events or events that happened before reset.
646 * Those are just logged through /dev/mcelog.
648 * This is executed in standard interrupt context.
650 * Note: spec recommends to panic for fatal unsignalled
651 * errors here. However this would be quite problematic --
652 * we would need to reimplement the Monarch handling and
653 * it would mess up the exclusion between exception handler
654 * and poll hander -- * so we skip this for now.
655 * These cases should not happen anyways, or only when the CPU
656 * is already totally * confused. In this case it's likely it will
657 * not fully execute the machine check handler either.
659 bool machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
661 bool error_seen
= false;
666 this_cpu_inc(mce_poll_count
);
668 mce_gather_info(&m
, NULL
);
670 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
671 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
680 m
.status
= mce_rdmsrl(msr_ops
.status(i
));
681 if (!(m
.status
& MCI_STATUS_VAL
))
686 * Uncorrected or signalled events are handled by the exception
687 * handler when it is enabled, so don't process those here.
689 * TBD do the same check for MCI_STATUS_EN here?
691 if (!(flags
& MCP_UC
) &&
692 (m
.status
& (mca_cfg
.ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
699 if (!(flags
& MCP_TIMESTAMP
))
702 severity
= mce_severity(&m
, mca_cfg
.tolerant
, NULL
, false);
704 if (severity
== MCE_DEFERRED_SEVERITY
&& memory_error(&m
))
705 if (m
.status
& MCI_STATUS_ADDRV
)
706 m
.severity
= severity
;
709 * Don't get the IP here because it's unlikely to
710 * have anything to do with the actual error location.
712 if (!(flags
& MCP_DONTLOG
) && !mca_cfg
.dont_log_ce
)
714 else if (mce_usable_address(&m
)) {
716 * Although we skipped logging this, we still want
717 * to take action. Add to the pool so the registered
718 * notifiers will see it.
720 if (!mce_gen_pool_add(&m
))
725 * Clear state for this bank.
727 mce_wrmsrl(msr_ops
.status(i
), 0);
731 * Don't clear MCG_STATUS here because it's only defined for
739 EXPORT_SYMBOL_GPL(machine_check_poll
);
742 * Do a quick check if any of the events requires a panic.
743 * This decides if we keep the events around or clear them.
745 static int mce_no_way_out(struct mce
*m
, char **msg
, unsigned long *validp
,
746 struct pt_regs
*regs
)
751 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
752 m
->status
= mce_rdmsrl(msr_ops
.status(i
));
753 if (m
->status
& MCI_STATUS_VAL
) {
754 __set_bit(i
, validp
);
755 if (quirk_no_way_out
)
756 quirk_no_way_out(i
, m
, regs
);
759 if (mce_severity(m
, mca_cfg
.tolerant
, &tmp
, true) >= MCE_PANIC_SEVERITY
) {
768 * Variable to establish order between CPUs while scanning.
769 * Each CPU spins initially until executing is equal its number.
771 static atomic_t mce_executing
;
774 * Defines order of CPUs on entry. First CPU becomes Monarch.
776 static atomic_t mce_callin
;
779 * Check if a timeout waiting for other CPUs happened.
781 static int mce_timed_out(u64
*t
, const char *msg
)
784 * The others already did panic for some reason.
785 * Bail out like in a timeout.
786 * rmb() to tell the compiler that system_state
787 * might have been modified by someone else.
790 if (atomic_read(&mce_panicked
))
792 if (!mca_cfg
.monarch_timeout
)
794 if ((s64
)*t
< SPINUNIT
) {
795 if (mca_cfg
.tolerant
<= 1)
796 mce_panic(msg
, NULL
, NULL
);
802 touch_nmi_watchdog();
807 * The Monarch's reign. The Monarch is the CPU who entered
808 * the machine check handler first. It waits for the others to
809 * raise the exception too and then grades them. When any
810 * error is fatal panic. Only then let the others continue.
812 * The other CPUs entering the MCE handler will be controlled by the
813 * Monarch. They are called Subjects.
815 * This way we prevent any potential data corruption in a unrecoverable case
816 * and also makes sure always all CPU's errors are examined.
818 * Also this detects the case of a machine check event coming from outer
819 * space (not detected by any CPUs) In this case some external agent wants
820 * us to shut down, so panic too.
822 * The other CPUs might still decide to panic if the handler happens
823 * in a unrecoverable place, but in this case the system is in a semi-stable
824 * state and won't corrupt anything by itself. It's ok to let the others
825 * continue for a bit first.
827 * All the spin loops have timeouts; when a timeout happens a CPU
828 * typically elects itself to be Monarch.
830 static void mce_reign(void)
833 struct mce
*m
= NULL
;
834 int global_worst
= 0;
839 * This CPU is the Monarch and the other CPUs have run
840 * through their handlers.
841 * Grade the severity of the errors of all the CPUs.
843 for_each_possible_cpu(cpu
) {
844 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
),
847 if (severity
> global_worst
) {
849 global_worst
= severity
;
850 m
= &per_cpu(mces_seen
, cpu
);
855 * Cannot recover? Panic here then.
856 * This dumps all the mces in the log buffer and stops the
859 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& mca_cfg
.tolerant
< 3)
860 mce_panic("Fatal machine check", m
, msg
);
863 * For UC somewhere we let the CPU who detects it handle it.
864 * Also must let continue the others, otherwise the handling
865 * CPU could deadlock on a lock.
869 * No machine check event found. Must be some external
870 * source or one CPU is hung. Panic.
872 if (global_worst
<= MCE_KEEP_SEVERITY
&& mca_cfg
.tolerant
< 3)
873 mce_panic("Fatal machine check from unknown source", NULL
, NULL
);
876 * Now clear all the mces_seen so that they don't reappear on
879 for_each_possible_cpu(cpu
)
880 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
883 static atomic_t global_nwo
;
886 * Start of Monarch synchronization. This waits until all CPUs have
887 * entered the exception handler and then determines if any of them
888 * saw a fatal event that requires panic. Then it executes them
889 * in the entry order.
890 * TBD double check parallel CPU hotunplug
892 static int mce_start(int *no_way_out
)
895 int cpus
= num_online_cpus();
896 u64 timeout
= (u64
)mca_cfg
.monarch_timeout
* NSEC_PER_USEC
;
901 atomic_add(*no_way_out
, &global_nwo
);
903 * Rely on the implied barrier below, such that global_nwo
904 * is updated before mce_callin.
906 order
= atomic_inc_return(&mce_callin
);
911 while (atomic_read(&mce_callin
) != cpus
) {
912 if (mce_timed_out(&timeout
,
913 "Timeout: Not all CPUs entered broadcast exception handler")) {
914 atomic_set(&global_nwo
, 0);
921 * mce_callin should be read before global_nwo
927 * Monarch: Starts executing now, the others wait.
929 atomic_set(&mce_executing
, 1);
932 * Subject: Now start the scanning loop one by one in
933 * the original callin order.
934 * This way when there are any shared banks it will be
935 * only seen by one CPU before cleared, avoiding duplicates.
937 while (atomic_read(&mce_executing
) < order
) {
938 if (mce_timed_out(&timeout
,
939 "Timeout: Subject CPUs unable to finish machine check processing")) {
940 atomic_set(&global_nwo
, 0);
948 * Cache the global no_way_out state.
950 *no_way_out
= atomic_read(&global_nwo
);
956 * Synchronize between CPUs after main scanning loop.
957 * This invokes the bulk of the Monarch processing.
959 static int mce_end(int order
)
962 u64 timeout
= (u64
)mca_cfg
.monarch_timeout
* NSEC_PER_USEC
;
970 * Allow others to run.
972 atomic_inc(&mce_executing
);
975 /* CHECKME: Can this race with a parallel hotplug? */
976 int cpus
= num_online_cpus();
979 * Monarch: Wait for everyone to go through their scanning
982 while (atomic_read(&mce_executing
) <= cpus
) {
983 if (mce_timed_out(&timeout
,
984 "Timeout: Monarch CPU unable to finish machine check processing"))
994 * Subject: Wait for Monarch to finish.
996 while (atomic_read(&mce_executing
) != 0) {
997 if (mce_timed_out(&timeout
,
998 "Timeout: Monarch CPU did not finish machine check processing"))
1004 * Don't reset anything. That's done by the Monarch.
1010 * Reset all global state.
1013 atomic_set(&global_nwo
, 0);
1014 atomic_set(&mce_callin
, 0);
1018 * Let others run again.
1020 atomic_set(&mce_executing
, 0);
1024 static void mce_clear_state(unsigned long *toclear
)
1028 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
1029 if (test_bit(i
, toclear
))
1030 mce_wrmsrl(msr_ops
.status(i
), 0);
1034 static int do_memory_failure(struct mce
*m
)
1036 int flags
= MF_ACTION_REQUIRED
;
1039 pr_err("Uncorrected hardware memory error in user-access at %llx", m
->addr
);
1040 if (!(m
->mcgstatus
& MCG_STATUS_RIPV
))
1041 flags
|= MF_MUST_KILL
;
1042 ret
= memory_failure(m
->addr
>> PAGE_SHIFT
, MCE_VECTOR
, flags
);
1044 pr_err("Memory error not recovered");
1049 * The actual machine check handler. This only handles real
1050 * exceptions when something got corrupted coming in through int 18.
1052 * This is executed in NMI context not subject to normal locking rules. This
1053 * implies that most kernel services cannot be safely used. Don't even
1054 * think about putting a printk in there!
1056 * On Intel systems this is entered on all CPUs in parallel through
1057 * MCE broadcast. However some CPUs might be broken beyond repair,
1058 * so be always careful when synchronizing with others.
1060 void do_machine_check(struct pt_regs
*regs
, long error_code
)
1062 struct mca_config
*cfg
= &mca_cfg
;
1063 struct mce m
, *final
;
1069 * Establish sequential order between the CPUs entering the machine
1074 * If no_way_out gets set, there is no safe way to recover from this
1075 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1079 * If kill_it gets set, there might be a way to recover from this
1083 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
1084 DECLARE_BITMAP(valid_banks
, MAX_NR_BANKS
);
1085 char *msg
= "Unknown";
1088 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1093 /* If this CPU is offline, just bail out. */
1094 if (cpu_is_offline(smp_processor_id())) {
1097 mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
1098 if (mcgstatus
& MCG_STATUS_RIPV
) {
1099 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1106 this_cpu_inc(mce_exception_count
);
1111 mce_gather_info(&m
, regs
);
1113 final
= this_cpu_ptr(&mces_seen
);
1116 memset(valid_banks
, 0, sizeof(valid_banks
));
1117 no_way_out
= mce_no_way_out(&m
, &msg
, valid_banks
, regs
);
1122 * When no restart IP might need to kill or panic.
1123 * Assume the worst for now, but if we find the
1124 * severity is MCE_AR_SEVERITY we have other options.
1126 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
1130 * Check if this MCE is signaled to only this logical processor,
1133 if (m
.cpuvendor
== X86_VENDOR_INTEL
)
1134 lmce
= m
.mcgstatus
& MCG_STATUS_LMCES
;
1137 * Go through all banks in exclusion of the other CPUs. This way we
1138 * don't report duplicated events on shared banks because the first one
1139 * to see it will clear it. If this is a Local MCE, then no need to
1140 * perform rendezvous.
1143 order
= mce_start(&no_way_out
);
1145 for (i
= 0; i
< cfg
->banks
; i
++) {
1146 __clear_bit(i
, toclear
);
1147 if (!test_bit(i
, valid_banks
))
1149 if (!mce_banks
[i
].ctl
)
1156 m
.status
= mce_rdmsrl(msr_ops
.status(i
));
1157 if ((m
.status
& MCI_STATUS_VAL
) == 0)
1161 * Non uncorrected or non signaled errors are handled by
1162 * machine_check_poll. Leave them alone, unless this panics.
1164 if (!(m
.status
& (cfg
->ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
1169 * Set taint even when machine check was not enabled.
1171 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
1173 severity
= mce_severity(&m
, cfg
->tolerant
, NULL
, true);
1176 * When machine check was for corrected/deferred handler don't
1177 * touch, unless we're panicing.
1179 if ((severity
== MCE_KEEP_SEVERITY
||
1180 severity
== MCE_UCNA_SEVERITY
) && !no_way_out
)
1182 __set_bit(i
, toclear
);
1183 if (severity
== MCE_NO_SEVERITY
) {
1185 * Machine check event was not enabled. Clear, but
1191 mce_read_aux(&m
, i
);
1193 /* assuming valid severity level != 0 */
1194 m
.severity
= severity
;
1198 if (severity
> worst
) {
1204 /* mce_clear_state will clear *final, save locally for use later */
1208 mce_clear_state(toclear
);
1211 * Do most of the synchronization with other CPUs.
1212 * When there's any problem use only local no_way_out state.
1215 if (mce_end(order
) < 0)
1216 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1219 * Local MCE skipped calling mce_reign()
1220 * If we found a fatal error, we need to panic here.
1222 if (worst
>= MCE_PANIC_SEVERITY
&& mca_cfg
.tolerant
< 3)
1223 mce_panic("Machine check from unknown source",
1228 * If tolerant is at an insane level we drop requests to kill
1229 * processes and continue even when there is no way out.
1231 if (cfg
->tolerant
== 3)
1233 else if (no_way_out
)
1234 mce_panic("Fatal machine check on current CPU", &m
, msg
);
1237 mce_report_event(regs
);
1238 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1242 if (worst
!= MCE_AR_SEVERITY
&& !kill_it
)
1245 /* Fault was in user mode and we need to take some action */
1246 if ((m
.cs
& 3) == 3) {
1247 ist_begin_non_atomic(regs
);
1250 if (kill_it
|| do_memory_failure(&m
))
1251 force_sig(SIGBUS
, current
);
1252 local_irq_disable();
1253 ist_end_non_atomic();
1255 if (!fixup_exception(regs
, X86_TRAP_MC
))
1256 mce_panic("Failed kernel mode recovery", &m
, NULL
);
1262 EXPORT_SYMBOL_GPL(do_machine_check
);
1264 #ifndef CONFIG_MEMORY_FAILURE
1265 int memory_failure(unsigned long pfn
, int vector
, int flags
)
1267 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1268 BUG_ON(flags
& MF_ACTION_REQUIRED
);
1269 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1270 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1278 * Action optional processing happens here (picking up
1279 * from the list of faulting pages that do_machine_check()
1280 * placed into the genpool).
1282 static void mce_process_work(struct work_struct
*dummy
)
1284 mce_gen_pool_process();
1287 #ifdef CONFIG_X86_MCE_INTEL
1289 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1290 * @cpu: The CPU on which the event occurred.
1291 * @status: Event status information
1293 * This function should be called by the thermal interrupt after the
1294 * event has been processed and the decision was made to log the event
1297 * The status parameter will be saved to the 'status' field of 'struct mce'
1298 * and historically has been the register value of the
1299 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1301 void mce_log_therm_throt_event(__u64 status
)
1306 m
.bank
= MCE_THERMAL_BANK
;
1310 #endif /* CONFIG_X86_MCE_INTEL */
1313 * Periodic polling timer for "silent" machine check errors. If the
1314 * poller finds an MCE, poll 2x faster. When the poller finds no more
1315 * errors, poll 2x slower (up to check_interval seconds).
1317 static unsigned long check_interval
= INITIAL_CHECK_INTERVAL
;
1319 static DEFINE_PER_CPU(unsigned long, mce_next_interval
); /* in jiffies */
1320 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1322 static unsigned long mce_adjust_timer_default(unsigned long interval
)
1327 static unsigned long (*mce_adjust_timer
)(unsigned long interval
) = mce_adjust_timer_default
;
1329 static void __restart_timer(struct timer_list
*t
, unsigned long interval
)
1331 unsigned long when
= jiffies
+ interval
;
1332 unsigned long flags
;
1334 local_irq_save(flags
);
1336 if (timer_pending(t
)) {
1337 if (time_before(when
, t
->expires
))
1340 t
->expires
= round_jiffies(when
);
1341 add_timer_on(t
, smp_processor_id());
1344 local_irq_restore(flags
);
1347 static void mce_timer_fn(unsigned long data
)
1349 struct timer_list
*t
= this_cpu_ptr(&mce_timer
);
1350 int cpu
= smp_processor_id();
1353 WARN_ON(cpu
!= data
);
1355 iv
= __this_cpu_read(mce_next_interval
);
1357 if (mce_available(this_cpu_ptr(&cpu_info
))) {
1358 machine_check_poll(MCP_TIMESTAMP
, this_cpu_ptr(&mce_poll_banks
));
1360 if (mce_intel_cmci_poll()) {
1361 iv
= mce_adjust_timer(iv
);
1367 * Alert userspace if needed. If we logged an MCE, reduce the polling
1368 * interval, otherwise increase the polling interval.
1370 if (mce_notify_irq())
1371 iv
= max(iv
/ 2, (unsigned long) HZ
/100);
1373 iv
= min(iv
* 2, round_jiffies_relative(check_interval
* HZ
));
1376 __this_cpu_write(mce_next_interval
, iv
);
1377 __restart_timer(t
, iv
);
1381 * Ensure that the timer is firing in @interval from now.
1383 void mce_timer_kick(unsigned long interval
)
1385 struct timer_list
*t
= this_cpu_ptr(&mce_timer
);
1386 unsigned long iv
= __this_cpu_read(mce_next_interval
);
1388 __restart_timer(t
, interval
);
1391 __this_cpu_write(mce_next_interval
, interval
);
1394 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1395 static void mce_timer_delete_all(void)
1399 for_each_online_cpu(cpu
)
1400 del_timer_sync(&per_cpu(mce_timer
, cpu
));
1403 static void mce_do_trigger(struct work_struct
*work
)
1405 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1408 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1411 * Notify the user(s) about new machine check events.
1412 * Can be called from interrupt context, but not from machine check/NMI
1415 int mce_notify_irq(void)
1417 /* Not more than two messages every minute */
1418 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1420 if (test_and_clear_bit(0, &mce_need_notify
)) {
1421 /* wake processes polling /dev/mcelog */
1422 wake_up_interruptible(&mce_chrdev_wait
);
1425 schedule_work(&mce_trigger_work
);
1427 if (__ratelimit(&ratelimit
))
1428 pr_info(HW_ERR
"Machine check events logged\n");
1434 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1436 static int __mcheck_cpu_mce_banks_init(void)
1439 u8 num_banks
= mca_cfg
.banks
;
1441 mce_banks
= kzalloc(num_banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1445 for (i
= 0; i
< num_banks
; i
++) {
1446 struct mce_bank
*b
= &mce_banks
[i
];
1455 * Initialize Machine Checks for a CPU.
1457 static int __mcheck_cpu_cap_init(void)
1462 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1464 b
= cap
& MCG_BANKCNT_MASK
;
1466 pr_info("CPU supports %d MCE banks\n", b
);
1468 if (b
> MAX_NR_BANKS
) {
1469 pr_warn("Using only %u machine check banks out of %u\n",
1474 /* Don't support asymmetric configurations today */
1475 WARN_ON(mca_cfg
.banks
!= 0 && b
!= mca_cfg
.banks
);
1479 int err
= __mcheck_cpu_mce_banks_init();
1485 /* Use accurate RIP reporting if available. */
1486 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1487 mca_cfg
.rip_msr
= MSR_IA32_MCG_EIP
;
1489 if (cap
& MCG_SER_P
)
1495 static void __mcheck_cpu_init_generic(void)
1497 enum mcp_flags m_fl
= 0;
1498 mce_banks_t all_banks
;
1501 if (!mca_cfg
.bootlog
)
1505 * Log the machine checks left over from the previous reset.
1507 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1508 machine_check_poll(MCP_UC
| m_fl
, &all_banks
);
1510 cr4_set_bits(X86_CR4_MCE
);
1512 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1513 if (cap
& MCG_CTL_P
)
1514 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1517 static void __mcheck_cpu_init_clear_banks(void)
1521 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
1522 struct mce_bank
*b
= &mce_banks
[i
];
1526 wrmsrl(msr_ops
.ctl(i
), b
->ctl
);
1527 wrmsrl(msr_ops
.status(i
), 0);
1532 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1533 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1534 * Vol 3B Table 15-20). But this confuses both the code that determines
1535 * whether the machine check occurred in kernel or user mode, and also
1536 * the severity assessment code. Pretend that EIPV was set, and take the
1537 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1539 static void quirk_sandybridge_ifu(int bank
, struct mce
*m
, struct pt_regs
*regs
)
1543 if ((m
->mcgstatus
& (MCG_STATUS_EIPV
|MCG_STATUS_RIPV
)) != 0)
1545 if ((m
->status
& (MCI_STATUS_OVER
|MCI_STATUS_UC
|
1546 MCI_STATUS_EN
|MCI_STATUS_MISCV
|MCI_STATUS_ADDRV
|
1547 MCI_STATUS_PCC
|MCI_STATUS_S
|MCI_STATUS_AR
|
1549 (MCI_STATUS_UC
|MCI_STATUS_EN
|
1550 MCI_STATUS_MISCV
|MCI_STATUS_ADDRV
|MCI_STATUS_S
|
1551 MCI_STATUS_AR
|MCACOD_INSTR
))
1554 m
->mcgstatus
|= MCG_STATUS_EIPV
;
1559 /* Add per CPU specific workarounds here */
1560 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1562 struct mca_config
*cfg
= &mca_cfg
;
1564 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1565 pr_info("unknown CPU type - not enabling MCE support\n");
1569 /* This should be disabled by the BIOS, but isn't always */
1570 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1571 if (c
->x86
== 15 && cfg
->banks
> 4) {
1573 * disable GART TBL walk error reporting, which
1574 * trips off incorrectly with the IOMMU & 3ware
1577 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1579 if (c
->x86
< 17 && cfg
->bootlog
< 0) {
1581 * Lots of broken BIOS around that don't clear them
1582 * by default and leave crap in there. Don't log:
1587 * Various K7s with broken bank 0 around. Always disable
1590 if (c
->x86
== 6 && cfg
->banks
> 0)
1591 mce_banks
[0].ctl
= 0;
1594 * overflow_recov is supported for F15h Models 00h-0fh
1595 * even though we don't have a CPUID bit for it.
1597 if (c
->x86
== 0x15 && c
->x86_model
<= 0xf)
1598 mce_flags
.overflow_recov
= 1;
1601 * Turn off MC4_MISC thresholding banks on those models since
1602 * they're not supported there.
1604 if (c
->x86
== 0x15 &&
1605 (c
->x86_model
>= 0x10 && c
->x86_model
<= 0x1f)) {
1610 0x00000413, /* MC4_MISC0 */
1611 0xc0000408, /* MC4_MISC1 */
1614 rdmsrl(MSR_K7_HWCR
, hwcr
);
1616 /* McStatusWrEn has to be set */
1617 need_toggle
= !(hwcr
& BIT(18));
1620 wrmsrl(MSR_K7_HWCR
, hwcr
| BIT(18));
1622 /* Clear CntP bit safely */
1623 for (i
= 0; i
< ARRAY_SIZE(msrs
); i
++)
1624 msr_clear_bit(msrs
[i
], 62);
1626 /* restore old settings */
1628 wrmsrl(MSR_K7_HWCR
, hwcr
);
1632 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1634 * SDM documents that on family 6 bank 0 should not be written
1635 * because it aliases to another special BIOS controlled
1637 * But it's not aliased anymore on model 0x1a+
1638 * Don't ignore bank 0 completely because there could be a
1639 * valid event later, merely don't write CTL0.
1642 if (c
->x86
== 6 && c
->x86_model
< 0x1A && cfg
->banks
> 0)
1643 mce_banks
[0].init
= 0;
1646 * All newer Intel systems support MCE broadcasting. Enable
1647 * synchronization with a one second timeout.
1649 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1650 cfg
->monarch_timeout
< 0)
1651 cfg
->monarch_timeout
= USEC_PER_SEC
;
1654 * There are also broken BIOSes on some Pentium M and
1657 if (c
->x86
== 6 && c
->x86_model
<= 13 && cfg
->bootlog
< 0)
1660 if (c
->x86
== 6 && c
->x86_model
== 45)
1661 quirk_no_way_out
= quirk_sandybridge_ifu
;
1663 if (cfg
->monarch_timeout
< 0)
1664 cfg
->monarch_timeout
= 0;
1665 if (cfg
->bootlog
!= 0)
1666 cfg
->panic_timeout
= 30;
1671 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1676 switch (c
->x86_vendor
) {
1677 case X86_VENDOR_INTEL
:
1678 intel_p5_mcheck_init(c
);
1681 case X86_VENDOR_CENTAUR
:
1682 winchip_mcheck_init(c
);
1692 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1694 switch (c
->x86_vendor
) {
1695 case X86_VENDOR_INTEL
:
1696 mce_intel_feature_init(c
);
1697 mce_adjust_timer
= cmci_intel_adjust_timer
;
1700 case X86_VENDOR_AMD
: {
1701 mce_flags
.overflow_recov
= !!cpu_has(c
, X86_FEATURE_OVERFLOW_RECOV
);
1702 mce_flags
.succor
= !!cpu_has(c
, X86_FEATURE_SUCCOR
);
1703 mce_flags
.smca
= !!cpu_has(c
, X86_FEATURE_SMCA
);
1706 * Install proper ops for Scalable MCA enabled processors
1708 if (mce_flags
.smca
) {
1709 msr_ops
.ctl
= smca_ctl_reg
;
1710 msr_ops
.status
= smca_status_reg
;
1711 msr_ops
.addr
= smca_addr_reg
;
1712 msr_ops
.misc
= smca_misc_reg
;
1714 mce_amd_feature_init(c
);
1724 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86
*c
)
1726 switch (c
->x86_vendor
) {
1727 case X86_VENDOR_INTEL
:
1728 mce_intel_feature_clear(c
);
1735 static void mce_start_timer(unsigned int cpu
, struct timer_list
*t
)
1737 unsigned long iv
= check_interval
* HZ
;
1739 if (mca_cfg
.ignore_ce
|| !iv
)
1742 per_cpu(mce_next_interval
, cpu
) = iv
;
1744 t
->expires
= round_jiffies(jiffies
+ iv
);
1745 add_timer_on(t
, cpu
);
1748 static void __mcheck_cpu_init_timer(void)
1750 struct timer_list
*t
= this_cpu_ptr(&mce_timer
);
1751 unsigned int cpu
= smp_processor_id();
1753 setup_pinned_timer(t
, mce_timer_fn
, cpu
);
1754 mce_start_timer(cpu
, t
);
1757 /* Handle unconfigured int18 (should never happen) */
1758 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1760 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1761 smp_processor_id());
1764 /* Call the installed machine check handler for this CPU setup. */
1765 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1766 unexpected_machine_check
;
1769 * Called for each booted CPU to set up machine checks.
1770 * Must be called with preempt off:
1772 void mcheck_cpu_init(struct cpuinfo_x86
*c
)
1774 if (mca_cfg
.disabled
)
1777 if (__mcheck_cpu_ancient_init(c
))
1780 if (!mce_available(c
))
1783 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1784 mca_cfg
.disabled
= true;
1788 if (mce_gen_pool_init()) {
1789 mca_cfg
.disabled
= true;
1790 pr_emerg("Couldn't allocate MCE records pool!\n");
1794 machine_check_vector
= do_machine_check
;
1796 __mcheck_cpu_init_generic();
1797 __mcheck_cpu_init_vendor(c
);
1798 __mcheck_cpu_init_clear_banks();
1799 __mcheck_cpu_init_timer();
1803 * Called for each booted CPU to clear some machine checks opt-ins
1805 void mcheck_cpu_clear(struct cpuinfo_x86
*c
)
1807 if (mca_cfg
.disabled
)
1810 if (!mce_available(c
))
1814 * Possibly to clear general settings generic to x86
1815 * __mcheck_cpu_clear_generic(c);
1817 __mcheck_cpu_clear_vendor(c
);
1822 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1825 static DEFINE_SPINLOCK(mce_chrdev_state_lock
);
1826 static int mce_chrdev_open_count
; /* #times opened */
1827 static int mce_chrdev_open_exclu
; /* already open exclusive? */
1829 static int mce_chrdev_open(struct inode
*inode
, struct file
*file
)
1831 spin_lock(&mce_chrdev_state_lock
);
1833 if (mce_chrdev_open_exclu
||
1834 (mce_chrdev_open_count
&& (file
->f_flags
& O_EXCL
))) {
1835 spin_unlock(&mce_chrdev_state_lock
);
1840 if (file
->f_flags
& O_EXCL
)
1841 mce_chrdev_open_exclu
= 1;
1842 mce_chrdev_open_count
++;
1844 spin_unlock(&mce_chrdev_state_lock
);
1846 return nonseekable_open(inode
, file
);
1849 static int mce_chrdev_release(struct inode
*inode
, struct file
*file
)
1851 spin_lock(&mce_chrdev_state_lock
);
1853 mce_chrdev_open_count
--;
1854 mce_chrdev_open_exclu
= 0;
1856 spin_unlock(&mce_chrdev_state_lock
);
1861 static void collect_tscs(void *data
)
1863 unsigned long *cpu_tsc
= (unsigned long *)data
;
1865 cpu_tsc
[smp_processor_id()] = rdtsc();
1868 static int mce_apei_read_done
;
1870 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1871 static int __mce_read_apei(char __user
**ubuf
, size_t usize
)
1877 if (usize
< sizeof(struct mce
))
1880 rc
= apei_read_mce(&m
, &record_id
);
1881 /* Error or no more MCE record */
1883 mce_apei_read_done
= 1;
1885 * When ERST is disabled, mce_chrdev_read() should return
1886 * "no record" instead of "no device."
1893 if (copy_to_user(*ubuf
, &m
, sizeof(struct mce
)))
1896 * In fact, we should have cleared the record after that has
1897 * been flushed to the disk or sent to network in
1898 * /sbin/mcelog, but we have no interface to support that now,
1899 * so just clear it to avoid duplication.
1901 rc
= apei_clear_mce(record_id
);
1903 mce_apei_read_done
= 1;
1906 *ubuf
+= sizeof(struct mce
);
1911 static ssize_t
mce_chrdev_read(struct file
*filp
, char __user
*ubuf
,
1912 size_t usize
, loff_t
*off
)
1914 char __user
*buf
= ubuf
;
1915 unsigned long *cpu_tsc
;
1916 unsigned prev
, next
;
1919 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1923 mutex_lock(&mce_chrdev_read_mutex
);
1925 if (!mce_apei_read_done
) {
1926 err
= __mce_read_apei(&buf
, usize
);
1927 if (err
|| buf
!= ubuf
)
1931 next
= mce_log_get_idx_check(mcelog
.next
);
1933 /* Only supports full reads right now */
1935 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
))
1941 for (i
= prev
; i
< next
; i
++) {
1942 unsigned long start
= jiffies
;
1943 struct mce
*m
= &mcelog
.entry
[i
];
1945 while (!m
->finished
) {
1946 if (time_after_eq(jiffies
, start
+ 2)) {
1947 memset(m
, 0, sizeof(*m
));
1953 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1959 memset(mcelog
.entry
+ prev
, 0,
1960 (next
- prev
) * sizeof(struct mce
));
1962 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1963 } while (next
!= prev
);
1965 synchronize_sched();
1968 * Collect entries that were still getting written before the
1971 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1973 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1974 struct mce
*m
= &mcelog
.entry
[i
];
1976 if (m
->finished
&& m
->tsc
< cpu_tsc
[m
->cpu
]) {
1977 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1980 memset(m
, 0, sizeof(*m
));
1988 mutex_unlock(&mce_chrdev_read_mutex
);
1991 return err
? err
: buf
- ubuf
;
1994 static unsigned int mce_chrdev_poll(struct file
*file
, poll_table
*wait
)
1996 poll_wait(file
, &mce_chrdev_wait
, wait
);
1997 if (READ_ONCE(mcelog
.next
))
1998 return POLLIN
| POLLRDNORM
;
1999 if (!mce_apei_read_done
&& apei_check_mce())
2000 return POLLIN
| POLLRDNORM
;
2004 static long mce_chrdev_ioctl(struct file
*f
, unsigned int cmd
,
2007 int __user
*p
= (int __user
*)arg
;
2009 if (!capable(CAP_SYS_ADMIN
))
2013 case MCE_GET_RECORD_LEN
:
2014 return put_user(sizeof(struct mce
), p
);
2015 case MCE_GET_LOG_LEN
:
2016 return put_user(MCE_LOG_LEN
, p
);
2017 case MCE_GETCLEAR_FLAGS
: {
2021 flags
= mcelog
.flags
;
2022 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
2024 return put_user(flags
, p
);
2031 static ssize_t (*mce_write
)(struct file
*filp
, const char __user
*ubuf
,
2032 size_t usize
, loff_t
*off
);
2034 void register_mce_write_callback(ssize_t (*fn
)(struct file
*filp
,
2035 const char __user
*ubuf
,
2036 size_t usize
, loff_t
*off
))
2040 EXPORT_SYMBOL_GPL(register_mce_write_callback
);
2042 static ssize_t
mce_chrdev_write(struct file
*filp
, const char __user
*ubuf
,
2043 size_t usize
, loff_t
*off
)
2046 return mce_write(filp
, ubuf
, usize
, off
);
2051 static const struct file_operations mce_chrdev_ops
= {
2052 .open
= mce_chrdev_open
,
2053 .release
= mce_chrdev_release
,
2054 .read
= mce_chrdev_read
,
2055 .write
= mce_chrdev_write
,
2056 .poll
= mce_chrdev_poll
,
2057 .unlocked_ioctl
= mce_chrdev_ioctl
,
2058 .llseek
= no_llseek
,
2061 static struct miscdevice mce_chrdev_device
= {
2067 static void __mce_disable_bank(void *arg
)
2069 int bank
= *((int *)arg
);
2070 __clear_bit(bank
, this_cpu_ptr(mce_poll_banks
));
2071 cmci_disable_bank(bank
);
2074 void mce_disable_bank(int bank
)
2076 if (bank
>= mca_cfg
.banks
) {
2078 "Ignoring request to disable invalid MCA bank %d.\n",
2082 set_bit(bank
, mce_banks_ce_disabled
);
2083 on_each_cpu(__mce_disable_bank
, &bank
, 1);
2087 * mce=off Disables machine check
2088 * mce=no_cmci Disables CMCI
2089 * mce=no_lmce Disables LMCE
2090 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2091 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2092 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2093 * monarchtimeout is how long to wait for other CPUs on machine
2094 * check, or 0 to not wait
2095 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
2096 * mce=nobootlog Don't log MCEs from before booting.
2097 * mce=bios_cmci_threshold Don't program the CMCI threshold
2098 * mce=recovery force enable memcpy_mcsafe()
2100 static int __init
mcheck_enable(char *str
)
2102 struct mca_config
*cfg
= &mca_cfg
;
2110 if (!strcmp(str
, "off"))
2111 cfg
->disabled
= true;
2112 else if (!strcmp(str
, "no_cmci"))
2113 cfg
->cmci_disabled
= true;
2114 else if (!strcmp(str
, "no_lmce"))
2115 cfg
->lmce_disabled
= true;
2116 else if (!strcmp(str
, "dont_log_ce"))
2117 cfg
->dont_log_ce
= true;
2118 else if (!strcmp(str
, "ignore_ce"))
2119 cfg
->ignore_ce
= true;
2120 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
2121 cfg
->bootlog
= (str
[0] == 'b');
2122 else if (!strcmp(str
, "bios_cmci_threshold"))
2123 cfg
->bios_cmci_threshold
= true;
2124 else if (!strcmp(str
, "recovery"))
2125 cfg
->recovery
= true;
2126 else if (isdigit(str
[0])) {
2127 if (get_option(&str
, &cfg
->tolerant
) == 2)
2128 get_option(&str
, &(cfg
->monarch_timeout
));
2130 pr_info("mce argument %s ignored. Please use /sys\n", str
);
2135 __setup("mce", mcheck_enable
);
2137 int __init
mcheck_init(void)
2139 mcheck_intel_therm_init();
2140 mce_register_decode_chain(&mce_srao_nb
);
2141 mcheck_vendor_init_severity();
2143 INIT_WORK(&mce_work
, mce_process_work
);
2144 init_irq_work(&mce_irq_work
, mce_irq_work_cb
);
2150 * mce_syscore: PM support
2154 * Disable machine checks on suspend and shutdown. We can't really handle
2157 static void mce_disable_error_reporting(void)
2161 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
2162 struct mce_bank
*b
= &mce_banks
[i
];
2165 wrmsrl(msr_ops
.ctl(i
), 0);
2170 static void vendor_disable_error_reporting(void)
2173 * Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
2174 * Disabling them for just a single offlined CPU is bad, since it will
2175 * inhibit reporting for all shared resources on the socket like the
2176 * last level cache (LLC), the integrated memory controller (iMC), etc.
2178 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2181 mce_disable_error_reporting();
2184 static int mce_syscore_suspend(void)
2186 vendor_disable_error_reporting();
2190 static void mce_syscore_shutdown(void)
2192 vendor_disable_error_reporting();
2196 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2197 * Only one CPU is active at this time, the others get re-added later using
2200 static void mce_syscore_resume(void)
2202 __mcheck_cpu_init_generic();
2203 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info
));
2204 __mcheck_cpu_init_clear_banks();
2207 static struct syscore_ops mce_syscore_ops
= {
2208 .suspend
= mce_syscore_suspend
,
2209 .shutdown
= mce_syscore_shutdown
,
2210 .resume
= mce_syscore_resume
,
2214 * mce_device: Sysfs support
2217 static void mce_cpu_restart(void *data
)
2219 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2221 __mcheck_cpu_init_generic();
2222 __mcheck_cpu_init_clear_banks();
2223 __mcheck_cpu_init_timer();
2226 /* Reinit MCEs after user configuration changes */
2227 static void mce_restart(void)
2229 mce_timer_delete_all();
2230 on_each_cpu(mce_cpu_restart
, NULL
, 1);
2233 /* Toggle features for corrected errors */
2234 static void mce_disable_cmci(void *data
)
2236 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2241 static void mce_enable_ce(void *all
)
2243 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2248 __mcheck_cpu_init_timer();
2251 static struct bus_type mce_subsys
= {
2252 .name
= "machinecheck",
2253 .dev_name
= "machinecheck",
2256 DEFINE_PER_CPU(struct device
*, mce_device
);
2258 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
2260 static inline struct mce_bank
*attr_to_bank(struct device_attribute
*attr
)
2262 return container_of(attr
, struct mce_bank
, attr
);
2265 static ssize_t
show_bank(struct device
*s
, struct device_attribute
*attr
,
2268 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
2271 static ssize_t
set_bank(struct device
*s
, struct device_attribute
*attr
,
2272 const char *buf
, size_t size
)
2276 if (kstrtou64(buf
, 0, &new) < 0)
2279 attr_to_bank(attr
)->ctl
= new;
2286 show_trigger(struct device
*s
, struct device_attribute
*attr
, char *buf
)
2288 strcpy(buf
, mce_helper
);
2290 return strlen(mce_helper
) + 1;
2293 static ssize_t
set_trigger(struct device
*s
, struct device_attribute
*attr
,
2294 const char *buf
, size_t siz
)
2298 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
2299 mce_helper
[sizeof(mce_helper
)-1] = 0;
2300 p
= strchr(mce_helper
, '\n');
2305 return strlen(mce_helper
) + !!p
;
2308 static ssize_t
set_ignore_ce(struct device
*s
,
2309 struct device_attribute
*attr
,
2310 const char *buf
, size_t size
)
2314 if (kstrtou64(buf
, 0, &new) < 0)
2317 if (mca_cfg
.ignore_ce
^ !!new) {
2319 /* disable ce features */
2320 mce_timer_delete_all();
2321 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2322 mca_cfg
.ignore_ce
= true;
2324 /* enable ce features */
2325 mca_cfg
.ignore_ce
= false;
2326 on_each_cpu(mce_enable_ce
, (void *)1, 1);
2332 static ssize_t
set_cmci_disabled(struct device
*s
,
2333 struct device_attribute
*attr
,
2334 const char *buf
, size_t size
)
2338 if (kstrtou64(buf
, 0, &new) < 0)
2341 if (mca_cfg
.cmci_disabled
^ !!new) {
2344 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2345 mca_cfg
.cmci_disabled
= true;
2348 mca_cfg
.cmci_disabled
= false;
2349 on_each_cpu(mce_enable_ce
, NULL
, 1);
2355 static ssize_t
store_int_with_restart(struct device
*s
,
2356 struct device_attribute
*attr
,
2357 const char *buf
, size_t size
)
2359 ssize_t ret
= device_store_int(s
, attr
, buf
, size
);
2364 static DEVICE_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
2365 static DEVICE_INT_ATTR(tolerant
, 0644, mca_cfg
.tolerant
);
2366 static DEVICE_INT_ATTR(monarch_timeout
, 0644, mca_cfg
.monarch_timeout
);
2367 static DEVICE_BOOL_ATTR(dont_log_ce
, 0644, mca_cfg
.dont_log_ce
);
2369 static struct dev_ext_attribute dev_attr_check_interval
= {
2370 __ATTR(check_interval
, 0644, device_show_int
, store_int_with_restart
),
2374 static struct dev_ext_attribute dev_attr_ignore_ce
= {
2375 __ATTR(ignore_ce
, 0644, device_show_bool
, set_ignore_ce
),
2379 static struct dev_ext_attribute dev_attr_cmci_disabled
= {
2380 __ATTR(cmci_disabled
, 0644, device_show_bool
, set_cmci_disabled
),
2381 &mca_cfg
.cmci_disabled
2384 static struct device_attribute
*mce_device_attrs
[] = {
2385 &dev_attr_tolerant
.attr
,
2386 &dev_attr_check_interval
.attr
,
2388 &dev_attr_monarch_timeout
.attr
,
2389 &dev_attr_dont_log_ce
.attr
,
2390 &dev_attr_ignore_ce
.attr
,
2391 &dev_attr_cmci_disabled
.attr
,
2395 static cpumask_var_t mce_device_initialized
;
2397 static void mce_device_release(struct device
*dev
)
2402 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2403 static int mce_device_create(unsigned int cpu
)
2409 if (!mce_available(&boot_cpu_data
))
2412 dev
= kzalloc(sizeof *dev
, GFP_KERNEL
);
2416 dev
->bus
= &mce_subsys
;
2417 dev
->release
= &mce_device_release
;
2419 err
= device_register(dev
);
2425 for (i
= 0; mce_device_attrs
[i
]; i
++) {
2426 err
= device_create_file(dev
, mce_device_attrs
[i
]);
2430 for (j
= 0; j
< mca_cfg
.banks
; j
++) {
2431 err
= device_create_file(dev
, &mce_banks
[j
].attr
);
2435 cpumask_set_cpu(cpu
, mce_device_initialized
);
2436 per_cpu(mce_device
, cpu
) = dev
;
2441 device_remove_file(dev
, &mce_banks
[j
].attr
);
2444 device_remove_file(dev
, mce_device_attrs
[i
]);
2446 device_unregister(dev
);
2451 static void mce_device_remove(unsigned int cpu
)
2453 struct device
*dev
= per_cpu(mce_device
, cpu
);
2456 if (!cpumask_test_cpu(cpu
, mce_device_initialized
))
2459 for (i
= 0; mce_device_attrs
[i
]; i
++)
2460 device_remove_file(dev
, mce_device_attrs
[i
]);
2462 for (i
= 0; i
< mca_cfg
.banks
; i
++)
2463 device_remove_file(dev
, &mce_banks
[i
].attr
);
2465 device_unregister(dev
);
2466 cpumask_clear_cpu(cpu
, mce_device_initialized
);
2467 per_cpu(mce_device
, cpu
) = NULL
;
2470 /* Make sure there are no machine checks on offlined CPUs. */
2471 static void mce_disable_cpu(void *h
)
2473 unsigned long action
= *(unsigned long *)h
;
2475 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2478 if (!(action
& CPU_TASKS_FROZEN
))
2481 vendor_disable_error_reporting();
2484 static void mce_reenable_cpu(void *h
)
2486 unsigned long action
= *(unsigned long *)h
;
2489 if (!mce_available(raw_cpu_ptr(&cpu_info
)))
2492 if (!(action
& CPU_TASKS_FROZEN
))
2494 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
2495 struct mce_bank
*b
= &mce_banks
[i
];
2498 wrmsrl(msr_ops
.ctl(i
), b
->ctl
);
2502 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2504 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
2506 unsigned int cpu
= (unsigned long)hcpu
;
2507 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2509 switch (action
& ~CPU_TASKS_FROZEN
) {
2511 mce_device_create(cpu
);
2512 if (threshold_cpu_callback
)
2513 threshold_cpu_callback(action
, cpu
);
2516 if (threshold_cpu_callback
)
2517 threshold_cpu_callback(action
, cpu
);
2518 mce_device_remove(cpu
);
2519 mce_intel_hcpu_update(cpu
);
2521 /* intentionally ignoring frozen here */
2522 if (!(action
& CPU_TASKS_FROZEN
))
2525 case CPU_DOWN_PREPARE
:
2526 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2529 case CPU_DOWN_FAILED
:
2530 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2531 mce_start_timer(cpu
, t
);
2538 static struct notifier_block mce_cpu_notifier
= {
2539 .notifier_call
= mce_cpu_callback
,
2542 static __init
void mce_init_banks(void)
2546 for (i
= 0; i
< mca_cfg
.banks
; i
++) {
2547 struct mce_bank
*b
= &mce_banks
[i
];
2548 struct device_attribute
*a
= &b
->attr
;
2550 sysfs_attr_init(&a
->attr
);
2551 a
->attr
.name
= b
->attrname
;
2552 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2554 a
->attr
.mode
= 0644;
2555 a
->show
= show_bank
;
2556 a
->store
= set_bank
;
2560 static __init
int mcheck_init_device(void)
2565 if (!mce_available(&boot_cpu_data
)) {
2570 if (!zalloc_cpumask_var(&mce_device_initialized
, GFP_KERNEL
)) {
2577 err
= subsys_system_register(&mce_subsys
, NULL
);
2581 cpu_notifier_register_begin();
2582 for_each_online_cpu(i
) {
2583 err
= mce_device_create(i
);
2586 * Register notifier anyway (and do not unreg it) so
2587 * that we don't leave undeleted timers, see notifier
2590 __register_hotcpu_notifier(&mce_cpu_notifier
);
2591 cpu_notifier_register_done();
2592 goto err_device_create
;
2596 __register_hotcpu_notifier(&mce_cpu_notifier
);
2597 cpu_notifier_register_done();
2599 register_syscore_ops(&mce_syscore_ops
);
2601 /* register character device /dev/mcelog */
2602 err
= misc_register(&mce_chrdev_device
);
2609 unregister_syscore_ops(&mce_syscore_ops
);
2613 * We didn't keep track of which devices were created above, but
2614 * even if we had, the set of online cpus might have changed.
2615 * Play safe and remove for every possible cpu, since
2616 * mce_device_remove() will do the right thing.
2618 for_each_possible_cpu(i
)
2619 mce_device_remove(i
);
2622 free_cpumask_var(mce_device_initialized
);
2625 pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err
);
2629 device_initcall_sync(mcheck_init_device
);
2632 * Old style boot options parsing. Only for compatibility.
2634 static int __init
mcheck_disable(char *str
)
2636 mca_cfg
.disabled
= true;
2639 __setup("nomce", mcheck_disable
);
2641 #ifdef CONFIG_DEBUG_FS
2642 struct dentry
*mce_get_debugfs_dir(void)
2644 static struct dentry
*dmce
;
2647 dmce
= debugfs_create_dir("mce", NULL
);
2652 static void mce_reset(void)
2655 atomic_set(&mce_fake_panicked
, 0);
2656 atomic_set(&mce_executing
, 0);
2657 atomic_set(&mce_callin
, 0);
2658 atomic_set(&global_nwo
, 0);
2661 static int fake_panic_get(void *data
, u64
*val
)
2667 static int fake_panic_set(void *data
, u64 val
)
2674 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2675 fake_panic_set
, "%llu\n");
2677 static int __init
mcheck_debugfs_init(void)
2679 struct dentry
*dmce
, *ffake_panic
;
2681 dmce
= mce_get_debugfs_dir();
2684 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2692 static int __init
mcheck_debugfs_init(void) { return -EINVAL
; }
2695 DEFINE_STATIC_KEY_FALSE(mcsafe_key
);
2696 EXPORT_SYMBOL_GPL(mcsafe_key
);
2698 static int __init
mcheck_late_init(void)
2700 if (mca_cfg
.recovery
)
2701 static_branch_inc(&mcsafe_key
);
2703 mcheck_debugfs_init();
2706 * Flush out everything that has been logged during early boot, now that
2707 * everything has been initialized (workqueues, decoders, ...).
2709 mce_schedule_work();
2713 late_initcall(mcheck_late_init
);