2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/device.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex
);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly
;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count
);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly
= 1;
76 static int banks __read_mostly
;
77 static int rip_msr __read_mostly
;
78 static int mce_bootlog __read_mostly
= -1;
79 static int monarch_timeout __read_mostly
= -1;
80 static int mce_panic_timeout __read_mostly
;
81 static int mce_dont_log_ce __read_mostly
;
82 int mce_cmci_disabled __read_mostly
;
83 int mce_ignore_ce __read_mostly
;
84 int mce_ser __read_mostly
;
86 struct mce_bank
*mce_banks __read_mostly
;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify
;
90 static char mce_helper
[128];
91 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait
);
95 static DEFINE_PER_CPU(struct mce
, mces_seen
);
96 static int cpu_missing
;
98 /* MCA banks polled by the period polling timer for corrected events */
99 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
100 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
103 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
106 * CPU/chipset specific EDAC code can register a notifier call here to print
107 * MCE errors in a human-readable form.
109 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
111 /* Do initial initialization of a struct mce */
112 void mce_setup(struct mce
*m
)
114 memset(m
, 0, sizeof(struct mce
));
115 m
->cpu
= m
->extcpu
= smp_processor_id();
117 /* We hope get_seconds stays lockless */
118 m
->time
= get_seconds();
119 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
120 m
->cpuid
= cpuid_eax(1);
121 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
122 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
123 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
126 DEFINE_PER_CPU(struct mce
, injectm
);
127 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
130 * Lockless MCE logging infrastructure.
131 * This avoids deadlocks on printk locks without having to break locks. Also
132 * separate MCEs from kernel messages to avoid bogus bug reports.
135 static struct mce_log mcelog
= {
136 .signature
= MCE_LOG_SIGNATURE
,
138 .recordlen
= sizeof(struct mce
),
141 void mce_log(struct mce
*mce
)
143 unsigned next
, entry
;
146 /* Emit the trace record: */
147 trace_mce_record(mce
);
149 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, mce
);
150 if (ret
== NOTIFY_STOP
)
156 entry
= rcu_dereference_check_mce(mcelog
.next
);
160 * When the buffer fills up discard new entries.
161 * Assume that the earlier errors are the more
164 if (entry
>= MCE_LOG_LEN
) {
165 set_bit(MCE_OVERFLOW
,
166 (unsigned long *)&mcelog
.flags
);
169 /* Old left over entry. Skip: */
170 if (mcelog
.entry
[entry
].finished
) {
178 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
181 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
183 mcelog
.entry
[entry
].finished
= 1;
187 set_bit(0, &mce_need_notify
);
190 static void drain_mcelog_buffer(void)
192 unsigned int next
, i
, prev
= 0;
194 next
= ACCESS_ONCE(mcelog
.next
);
199 /* drain what was logged during boot */
200 for (i
= prev
; i
< next
; i
++) {
201 unsigned long start
= jiffies
;
202 unsigned retries
= 1;
204 m
= &mcelog
.entry
[i
];
206 while (!m
->finished
) {
207 if (time_after_eq(jiffies
, start
+ 2*retries
))
212 if (!m
->finished
&& retries
>= 4) {
213 pr_err("MCE: skipping error being logged currently!\n");
218 atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
221 memset(mcelog
.entry
+ prev
, 0, (next
- prev
) * sizeof(*m
));
223 next
= cmpxchg(&mcelog
.next
, prev
, 0);
224 } while (next
!= prev
);
228 void mce_register_decode_chain(struct notifier_block
*nb
)
230 atomic_notifier_chain_register(&x86_mce_decoder_chain
, nb
);
231 drain_mcelog_buffer();
233 EXPORT_SYMBOL_GPL(mce_register_decode_chain
);
235 void mce_unregister_decode_chain(struct notifier_block
*nb
)
237 atomic_notifier_chain_unregister(&x86_mce_decoder_chain
, nb
);
239 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain
);
241 static void print_mce(struct mce
*m
)
245 pr_emerg(HW_ERR
"CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
246 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
249 pr_emerg(HW_ERR
"RIP%s %02x:<%016Lx> ",
250 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
253 if (m
->cs
== __KERNEL_CS
)
254 print_symbol("{%s}", m
->ip
);
258 pr_emerg(HW_ERR
"TSC %llx ", m
->tsc
);
260 pr_cont("ADDR %llx ", m
->addr
);
262 pr_cont("MISC %llx ", m
->misc
);
266 * Note this output is parsed by external tools and old fields
267 * should not be changed.
269 pr_emerg(HW_ERR
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
270 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
,
271 cpu_data(m
->extcpu
).microcode
);
274 * Print out human-readable details about the MCE error,
275 * (if the CPU has an implementation for that)
277 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
278 if (ret
== NOTIFY_STOP
)
281 pr_emerg_ratelimited(HW_ERR
"Run the above through 'mcelog --ascii'\n");
284 #define PANIC_TIMEOUT 5 /* 5 seconds */
286 static atomic_t mce_paniced
;
288 static int fake_panic
;
289 static atomic_t mce_fake_paniced
;
291 /* Panic in progress. Enable interrupts and wait for final IPI */
292 static void wait_for_panic(void)
294 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
298 while (timeout
-- > 0)
300 if (panic_timeout
== 0)
301 panic_timeout
= mce_panic_timeout
;
302 panic("Panicing machine check CPU died");
305 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
311 * Make sure only one CPU runs in machine check panic
313 if (atomic_inc_return(&mce_paniced
) > 1)
320 /* Don't log too much for fake panic */
321 if (atomic_inc_return(&mce_fake_paniced
) > 1)
324 /* First print corrected ones that are still unlogged */
325 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
326 struct mce
*m
= &mcelog
.entry
[i
];
327 if (!(m
->status
& MCI_STATUS_VAL
))
329 if (!(m
->status
& MCI_STATUS_UC
)) {
332 apei_err
= apei_write_mce(m
);
335 /* Now print uncorrected but with the final one last */
336 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
337 struct mce
*m
= &mcelog
.entry
[i
];
338 if (!(m
->status
& MCI_STATUS_VAL
))
340 if (!(m
->status
& MCI_STATUS_UC
))
342 if (!final
|| memcmp(m
, final
, sizeof(struct mce
))) {
345 apei_err
= apei_write_mce(m
);
351 apei_err
= apei_write_mce(final
);
354 pr_emerg(HW_ERR
"Some CPUs didn't answer in synchronization\n");
356 pr_emerg(HW_ERR
"Machine check: %s\n", exp
);
358 if (panic_timeout
== 0)
359 panic_timeout
= mce_panic_timeout
;
362 pr_emerg(HW_ERR
"Fake kernel panic: %s\n", msg
);
365 /* Support code for software error injection */
367 static int msr_to_offset(u32 msr
)
369 unsigned bank
= __this_cpu_read(injectm
.bank
);
372 return offsetof(struct mce
, ip
);
373 if (msr
== MSR_IA32_MCx_STATUS(bank
))
374 return offsetof(struct mce
, status
);
375 if (msr
== MSR_IA32_MCx_ADDR(bank
))
376 return offsetof(struct mce
, addr
);
377 if (msr
== MSR_IA32_MCx_MISC(bank
))
378 return offsetof(struct mce
, misc
);
379 if (msr
== MSR_IA32_MCG_STATUS
)
380 return offsetof(struct mce
, mcgstatus
);
384 /* MSR access wrappers used for error injection */
385 static u64
mce_rdmsrl(u32 msr
)
389 if (__this_cpu_read(injectm
.finished
)) {
390 int offset
= msr_to_offset(msr
);
394 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
397 if (rdmsrl_safe(msr
, &v
)) {
398 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr
);
400 * Return zero in case the access faulted. This should
401 * not happen normally but can happen if the CPU does
402 * something weird, or if the code is buggy.
410 static void mce_wrmsrl(u32 msr
, u64 v
)
412 if (__this_cpu_read(injectm
.finished
)) {
413 int offset
= msr_to_offset(msr
);
416 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
423 * Collect all global (w.r.t. this processor) status about this machine
424 * check into our "mce" struct so that we can use it later to assess
425 * the severity of the problem as we read per-bank specific details.
427 static inline void mce_gather_info(struct mce
*m
, struct pt_regs
*regs
)
431 m
->mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
434 * Get the address of the instruction at the time of
435 * the machine check error.
437 if (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
)) {
442 * When in VM86 mode make the cs look like ring 3
443 * always. This is a lie, but it's better than passing
444 * the additional vm86 bit around everywhere.
446 if (v8086_mode(regs
))
449 /* Use accurate RIP reporting if available. */
451 m
->ip
= mce_rdmsrl(rip_msr
);
456 * Simple lockless ring to communicate PFNs from the exception handler with the
457 * process context work function. This is vastly simplified because there's
458 * only a single reader and a single writer.
460 #define MCE_RING_SIZE 16 /* we use one entry less */
463 unsigned short start
;
465 unsigned long ring
[MCE_RING_SIZE
];
467 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
469 /* Runs with CPU affinity in workqueue */
470 static int mce_ring_empty(void)
472 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
474 return r
->start
== r
->end
;
477 static int mce_ring_get(unsigned long *pfn
)
484 r
= &__get_cpu_var(mce_ring
);
485 if (r
->start
== r
->end
)
487 *pfn
= r
->ring
[r
->start
];
488 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
495 /* Always runs in MCE context with preempt off */
496 static int mce_ring_add(unsigned long pfn
)
498 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
501 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
502 if (next
== r
->start
)
504 r
->ring
[r
->end
] = pfn
;
510 int mce_available(struct cpuinfo_x86
*c
)
514 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
517 static void mce_schedule_work(void)
519 if (!mce_ring_empty()) {
520 struct work_struct
*work
= &__get_cpu_var(mce_work
);
521 if (!work_pending(work
))
526 DEFINE_PER_CPU(struct irq_work
, mce_irq_work
);
528 static void mce_irq_work_cb(struct irq_work
*entry
)
534 static void mce_report_event(struct pt_regs
*regs
)
536 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
539 * Triggering the work queue here is just an insurance
540 * policy in case the syscall exit notify handler
541 * doesn't run soon enough or ends up running on the
542 * wrong CPU (can happen when audit sleeps)
548 irq_work_queue(&__get_cpu_var(mce_irq_work
));
552 * Read ADDR and MISC registers.
554 static void mce_read_aux(struct mce
*m
, int i
)
556 if (m
->status
& MCI_STATUS_MISCV
)
557 m
->misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
558 if (m
->status
& MCI_STATUS_ADDRV
) {
559 m
->addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
562 * Mask the reported address by the reported granularity.
564 if (mce_ser
&& (m
->status
& MCI_STATUS_MISCV
)) {
565 u8 shift
= MCI_MISC_ADDR_LSB(m
->misc
);
572 DEFINE_PER_CPU(unsigned, mce_poll_count
);
575 * Poll for corrected events or events that happened before reset.
576 * Those are just logged through /dev/mcelog.
578 * This is executed in standard interrupt context.
580 * Note: spec recommends to panic for fatal unsignalled
581 * errors here. However this would be quite problematic --
582 * we would need to reimplement the Monarch handling and
583 * it would mess up the exclusion between exception handler
584 * and poll hander -- * so we skip this for now.
585 * These cases should not happen anyways, or only when the CPU
586 * is already totally * confused. In this case it's likely it will
587 * not fully execute the machine check handler either.
589 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
594 this_cpu_inc(mce_poll_count
);
596 mce_gather_info(&m
, NULL
);
598 for (i
= 0; i
< banks
; i
++) {
599 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
608 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
609 if (!(m
.status
& MCI_STATUS_VAL
))
613 * Uncorrected or signalled events are handled by the exception
614 * handler when it is enabled, so don't process those here.
616 * TBD do the same check for MCI_STATUS_EN here?
618 if (!(flags
& MCP_UC
) &&
619 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
624 if (!(flags
& MCP_TIMESTAMP
))
627 * Don't get the IP here because it's unlikely to
628 * have anything to do with the actual error location.
630 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
)
634 * Clear state for this bank.
636 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
640 * Don't clear MCG_STATUS here because it's only defined for
646 EXPORT_SYMBOL_GPL(machine_check_poll
);
649 * Do a quick check if any of the events requires a panic.
650 * This decides if we keep the events around or clear them.
652 static int mce_no_way_out(struct mce
*m
, char **msg
, unsigned long *validp
)
656 for (i
= 0; i
< banks
; i
++) {
657 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
658 if (m
->status
& MCI_STATUS_VAL
)
659 __set_bit(i
, validp
);
660 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
667 * Variable to establish order between CPUs while scanning.
668 * Each CPU spins initially until executing is equal its number.
670 static atomic_t mce_executing
;
673 * Defines order of CPUs on entry. First CPU becomes Monarch.
675 static atomic_t mce_callin
;
678 * Check if a timeout waiting for other CPUs happened.
680 static int mce_timed_out(u64
*t
)
683 * The others already did panic for some reason.
684 * Bail out like in a timeout.
685 * rmb() to tell the compiler that system_state
686 * might have been modified by someone else.
689 if (atomic_read(&mce_paniced
))
691 if (!monarch_timeout
)
693 if ((s64
)*t
< SPINUNIT
) {
694 /* CHECKME: Make panic default for 1 too? */
696 mce_panic("Timeout synchronizing machine check over CPUs",
703 touch_nmi_watchdog();
708 * The Monarch's reign. The Monarch is the CPU who entered
709 * the machine check handler first. It waits for the others to
710 * raise the exception too and then grades them. When any
711 * error is fatal panic. Only then let the others continue.
713 * The other CPUs entering the MCE handler will be controlled by the
714 * Monarch. They are called Subjects.
716 * This way we prevent any potential data corruption in a unrecoverable case
717 * and also makes sure always all CPU's errors are examined.
719 * Also this detects the case of a machine check event coming from outer
720 * space (not detected by any CPUs) In this case some external agent wants
721 * us to shut down, so panic too.
723 * The other CPUs might still decide to panic if the handler happens
724 * in a unrecoverable place, but in this case the system is in a semi-stable
725 * state and won't corrupt anything by itself. It's ok to let the others
726 * continue for a bit first.
728 * All the spin loops have timeouts; when a timeout happens a CPU
729 * typically elects itself to be Monarch.
731 static void mce_reign(void)
734 struct mce
*m
= NULL
;
735 int global_worst
= 0;
740 * This CPU is the Monarch and the other CPUs have run
741 * through their handlers.
742 * Grade the severity of the errors of all the CPUs.
744 for_each_possible_cpu(cpu
) {
745 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
747 if (severity
> global_worst
) {
749 global_worst
= severity
;
750 m
= &per_cpu(mces_seen
, cpu
);
755 * Cannot recover? Panic here then.
756 * This dumps all the mces in the log buffer and stops the
759 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
760 mce_panic("Fatal Machine check", m
, msg
);
763 * For UC somewhere we let the CPU who detects it handle it.
764 * Also must let continue the others, otherwise the handling
765 * CPU could deadlock on a lock.
769 * No machine check event found. Must be some external
770 * source or one CPU is hung. Panic.
772 if (global_worst
<= MCE_KEEP_SEVERITY
&& tolerant
< 3)
773 mce_panic("Machine check from unknown source", NULL
, NULL
);
776 * Now clear all the mces_seen so that they don't reappear on
779 for_each_possible_cpu(cpu
)
780 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
783 static atomic_t global_nwo
;
786 * Start of Monarch synchronization. This waits until all CPUs have
787 * entered the exception handler and then determines if any of them
788 * saw a fatal event that requires panic. Then it executes them
789 * in the entry order.
790 * TBD double check parallel CPU hotunplug
792 static int mce_start(int *no_way_out
)
795 int cpus
= num_online_cpus();
796 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
801 atomic_add(*no_way_out
, &global_nwo
);
803 * global_nwo should be updated before mce_callin
806 order
= atomic_inc_return(&mce_callin
);
811 while (atomic_read(&mce_callin
) != cpus
) {
812 if (mce_timed_out(&timeout
)) {
813 atomic_set(&global_nwo
, 0);
820 * mce_callin should be read before global_nwo
826 * Monarch: Starts executing now, the others wait.
828 atomic_set(&mce_executing
, 1);
831 * Subject: Now start the scanning loop one by one in
832 * the original callin order.
833 * This way when there are any shared banks it will be
834 * only seen by one CPU before cleared, avoiding duplicates.
836 while (atomic_read(&mce_executing
) < order
) {
837 if (mce_timed_out(&timeout
)) {
838 atomic_set(&global_nwo
, 0);
846 * Cache the global no_way_out state.
848 *no_way_out
= atomic_read(&global_nwo
);
854 * Synchronize between CPUs after main scanning loop.
855 * This invokes the bulk of the Monarch processing.
857 static int mce_end(int order
)
860 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
868 * Allow others to run.
870 atomic_inc(&mce_executing
);
873 /* CHECKME: Can this race with a parallel hotplug? */
874 int cpus
= num_online_cpus();
877 * Monarch: Wait for everyone to go through their scanning
880 while (atomic_read(&mce_executing
) <= cpus
) {
881 if (mce_timed_out(&timeout
))
891 * Subject: Wait for Monarch to finish.
893 while (atomic_read(&mce_executing
) != 0) {
894 if (mce_timed_out(&timeout
))
900 * Don't reset anything. That's done by the Monarch.
906 * Reset all global state.
909 atomic_set(&global_nwo
, 0);
910 atomic_set(&mce_callin
, 0);
914 * Let others run again.
916 atomic_set(&mce_executing
, 0);
921 * Check if the address reported by the CPU is in a format we can parse.
922 * It would be possible to add code for most other cases, but all would
923 * be somewhat complicated (e.g. segment offset would require an instruction
924 * parser). So only support physical addresses up to page granuality for now.
926 static int mce_usable_address(struct mce
*m
)
928 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
930 if (MCI_MISC_ADDR_LSB(m
->misc
) > PAGE_SHIFT
)
932 if (MCI_MISC_ADDR_MODE(m
->misc
) != MCI_MISC_ADDR_PHYS
)
937 static void mce_clear_state(unsigned long *toclear
)
941 for (i
= 0; i
< banks
; i
++) {
942 if (test_bit(i
, toclear
))
943 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
948 * Need to save faulting physical address associated with a process
949 * in the machine check handler some place where we can grab it back
950 * later in mce_notify_process()
952 #define MCE_INFO_MAX 16
956 struct task_struct
*t
;
959 } mce_info
[MCE_INFO_MAX
];
961 static void mce_save_info(__u64 addr
, int c
)
965 for (mi
= mce_info
; mi
< &mce_info
[MCE_INFO_MAX
]; mi
++) {
966 if (atomic_cmpxchg(&mi
->inuse
, 0, 1) == 0) {
974 mce_panic("Too many concurrent recoverable errors", NULL
, NULL
);
977 static struct mce_info
*mce_find_info(void)
981 for (mi
= mce_info
; mi
< &mce_info
[MCE_INFO_MAX
]; mi
++)
982 if (atomic_read(&mi
->inuse
) && mi
->t
== current
)
987 static void mce_clear_info(struct mce_info
*mi
)
989 atomic_set(&mi
->inuse
, 0);
993 * The actual machine check handler. This only handles real
994 * exceptions when something got corrupted coming in through int 18.
996 * This is executed in NMI context not subject to normal locking rules. This
997 * implies that most kernel services cannot be safely used. Don't even
998 * think about putting a printk in there!
1000 * On Intel systems this is entered on all CPUs in parallel through
1001 * MCE broadcast. However some CPUs might be broken beyond repair,
1002 * so be always careful when synchronizing with others.
1004 void do_machine_check(struct pt_regs
*regs
, long error_code
)
1006 struct mce m
, *final
;
1011 * Establish sequential order between the CPUs entering the machine
1016 * If no_way_out gets set, there is no safe way to recover from this
1017 * MCE. If tolerant is cranked up, we'll try anyway.
1021 * If kill_it gets set, there might be a way to recover from this
1025 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
1026 DECLARE_BITMAP(valid_banks
, MAX_NR_BANKS
);
1027 char *msg
= "Unknown";
1029 atomic_inc(&mce_entry
);
1031 this_cpu_inc(mce_exception_count
);
1036 mce_gather_info(&m
, regs
);
1038 final
= &__get_cpu_var(mces_seen
);
1041 memset(valid_banks
, 0, sizeof(valid_banks
));
1042 no_way_out
= mce_no_way_out(&m
, &msg
, valid_banks
);
1047 * When no restart IP might need to kill or panic.
1048 * Assume the worst for now, but if we find the
1049 * severity is MCE_AR_SEVERITY we have other options.
1051 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
1055 * Go through all the banks in exclusion of the other CPUs.
1056 * This way we don't report duplicated events on shared banks
1057 * because the first one to see it will clear it.
1059 order
= mce_start(&no_way_out
);
1060 for (i
= 0; i
< banks
; i
++) {
1061 __clear_bit(i
, toclear
);
1062 if (!test_bit(i
, valid_banks
))
1064 if (!mce_banks
[i
].ctl
)
1071 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
1072 if ((m
.status
& MCI_STATUS_VAL
) == 0)
1076 * Non uncorrected or non signaled errors are handled by
1077 * machine_check_poll. Leave them alone, unless this panics.
1079 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
1084 * Set taint even when machine check was not enabled.
1086 add_taint(TAINT_MACHINE_CHECK
);
1088 severity
= mce_severity(&m
, tolerant
, NULL
);
1091 * When machine check was for corrected handler don't touch,
1092 * unless we're panicing.
1094 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
1096 __set_bit(i
, toclear
);
1097 if (severity
== MCE_NO_SEVERITY
) {
1099 * Machine check event was not enabled. Clear, but
1105 mce_read_aux(&m
, i
);
1108 * Action optional error. Queue address for later processing.
1109 * When the ring overflows we just ignore the AO error.
1110 * RED-PEN add some logging mechanism when
1111 * usable_address or mce_add_ring fails.
1112 * RED-PEN don't ignore overflow for tolerant == 0
1114 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
1115 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
1119 if (severity
> worst
) {
1125 /* mce_clear_state will clear *final, save locally for use later */
1129 mce_clear_state(toclear
);
1132 * Do most of the synchronization with other CPUs.
1133 * When there's any problem use only local no_way_out state.
1135 if (mce_end(order
) < 0)
1136 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1139 * At insane "tolerant" levels we take no action. Otherwise
1140 * we only die if we have no other choice. For less serious
1141 * issues we try to recover, or limit damage to the current
1146 mce_panic("Fatal machine check on current CPU", &m
, msg
);
1147 if (worst
== MCE_AR_SEVERITY
) {
1148 /* schedule action before return to userland */
1149 mce_save_info(m
.addr
, m
.mcgstatus
& MCG_STATUS_RIPV
);
1150 set_thread_flag(TIF_MCE_NOTIFY
);
1151 } else if (kill_it
) {
1152 force_sig(SIGBUS
, current
);
1157 mce_report_event(regs
);
1158 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1160 atomic_dec(&mce_entry
);
1163 EXPORT_SYMBOL_GPL(do_machine_check
);
1165 #ifndef CONFIG_MEMORY_FAILURE
1166 int memory_failure(unsigned long pfn
, int vector
, int flags
)
1168 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1169 BUG_ON(flags
& MF_ACTION_REQUIRED
);
1170 printk(KERN_ERR
"Uncorrected memory error in page 0x%lx ignored\n"
1171 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn
);
1178 * Called in process context that interrupted by MCE and marked with
1179 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1180 * This code is allowed to sleep.
1181 * Attempt possible recovery such as calling the high level VM handler to
1182 * process any corrupted pages, and kill/signal current process if required.
1183 * Action required errors are handled here.
1185 void mce_notify_process(void)
1188 struct mce_info
*mi
= mce_find_info();
1191 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL
, NULL
);
1192 pfn
= mi
->paddr
>> PAGE_SHIFT
;
1194 clear_thread_flag(TIF_MCE_NOTIFY
);
1196 pr_err("Uncorrected hardware memory error in user-access at %llx",
1199 * We must call memory_failure() here even if the current process is
1200 * doomed. We still need to mark the page as poisoned and alert any
1201 * other users of the page.
1203 if (memory_failure(pfn
, MCE_VECTOR
, MF_ACTION_REQUIRED
) < 0 ||
1204 mi
->restartable
== 0) {
1205 pr_err("Memory error not recovered");
1206 force_sig(SIGBUS
, current
);
1212 * Action optional processing happens here (picking up
1213 * from the list of faulting pages that do_machine_check()
1214 * placed into the "ring").
1216 static void mce_process_work(struct work_struct
*dummy
)
1220 while (mce_ring_get(&pfn
))
1221 memory_failure(pfn
, MCE_VECTOR
, 0);
1224 #ifdef CONFIG_X86_MCE_INTEL
1226 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1227 * @cpu: The CPU on which the event occurred.
1228 * @status: Event status information
1230 * This function should be called by the thermal interrupt after the
1231 * event has been processed and the decision was made to log the event
1234 * The status parameter will be saved to the 'status' field of 'struct mce'
1235 * and historically has been the register value of the
1236 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1238 void mce_log_therm_throt_event(__u64 status
)
1243 m
.bank
= MCE_THERMAL_BANK
;
1247 #endif /* CONFIG_X86_MCE_INTEL */
1250 * Periodic polling timer for "silent" machine check errors. If the
1251 * poller finds an MCE, poll 2x faster. When the poller finds no more
1252 * errors, poll 2x slower (up to check_interval seconds).
1254 static unsigned long check_interval
= 5 * 60; /* 5 minutes */
1256 static DEFINE_PER_CPU(unsigned long, mce_next_interval
); /* in jiffies */
1257 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1259 static void mce_timer_fn(unsigned long data
)
1261 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1264 WARN_ON(smp_processor_id() != data
);
1266 if (mce_available(__this_cpu_ptr(&cpu_info
))) {
1267 machine_check_poll(MCP_TIMESTAMP
,
1268 &__get_cpu_var(mce_poll_banks
));
1272 * Alert userspace if needed. If we logged an MCE, reduce the
1273 * polling interval, otherwise increase the polling interval.
1275 iv
= __this_cpu_read(mce_next_interval
);
1276 if (mce_notify_irq())
1277 iv
= max(iv
, (unsigned long) HZ
/100);
1279 iv
= min(iv
* 2, round_jiffies_relative(check_interval
* HZ
));
1280 __this_cpu_write(mce_next_interval
, iv
);
1282 t
->expires
= jiffies
+ iv
;
1283 add_timer_on(t
, smp_processor_id());
1286 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1287 static void mce_timer_delete_all(void)
1291 for_each_online_cpu(cpu
)
1292 del_timer_sync(&per_cpu(mce_timer
, cpu
));
1295 static void mce_do_trigger(struct work_struct
*work
)
1297 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1300 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1303 * Notify the user(s) about new machine check events.
1304 * Can be called from interrupt context, but not from machine check/NMI
1307 int mce_notify_irq(void)
1309 /* Not more than two messages every minute */
1310 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1312 if (test_and_clear_bit(0, &mce_need_notify
)) {
1313 /* wake processes polling /dev/mcelog */
1314 wake_up_interruptible(&mce_chrdev_wait
);
1317 * There is no risk of missing notifications because
1318 * work_pending is always cleared before the function is
1321 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1322 schedule_work(&mce_trigger_work
);
1324 if (__ratelimit(&ratelimit
))
1325 pr_info(HW_ERR
"Machine check events logged\n");
1331 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1333 static int __cpuinit
__mcheck_cpu_mce_banks_init(void)
1337 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1340 for (i
= 0; i
< banks
; i
++) {
1341 struct mce_bank
*b
= &mce_banks
[i
];
1350 * Initialize Machine Checks for a CPU.
1352 static int __cpuinit
__mcheck_cpu_cap_init(void)
1357 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1359 b
= cap
& MCG_BANKCNT_MASK
;
1361 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1363 if (b
> MAX_NR_BANKS
) {
1365 "MCE: Using only %u machine check banks out of %u\n",
1370 /* Don't support asymmetric configurations today */
1371 WARN_ON(banks
!= 0 && b
!= banks
);
1374 int err
= __mcheck_cpu_mce_banks_init();
1380 /* Use accurate RIP reporting if available. */
1381 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1382 rip_msr
= MSR_IA32_MCG_EIP
;
1384 if (cap
& MCG_SER_P
)
1390 static void __mcheck_cpu_init_generic(void)
1392 mce_banks_t all_banks
;
1397 * Log the machine checks left over from the previous reset.
1399 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1400 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1402 set_in_cr4(X86_CR4_MCE
);
1404 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1405 if (cap
& MCG_CTL_P
)
1406 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1408 for (i
= 0; i
< banks
; i
++) {
1409 struct mce_bank
*b
= &mce_banks
[i
];
1413 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1414 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1418 /* Add per CPU specific workarounds here */
1419 static int __cpuinit
__mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1421 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1422 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1426 /* This should be disabled by the BIOS, but isn't always */
1427 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1428 if (c
->x86
== 15 && banks
> 4) {
1430 * disable GART TBL walk error reporting, which
1431 * trips off incorrectly with the IOMMU & 3ware
1434 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1436 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1438 * Lots of broken BIOS around that don't clear them
1439 * by default and leave crap in there. Don't log:
1444 * Various K7s with broken bank 0 around. Always disable
1447 if (c
->x86
== 6 && banks
> 0)
1448 mce_banks
[0].ctl
= 0;
1451 * Turn off MC4_MISC thresholding banks on those models since
1452 * they're not supported there.
1454 if (c
->x86
== 0x15 &&
1455 (c
->x86_model
>= 0x10 && c
->x86_model
<= 0x1f)) {
1460 0x00000413, /* MC4_MISC0 */
1461 0xc0000408, /* MC4_MISC1 */
1464 rdmsrl(MSR_K7_HWCR
, hwcr
);
1466 /* McStatusWrEn has to be set */
1467 need_toggle
= !(hwcr
& BIT(18));
1470 wrmsrl(MSR_K7_HWCR
, hwcr
| BIT(18));
1472 for (i
= 0; i
< ARRAY_SIZE(msrs
); i
++) {
1473 rdmsrl(msrs
[i
], val
);
1476 if (val
& BIT_64(62)) {
1478 wrmsrl(msrs
[i
], val
);
1482 /* restore old settings */
1484 wrmsrl(MSR_K7_HWCR
, hwcr
);
1488 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1490 * SDM documents that on family 6 bank 0 should not be written
1491 * because it aliases to another special BIOS controlled
1493 * But it's not aliased anymore on model 0x1a+
1494 * Don't ignore bank 0 completely because there could be a
1495 * valid event later, merely don't write CTL0.
1498 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1499 mce_banks
[0].init
= 0;
1502 * All newer Intel systems support MCE broadcasting. Enable
1503 * synchronization with a one second timeout.
1505 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1506 monarch_timeout
< 0)
1507 monarch_timeout
= USEC_PER_SEC
;
1510 * There are also broken BIOSes on some Pentium M and
1513 if (c
->x86
== 6 && c
->x86_model
<= 13 && mce_bootlog
< 0)
1516 if (monarch_timeout
< 0)
1517 monarch_timeout
= 0;
1518 if (mce_bootlog
!= 0)
1519 mce_panic_timeout
= 30;
1524 static int __cpuinit
__mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1529 switch (c
->x86_vendor
) {
1530 case X86_VENDOR_INTEL
:
1531 intel_p5_mcheck_init(c
);
1534 case X86_VENDOR_CENTAUR
:
1535 winchip_mcheck_init(c
);
1543 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1545 switch (c
->x86_vendor
) {
1546 case X86_VENDOR_INTEL
:
1547 mce_intel_feature_init(c
);
1549 case X86_VENDOR_AMD
:
1550 mce_amd_feature_init(c
);
1557 static void __mcheck_cpu_init_timer(void)
1559 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1560 unsigned long iv
= __this_cpu_read(mce_next_interval
);
1562 setup_timer(t
, mce_timer_fn
, smp_processor_id());
1567 __this_cpu_write(mce_next_interval
, iv
);
1570 t
->expires
= round_jiffies(jiffies
+ iv
);
1571 add_timer_on(t
, smp_processor_id());
1574 /* Handle unconfigured int18 (should never happen) */
1575 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1577 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1578 smp_processor_id());
1581 /* Call the installed machine check handler for this CPU setup. */
1582 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1583 unexpected_machine_check
;
1586 * Called for each booted CPU to set up machine checks.
1587 * Must be called with preempt off:
1589 void __cpuinit
mcheck_cpu_init(struct cpuinfo_x86
*c
)
1594 if (__mcheck_cpu_ancient_init(c
))
1597 if (!mce_available(c
))
1600 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1605 machine_check_vector
= do_machine_check
;
1607 __mcheck_cpu_init_generic();
1608 __mcheck_cpu_init_vendor(c
);
1609 __mcheck_cpu_init_timer();
1610 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1611 init_irq_work(&__get_cpu_var(mce_irq_work
), &mce_irq_work_cb
);
1615 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1618 static DEFINE_SPINLOCK(mce_chrdev_state_lock
);
1619 static int mce_chrdev_open_count
; /* #times opened */
1620 static int mce_chrdev_open_exclu
; /* already open exclusive? */
1622 static int mce_chrdev_open(struct inode
*inode
, struct file
*file
)
1624 spin_lock(&mce_chrdev_state_lock
);
1626 if (mce_chrdev_open_exclu
||
1627 (mce_chrdev_open_count
&& (file
->f_flags
& O_EXCL
))) {
1628 spin_unlock(&mce_chrdev_state_lock
);
1633 if (file
->f_flags
& O_EXCL
)
1634 mce_chrdev_open_exclu
= 1;
1635 mce_chrdev_open_count
++;
1637 spin_unlock(&mce_chrdev_state_lock
);
1639 return nonseekable_open(inode
, file
);
1642 static int mce_chrdev_release(struct inode
*inode
, struct file
*file
)
1644 spin_lock(&mce_chrdev_state_lock
);
1646 mce_chrdev_open_count
--;
1647 mce_chrdev_open_exclu
= 0;
1649 spin_unlock(&mce_chrdev_state_lock
);
1654 static void collect_tscs(void *data
)
1656 unsigned long *cpu_tsc
= (unsigned long *)data
;
1658 rdtscll(cpu_tsc
[smp_processor_id()]);
1661 static int mce_apei_read_done
;
1663 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1664 static int __mce_read_apei(char __user
**ubuf
, size_t usize
)
1670 if (usize
< sizeof(struct mce
))
1673 rc
= apei_read_mce(&m
, &record_id
);
1674 /* Error or no more MCE record */
1676 mce_apei_read_done
= 1;
1678 * When ERST is disabled, mce_chrdev_read() should return
1679 * "no record" instead of "no device."
1686 if (copy_to_user(*ubuf
, &m
, sizeof(struct mce
)))
1689 * In fact, we should have cleared the record after that has
1690 * been flushed to the disk or sent to network in
1691 * /sbin/mcelog, but we have no interface to support that now,
1692 * so just clear it to avoid duplication.
1694 rc
= apei_clear_mce(record_id
);
1696 mce_apei_read_done
= 1;
1699 *ubuf
+= sizeof(struct mce
);
1704 static ssize_t
mce_chrdev_read(struct file
*filp
, char __user
*ubuf
,
1705 size_t usize
, loff_t
*off
)
1707 char __user
*buf
= ubuf
;
1708 unsigned long *cpu_tsc
;
1709 unsigned prev
, next
;
1712 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1716 mutex_lock(&mce_chrdev_read_mutex
);
1718 if (!mce_apei_read_done
) {
1719 err
= __mce_read_apei(&buf
, usize
);
1720 if (err
|| buf
!= ubuf
)
1724 next
= rcu_dereference_check_mce(mcelog
.next
);
1726 /* Only supports full reads right now */
1728 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
))
1734 for (i
= prev
; i
< next
; i
++) {
1735 unsigned long start
= jiffies
;
1736 struct mce
*m
= &mcelog
.entry
[i
];
1738 while (!m
->finished
) {
1739 if (time_after_eq(jiffies
, start
+ 2)) {
1740 memset(m
, 0, sizeof(*m
));
1746 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1752 memset(mcelog
.entry
+ prev
, 0,
1753 (next
- prev
) * sizeof(struct mce
));
1755 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1756 } while (next
!= prev
);
1758 synchronize_sched();
1761 * Collect entries that were still getting written before the
1764 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1766 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1767 struct mce
*m
= &mcelog
.entry
[i
];
1769 if (m
->finished
&& m
->tsc
< cpu_tsc
[m
->cpu
]) {
1770 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1773 memset(m
, 0, sizeof(*m
));
1781 mutex_unlock(&mce_chrdev_read_mutex
);
1784 return err
? err
: buf
- ubuf
;
1787 static unsigned int mce_chrdev_poll(struct file
*file
, poll_table
*wait
)
1789 poll_wait(file
, &mce_chrdev_wait
, wait
);
1790 if (rcu_access_index(mcelog
.next
))
1791 return POLLIN
| POLLRDNORM
;
1792 if (!mce_apei_read_done
&& apei_check_mce())
1793 return POLLIN
| POLLRDNORM
;
1797 static long mce_chrdev_ioctl(struct file
*f
, unsigned int cmd
,
1800 int __user
*p
= (int __user
*)arg
;
1802 if (!capable(CAP_SYS_ADMIN
))
1806 case MCE_GET_RECORD_LEN
:
1807 return put_user(sizeof(struct mce
), p
);
1808 case MCE_GET_LOG_LEN
:
1809 return put_user(MCE_LOG_LEN
, p
);
1810 case MCE_GETCLEAR_FLAGS
: {
1814 flags
= mcelog
.flags
;
1815 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1817 return put_user(flags
, p
);
1824 static ssize_t (*mce_write
)(struct file
*filp
, const char __user
*ubuf
,
1825 size_t usize
, loff_t
*off
);
1827 void register_mce_write_callback(ssize_t (*fn
)(struct file
*filp
,
1828 const char __user
*ubuf
,
1829 size_t usize
, loff_t
*off
))
1833 EXPORT_SYMBOL_GPL(register_mce_write_callback
);
1835 ssize_t
mce_chrdev_write(struct file
*filp
, const char __user
*ubuf
,
1836 size_t usize
, loff_t
*off
)
1839 return mce_write(filp
, ubuf
, usize
, off
);
1844 static const struct file_operations mce_chrdev_ops
= {
1845 .open
= mce_chrdev_open
,
1846 .release
= mce_chrdev_release
,
1847 .read
= mce_chrdev_read
,
1848 .write
= mce_chrdev_write
,
1849 .poll
= mce_chrdev_poll
,
1850 .unlocked_ioctl
= mce_chrdev_ioctl
,
1851 .llseek
= no_llseek
,
1854 static struct miscdevice mce_chrdev_device
= {
1861 * mce=off Disables machine check
1862 * mce=no_cmci Disables CMCI
1863 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1864 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1865 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1866 * monarchtimeout is how long to wait for other CPUs on machine
1867 * check, or 0 to not wait
1868 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1869 * mce=nobootlog Don't log MCEs from before booting.
1871 static int __init
mcheck_enable(char *str
)
1879 if (!strcmp(str
, "off"))
1881 else if (!strcmp(str
, "no_cmci"))
1882 mce_cmci_disabled
= 1;
1883 else if (!strcmp(str
, "dont_log_ce"))
1884 mce_dont_log_ce
= 1;
1885 else if (!strcmp(str
, "ignore_ce"))
1887 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1888 mce_bootlog
= (str
[0] == 'b');
1889 else if (isdigit(str
[0])) {
1890 get_option(&str
, &tolerant
);
1893 get_option(&str
, &monarch_timeout
);
1896 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1902 __setup("mce", mcheck_enable
);
1904 int __init
mcheck_init(void)
1906 mcheck_intel_therm_init();
1912 * mce_syscore: PM support
1916 * Disable machine checks on suspend and shutdown. We can't really handle
1919 static int mce_disable_error_reporting(void)
1923 for (i
= 0; i
< banks
; i
++) {
1924 struct mce_bank
*b
= &mce_banks
[i
];
1927 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1932 static int mce_syscore_suspend(void)
1934 return mce_disable_error_reporting();
1937 static void mce_syscore_shutdown(void)
1939 mce_disable_error_reporting();
1943 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1944 * Only one CPU is active at this time, the others get re-added later using
1947 static void mce_syscore_resume(void)
1949 __mcheck_cpu_init_generic();
1950 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info
));
1953 static struct syscore_ops mce_syscore_ops
= {
1954 .suspend
= mce_syscore_suspend
,
1955 .shutdown
= mce_syscore_shutdown
,
1956 .resume
= mce_syscore_resume
,
1960 * mce_device: Sysfs support
1963 static void mce_cpu_restart(void *data
)
1965 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1967 __mcheck_cpu_init_generic();
1968 __mcheck_cpu_init_timer();
1971 /* Reinit MCEs after user configuration changes */
1972 static void mce_restart(void)
1974 mce_timer_delete_all();
1975 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1978 /* Toggle features for corrected errors */
1979 static void mce_disable_cmci(void *data
)
1981 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1986 static void mce_enable_ce(void *all
)
1988 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1993 __mcheck_cpu_init_timer();
1996 static struct bus_type mce_subsys
= {
1997 .name
= "machinecheck",
1998 .dev_name
= "machinecheck",
2001 DEFINE_PER_CPU(struct device
*, mce_device
);
2004 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
2006 static inline struct mce_bank
*attr_to_bank(struct device_attribute
*attr
)
2008 return container_of(attr
, struct mce_bank
, attr
);
2011 static ssize_t
show_bank(struct device
*s
, struct device_attribute
*attr
,
2014 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
2017 static ssize_t
set_bank(struct device
*s
, struct device_attribute
*attr
,
2018 const char *buf
, size_t size
)
2022 if (strict_strtoull(buf
, 0, &new) < 0)
2025 attr_to_bank(attr
)->ctl
= new;
2032 show_trigger(struct device
*s
, struct device_attribute
*attr
, char *buf
)
2034 strcpy(buf
, mce_helper
);
2036 return strlen(mce_helper
) + 1;
2039 static ssize_t
set_trigger(struct device
*s
, struct device_attribute
*attr
,
2040 const char *buf
, size_t siz
)
2044 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
2045 mce_helper
[sizeof(mce_helper
)-1] = 0;
2046 p
= strchr(mce_helper
, '\n');
2051 return strlen(mce_helper
) + !!p
;
2054 static ssize_t
set_ignore_ce(struct device
*s
,
2055 struct device_attribute
*attr
,
2056 const char *buf
, size_t size
)
2060 if (strict_strtoull(buf
, 0, &new) < 0)
2063 if (mce_ignore_ce
^ !!new) {
2065 /* disable ce features */
2066 mce_timer_delete_all();
2067 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2070 /* enable ce features */
2072 on_each_cpu(mce_enable_ce
, (void *)1, 1);
2078 static ssize_t
set_cmci_disabled(struct device
*s
,
2079 struct device_attribute
*attr
,
2080 const char *buf
, size_t size
)
2084 if (strict_strtoull(buf
, 0, &new) < 0)
2087 if (mce_cmci_disabled
^ !!new) {
2090 on_each_cpu(mce_disable_cmci
, NULL
, 1);
2091 mce_cmci_disabled
= 1;
2094 mce_cmci_disabled
= 0;
2095 on_each_cpu(mce_enable_ce
, NULL
, 1);
2101 static ssize_t
store_int_with_restart(struct device
*s
,
2102 struct device_attribute
*attr
,
2103 const char *buf
, size_t size
)
2105 ssize_t ret
= device_store_int(s
, attr
, buf
, size
);
2110 static DEVICE_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
2111 static DEVICE_INT_ATTR(tolerant
, 0644, tolerant
);
2112 static DEVICE_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
2113 static DEVICE_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
2115 static struct dev_ext_attribute dev_attr_check_interval
= {
2116 __ATTR(check_interval
, 0644, device_show_int
, store_int_with_restart
),
2120 static struct dev_ext_attribute dev_attr_ignore_ce
= {
2121 __ATTR(ignore_ce
, 0644, device_show_int
, set_ignore_ce
),
2125 static struct dev_ext_attribute dev_attr_cmci_disabled
= {
2126 __ATTR(cmci_disabled
, 0644, device_show_int
, set_cmci_disabled
),
2130 static struct device_attribute
*mce_device_attrs
[] = {
2131 &dev_attr_tolerant
.attr
,
2132 &dev_attr_check_interval
.attr
,
2134 &dev_attr_monarch_timeout
.attr
,
2135 &dev_attr_dont_log_ce
.attr
,
2136 &dev_attr_ignore_ce
.attr
,
2137 &dev_attr_cmci_disabled
.attr
,
2141 static cpumask_var_t mce_device_initialized
;
2143 static void mce_device_release(struct device
*dev
)
2148 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2149 static __cpuinit
int mce_device_create(unsigned int cpu
)
2155 if (!mce_available(&boot_cpu_data
))
2158 dev
= kzalloc(sizeof *dev
, GFP_KERNEL
);
2162 dev
->bus
= &mce_subsys
;
2163 dev
->release
= &mce_device_release
;
2165 err
= device_register(dev
);
2169 for (i
= 0; mce_device_attrs
[i
]; i
++) {
2170 err
= device_create_file(dev
, mce_device_attrs
[i
]);
2174 for (j
= 0; j
< banks
; j
++) {
2175 err
= device_create_file(dev
, &mce_banks
[j
].attr
);
2179 cpumask_set_cpu(cpu
, mce_device_initialized
);
2180 per_cpu(mce_device
, cpu
) = dev
;
2185 device_remove_file(dev
, &mce_banks
[j
].attr
);
2188 device_remove_file(dev
, mce_device_attrs
[i
]);
2190 device_unregister(dev
);
2195 static __cpuinit
void mce_device_remove(unsigned int cpu
)
2197 struct device
*dev
= per_cpu(mce_device
, cpu
);
2200 if (!cpumask_test_cpu(cpu
, mce_device_initialized
))
2203 for (i
= 0; mce_device_attrs
[i
]; i
++)
2204 device_remove_file(dev
, mce_device_attrs
[i
]);
2206 for (i
= 0; i
< banks
; i
++)
2207 device_remove_file(dev
, &mce_banks
[i
].attr
);
2209 device_unregister(dev
);
2210 cpumask_clear_cpu(cpu
, mce_device_initialized
);
2211 per_cpu(mce_device
, cpu
) = NULL
;
2214 /* Make sure there are no machine checks on offlined CPUs. */
2215 static void __cpuinit
mce_disable_cpu(void *h
)
2217 unsigned long action
= *(unsigned long *)h
;
2220 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2223 if (!(action
& CPU_TASKS_FROZEN
))
2225 for (i
= 0; i
< banks
; i
++) {
2226 struct mce_bank
*b
= &mce_banks
[i
];
2229 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
2233 static void __cpuinit
mce_reenable_cpu(void *h
)
2235 unsigned long action
= *(unsigned long *)h
;
2238 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2241 if (!(action
& CPU_TASKS_FROZEN
))
2243 for (i
= 0; i
< banks
; i
++) {
2244 struct mce_bank
*b
= &mce_banks
[i
];
2247 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
2251 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2252 static int __cpuinit
2253 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
2255 unsigned int cpu
= (unsigned long)hcpu
;
2256 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2260 case CPU_ONLINE_FROZEN
:
2261 mce_device_create(cpu
);
2262 if (threshold_cpu_callback
)
2263 threshold_cpu_callback(action
, cpu
);
2266 case CPU_DEAD_FROZEN
:
2267 if (threshold_cpu_callback
)
2268 threshold_cpu_callback(action
, cpu
);
2269 mce_device_remove(cpu
);
2271 case CPU_DOWN_PREPARE
:
2272 case CPU_DOWN_PREPARE_FROZEN
:
2274 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2276 case CPU_DOWN_FAILED
:
2277 case CPU_DOWN_FAILED_FROZEN
:
2278 if (!mce_ignore_ce
&& check_interval
) {
2279 t
->expires
= round_jiffies(jiffies
+
2280 per_cpu(mce_next_interval
, cpu
));
2281 add_timer_on(t
, cpu
);
2283 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2286 /* intentionally ignoring frozen here */
2287 cmci_rediscover(cpu
);
2293 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
2294 .notifier_call
= mce_cpu_callback
,
2297 static __init
void mce_init_banks(void)
2301 for (i
= 0; i
< banks
; i
++) {
2302 struct mce_bank
*b
= &mce_banks
[i
];
2303 struct device_attribute
*a
= &b
->attr
;
2305 sysfs_attr_init(&a
->attr
);
2306 a
->attr
.name
= b
->attrname
;
2307 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2309 a
->attr
.mode
= 0644;
2310 a
->show
= show_bank
;
2311 a
->store
= set_bank
;
2315 static __init
int mcheck_init_device(void)
2320 if (!mce_available(&boot_cpu_data
))
2323 zalloc_cpumask_var(&mce_device_initialized
, GFP_KERNEL
);
2327 err
= subsys_system_register(&mce_subsys
, NULL
);
2331 for_each_online_cpu(i
) {
2332 err
= mce_device_create(i
);
2337 register_syscore_ops(&mce_syscore_ops
);
2338 register_hotcpu_notifier(&mce_cpu_notifier
);
2340 /* register character device /dev/mcelog */
2341 misc_register(&mce_chrdev_device
);
2345 device_initcall(mcheck_init_device
);
2348 * Old style boot options parsing. Only for compatibility.
2350 static int __init
mcheck_disable(char *str
)
2355 __setup("nomce", mcheck_disable
);
2357 #ifdef CONFIG_DEBUG_FS
2358 struct dentry
*mce_get_debugfs_dir(void)
2360 static struct dentry
*dmce
;
2363 dmce
= debugfs_create_dir("mce", NULL
);
2368 static void mce_reset(void)
2371 atomic_set(&mce_fake_paniced
, 0);
2372 atomic_set(&mce_executing
, 0);
2373 atomic_set(&mce_callin
, 0);
2374 atomic_set(&global_nwo
, 0);
2377 static int fake_panic_get(void *data
, u64
*val
)
2383 static int fake_panic_set(void *data
, u64 val
)
2390 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2391 fake_panic_set
, "%llu\n");
2393 static int __init
mcheck_debugfs_init(void)
2395 struct dentry
*dmce
, *ffake_panic
;
2397 dmce
= mce_get_debugfs_dir();
2400 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2407 late_initcall(mcheck_debugfs_init
);