2 * (c) 2005-2016 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
8 * Maintained by: Borislav Petkov <bp@alien8.de>
10 * All MC4_MISCi registers are shared between cores on a node.
12 #include <linux/interrupt.h>
13 #include <linux/notifier.h>
14 #include <linux/kobject.h>
15 #include <linux/percpu.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/sysfs.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/cpu.h>
22 #include <linux/smp.h>
24 #include <asm/amd_nb.h>
29 #include <asm/trace/irq_vectors.h>
32 #define THRESHOLD_MAX 0xFFF
33 #define INT_TYPE_APIC 0x00020000
34 #define MASK_VALID_HI 0x80000000
35 #define MASK_CNTP_HI 0x40000000
36 #define MASK_LOCKED_HI 0x20000000
37 #define MASK_LVTOFF_HI 0x00F00000
38 #define MASK_COUNT_EN_HI 0x00080000
39 #define MASK_INT_TYPE_HI 0x00060000
40 #define MASK_OVERFLOW_HI 0x00010000
41 #define MASK_ERR_COUNT_HI 0x00000FFF
42 #define MASK_BLKPTR_LO 0xFF000000
43 #define MCG_XBLK_ADDR 0xC0000400
45 /* Deferred error settings */
46 #define MSR_CU_DEF_ERR 0xC0000410
47 #define MASK_DEF_LVTOFF 0x000000F0
48 #define MASK_DEF_INT_TYPE 0x00000006
49 #define DEF_LVT_OFF 0x2
50 #define DEF_INT_TYPE_APIC 0x2
54 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
55 #define SMCA_THR_LVT_OFF 0xF000
57 static const char * const th_names
[] = {
66 struct smca_bank_name smca_bank_names
[] = {
67 [SMCA_LS
] = { "load_store", "Load Store Unit" },
68 [SMCA_IF
] = { "insn_fetch", "Instruction Fetch Unit" },
69 [SMCA_L2_CACHE
] = { "l2_cache", "L2 Cache" },
70 [SMCA_DE
] = { "decode_unit", "Decode Unit" },
71 [SMCA_EX
] = { "execution_unit", "Execution Unit" },
72 [SMCA_FP
] = { "floating_point", "Floating Point Unit" },
73 [SMCA_L3_CACHE
] = { "l3_cache", "L3 Cache" },
74 [SMCA_CS
] = { "coherent_slave", "Coherent Slave" },
75 [SMCA_PIE
] = { "pie", "Power, Interrupts, etc." },
76 [SMCA_UMC
] = { "umc", "Unified Memory Controller" },
77 [SMCA_PB
] = { "param_block", "Parameter Block" },
78 [SMCA_PSP
] = { "psp", "Platform Security Processor" },
79 [SMCA_SMU
] = { "smu", "System Management Unit" },
81 EXPORT_SYMBOL_GPL(smca_bank_names
);
83 static struct smca_hwid_mcatype smca_hwid_mcatypes
[] = {
84 /* { bank_type, hwid_mcatype, xec_bitmap } */
86 /* ZN Core (HWID=0xB0) MCA types */
87 { SMCA_LS
, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
88 { SMCA_IF
, HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
89 { SMCA_L2_CACHE
, HWID_MCATYPE(0xB0, 0x2), 0xF },
90 { SMCA_DE
, HWID_MCATYPE(0xB0, 0x3), 0x1FF },
91 /* HWID 0xB0 MCATYPE 0x4 is Reserved */
92 { SMCA_EX
, HWID_MCATYPE(0xB0, 0x5), 0x7FF },
93 { SMCA_FP
, HWID_MCATYPE(0xB0, 0x6), 0x7F },
94 { SMCA_L3_CACHE
, HWID_MCATYPE(0xB0, 0x7), 0xFF },
96 /* Data Fabric MCA types */
97 { SMCA_CS
, HWID_MCATYPE(0x2E, 0x0), 0x1FF },
98 { SMCA_PIE
, HWID_MCATYPE(0x2E, 0x1), 0xF },
100 /* Unified Memory Controller MCA type */
101 { SMCA_UMC
, HWID_MCATYPE(0x96, 0x0), 0x3F },
103 /* Parameter Block MCA type */
104 { SMCA_PB
, HWID_MCATYPE(0x05, 0x0), 0x1 },
106 /* Platform Security Processor MCA type */
107 { SMCA_PSP
, HWID_MCATYPE(0xFF, 0x0), 0x1 },
109 /* System Management Unit MCA type */
110 { SMCA_SMU
, HWID_MCATYPE(0x01, 0x0), 0x1 },
113 struct smca_bank_info smca_banks
[MAX_NR_BANKS
];
114 EXPORT_SYMBOL_GPL(smca_banks
);
116 static DEFINE_PER_CPU(struct threshold_bank
**, threshold_banks
);
117 static DEFINE_PER_CPU(unsigned int, bank_map
); /* see which banks are on */
119 static void amd_threshold_interrupt(void);
120 static void amd_deferred_error_interrupt(void);
122 static void default_deferred_error_interrupt(void)
124 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR
);
126 void (*deferred_error_int_vector
)(void) = default_deferred_error_interrupt
;
132 static void get_smca_bank_info(unsigned int bank
)
134 unsigned int i
, hwid_mcatype
, cpu
= smp_processor_id();
135 struct smca_hwid_mcatype
*type
;
136 u32 high
, instanceId
;
139 /* Collect bank_info using CPU 0 for now. */
143 if (rdmsr_safe_on_cpu(cpu
, MSR_AMD64_SMCA_MCx_IPID(bank
), &instanceId
, &high
)) {
144 pr_warn("Failed to read MCA_IPID for bank %d\n", bank
);
148 hwid
= high
& MCI_IPID_HWID
;
149 mcatype
= (high
& MCI_IPID_MCATYPE
) >> 16;
150 hwid_mcatype
= HWID_MCATYPE(hwid
, mcatype
);
152 for (i
= 0; i
< ARRAY_SIZE(smca_hwid_mcatypes
); i
++) {
153 type
= &smca_hwid_mcatypes
[i
];
154 if (hwid_mcatype
== type
->hwid_mcatype
) {
155 smca_banks
[bank
].type
= type
;
156 smca_banks
[bank
].type_instance
= instanceId
;
162 struct thresh_restart
{
163 struct threshold_block
*b
;
170 static inline bool is_shared_bank(int bank
)
173 * Scalable MCA provides for only one core to have access to the MSRs of
179 /* Bank 4 is for northbridge reporting and is thus shared */
183 static const char *bank4_names(const struct threshold_block
*b
)
185 switch (b
->address
) {
197 WARN(1, "Funny MSR: 0x%08x\n", b
->address
);
203 static bool lvt_interrupt_supported(unsigned int bank
, u32 msr_high_bits
)
206 * bank 4 supports APIC LVT interrupts implicitly since forever.
212 * IntP: interrupt present; if this bit is set, the thresholding
213 * bank can generate APIC LVT interrupts
215 return msr_high_bits
& BIT(28);
218 static int lvt_off_valid(struct threshold_block
*b
, int apic
, u32 lo
, u32 hi
)
220 int msr
= (hi
& MASK_LVTOFF_HI
) >> 20;
223 pr_err(FW_BUG
"cpu %d, failed to setup threshold interrupt "
224 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b
->cpu
,
225 b
->bank
, b
->block
, b
->address
, hi
, lo
);
231 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
232 * the BIOS provides the value. The original field where LVT offset
233 * was set is reserved. Return early here:
238 pr_err(FW_BUG
"cpu %d, invalid threshold interrupt offset %d "
239 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
240 b
->cpu
, apic
, b
->bank
, b
->block
, b
->address
, hi
, lo
);
247 /* Reprogram MCx_MISC MSR behind this threshold bank. */
248 static void threshold_restart_bank(void *_tr
)
250 struct thresh_restart
*tr
= _tr
;
253 rdmsr(tr
->b
->address
, lo
, hi
);
255 if (tr
->b
->threshold_limit
< (hi
& THRESHOLD_MAX
))
256 tr
->reset
= 1; /* limit cannot be lower than err count */
258 if (tr
->reset
) { /* reset err count and overflow bit */
260 (hi
& ~(MASK_ERR_COUNT_HI
| MASK_OVERFLOW_HI
)) |
261 (THRESHOLD_MAX
- tr
->b
->threshold_limit
);
262 } else if (tr
->old_limit
) { /* change limit w/o reset */
263 int new_count
= (hi
& THRESHOLD_MAX
) +
264 (tr
->old_limit
- tr
->b
->threshold_limit
);
266 hi
= (hi
& ~MASK_ERR_COUNT_HI
) |
267 (new_count
& THRESHOLD_MAX
);
271 hi
&= ~MASK_INT_TYPE_HI
;
273 if (!tr
->b
->interrupt_capable
)
276 if (tr
->set_lvt_off
) {
277 if (lvt_off_valid(tr
->b
, tr
->lvt_off
, lo
, hi
)) {
278 /* set new lvt offset */
279 hi
&= ~MASK_LVTOFF_HI
;
280 hi
|= tr
->lvt_off
<< 20;
284 if (tr
->b
->interrupt_enable
)
289 hi
|= MASK_COUNT_EN_HI
;
290 wrmsr(tr
->b
->address
, lo
, hi
);
293 static void mce_threshold_block_init(struct threshold_block
*b
, int offset
)
295 struct thresh_restart tr
= {
301 b
->threshold_limit
= THRESHOLD_MAX
;
302 threshold_restart_bank(&tr
);
305 static int setup_APIC_mce_threshold(int reserved
, int new)
307 if (reserved
< 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR
,
308 APIC_EILVT_MSG_FIX
, 0))
314 static int setup_APIC_deferred_error(int reserved
, int new)
316 if (reserved
< 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR
,
317 APIC_EILVT_MSG_FIX
, 0))
323 static void deferred_error_interrupt_enable(struct cpuinfo_x86
*c
)
325 u32 low
= 0, high
= 0;
326 int def_offset
= -1, def_new
;
328 if (rdmsr_safe(MSR_CU_DEF_ERR
, &low
, &high
))
331 def_new
= (low
& MASK_DEF_LVTOFF
) >> 4;
332 if (!(low
& MASK_DEF_LVTOFF
)) {
333 pr_err(FW_BUG
"Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
334 def_new
= DEF_LVT_OFF
;
335 low
= (low
& ~MASK_DEF_LVTOFF
) | (DEF_LVT_OFF
<< 4);
338 def_offset
= setup_APIC_deferred_error(def_offset
, def_new
);
339 if ((def_offset
== def_new
) &&
340 (deferred_error_int_vector
!= amd_deferred_error_interrupt
))
341 deferred_error_int_vector
= amd_deferred_error_interrupt
;
343 low
= (low
& ~MASK_DEF_INT_TYPE
) | DEF_INT_TYPE_APIC
;
344 wrmsr(MSR_CU_DEF_ERR
, low
, high
);
347 static u32
get_block_address(unsigned int cpu
, u32 current_addr
, u32 low
, u32 high
,
348 unsigned int bank
, unsigned int block
)
350 u32 addr
= 0, offset
= 0;
352 if (mce_flags
.smca
) {
354 addr
= MSR_AMD64_SMCA_MCx_MISC(bank
);
357 * For SMCA enabled processors, BLKPTR field of the
358 * first MISC register (MCx_MISC0) indicates presence of
359 * additional MISC register set (MISC1-4).
363 if (rdmsr_safe_on_cpu(cpu
, MSR_AMD64_SMCA_MCx_CONFIG(bank
), &low
, &high
))
366 if (!(low
& MCI_CONFIG_MCAX
))
369 if (!rdmsr_safe_on_cpu(cpu
, MSR_AMD64_SMCA_MCx_MISC(bank
), &low
, &high
) &&
370 (low
& MASK_BLKPTR_LO
))
371 addr
= MSR_AMD64_SMCA_MCx_MISCy(bank
, block
- 1);
376 /* Fall back to method we used for older processors: */
379 addr
= msr_ops
.misc(bank
);
382 offset
= ((low
& MASK_BLKPTR_LO
) >> 21);
384 addr
= MCG_XBLK_ADDR
+ offset
;
387 addr
= ++current_addr
;
393 prepare_threshold_block(unsigned int bank
, unsigned int block
, u32 addr
,
394 int offset
, u32 misc_high
)
396 unsigned int cpu
= smp_processor_id();
397 u32 smca_low
, smca_high
, smca_addr
;
398 struct threshold_block b
;
402 per_cpu(bank_map
, cpu
) |= (1 << bank
);
404 memset(&b
, 0, sizeof(b
));
409 b
.interrupt_capable
= lvt_interrupt_supported(bank
, misc_high
);
411 if (!b
.interrupt_capable
)
414 b
.interrupt_enable
= 1;
416 if (!mce_flags
.smca
) {
417 new = (misc_high
& MASK_LVTOFF_HI
) >> 20;
421 smca_addr
= MSR_AMD64_SMCA_MCx_CONFIG(bank
);
423 if (!rdmsr_safe(smca_addr
, &smca_low
, &smca_high
)) {
425 * OS is required to set the MCAX bit to acknowledge that it is
426 * now using the new MSR ranges and new registers under each
427 * bank. It also means that the OS will configure deferred
428 * errors in the new MCx_CONFIG register. If the bit is not set,
429 * uncorrectable errors will cause a system panic.
431 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
436 * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR}
437 * registers with the option of additionally logging to
438 * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set.
440 * This bit is usually set by BIOS to retain the old behavior
441 * for OSes that don't use the new registers. Linux supports the
442 * new registers so let's disable that additional logging here.
444 * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high
445 * portion of the MSR).
447 smca_high
&= ~BIT(2);
449 wrmsr(smca_addr
, smca_low
, smca_high
);
452 /* Gather LVT offset for thresholding: */
453 if (rdmsr_safe(MSR_CU_DEF_ERR
, &smca_low
, &smca_high
))
456 new = (smca_low
& SMCA_THR_LVT_OFF
) >> 12;
459 offset
= setup_APIC_mce_threshold(offset
, new);
461 if ((offset
== new) && (mce_threshold_vector
!= amd_threshold_interrupt
))
462 mce_threshold_vector
= amd_threshold_interrupt
;
465 mce_threshold_block_init(&b
, offset
);
471 /* cpu init entry point, called from mce.c with preempt off */
472 void mce_amd_feature_init(struct cpuinfo_x86
*c
)
474 u32 low
= 0, high
= 0, address
= 0;
475 unsigned int bank
, block
, cpu
= smp_processor_id();
478 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
480 get_smca_bank_info(bank
);
482 for (block
= 0; block
< NR_BLOCKS
; ++block
) {
483 address
= get_block_address(cpu
, address
, low
, high
, bank
, block
);
487 if (rdmsr_safe(address
, &low
, &high
))
490 if (!(high
& MASK_VALID_HI
))
493 if (!(high
& MASK_CNTP_HI
) ||
494 (high
& MASK_LOCKED_HI
))
497 offset
= prepare_threshold_block(bank
, block
, address
, offset
, high
);
501 if (mce_flags
.succor
)
502 deferred_error_interrupt_enable(c
);
506 __log_error(unsigned int bank
, bool deferred_err
, bool threshold_err
, u64 misc
)
508 u32 msr_status
= msr_ops
.status(bank
);
509 u32 msr_addr
= msr_ops
.addr(bank
);
513 WARN_ON_ONCE(deferred_err
&& threshold_err
);
515 if (deferred_err
&& mce_flags
.smca
) {
516 msr_status
= MSR_AMD64_SMCA_MCx_DESTAT(bank
);
517 msr_addr
= MSR_AMD64_SMCA_MCx_DEADDR(bank
);
520 rdmsrl(msr_status
, status
);
522 if (!(status
& MCI_STATUS_VAL
))
533 if (m
.status
& MCI_STATUS_ADDRV
)
534 rdmsrl(msr_addr
, m
.addr
);
536 if (mce_flags
.smca
&& (m
.status
& MCI_STATUS_SYNDV
))
537 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank
), m
.synd
);
541 wrmsrl(msr_status
, 0);
544 static inline void __smp_deferred_error_interrupt(void)
546 inc_irq_stat(irq_deferred_error_count
);
547 deferred_error_int_vector();
550 asmlinkage __visible
void smp_deferred_error_interrupt(void)
553 __smp_deferred_error_interrupt();
557 asmlinkage __visible
void smp_trace_deferred_error_interrupt(void)
560 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR
);
561 __smp_deferred_error_interrupt();
562 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR
);
566 /* APIC interrupt handler for deferred errors */
567 static void amd_deferred_error_interrupt(void)
573 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
574 msr_status
= (mce_flags
.smca
) ? MSR_AMD64_SMCA_MCx_DESTAT(bank
)
575 : msr_ops
.status(bank
);
577 rdmsrl(msr_status
, status
);
579 if (!(status
& MCI_STATUS_VAL
) ||
580 !(status
& MCI_STATUS_DEFERRED
))
583 __log_error(bank
, true, false, 0);
589 * APIC Interrupt Handler
593 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
594 * the interrupt goes off when error_count reaches threshold_limit.
595 * the handler will simply log mcelog w/ software defined bank number.
598 static void amd_threshold_interrupt(void)
600 u32 low
= 0, high
= 0, address
= 0;
601 unsigned int bank
, block
, cpu
= smp_processor_id();
603 /* assume first bank caused it */
604 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
605 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
607 for (block
= 0; block
< NR_BLOCKS
; ++block
) {
608 address
= get_block_address(cpu
, address
, low
, high
, bank
, block
);
612 if (rdmsr_safe(address
, &low
, &high
))
615 if (!(high
& MASK_VALID_HI
)) {
622 if (!(high
& MASK_CNTP_HI
) ||
623 (high
& MASK_LOCKED_HI
))
627 * Log the machine check that caused the threshold
630 if (high
& MASK_OVERFLOW_HI
)
637 __log_error(bank
, false, true, ((u64
)high
<< 32) | low
);
644 struct threshold_attr
{
645 struct attribute attr
;
646 ssize_t (*show
) (struct threshold_block
*, char *);
647 ssize_t (*store
) (struct threshold_block
*, const char *, size_t count
);
650 #define SHOW_FIELDS(name) \
651 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
653 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
655 SHOW_FIELDS(interrupt_enable
)
656 SHOW_FIELDS(threshold_limit
)
659 store_interrupt_enable(struct threshold_block
*b
, const char *buf
, size_t size
)
661 struct thresh_restart tr
;
664 if (!b
->interrupt_capable
)
667 if (kstrtoul(buf
, 0, &new) < 0)
670 b
->interrupt_enable
= !!new;
672 memset(&tr
, 0, sizeof(tr
));
675 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
681 store_threshold_limit(struct threshold_block
*b
, const char *buf
, size_t size
)
683 struct thresh_restart tr
;
686 if (kstrtoul(buf
, 0, &new) < 0)
689 if (new > THRESHOLD_MAX
)
694 memset(&tr
, 0, sizeof(tr
));
695 tr
.old_limit
= b
->threshold_limit
;
696 b
->threshold_limit
= new;
699 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
704 static ssize_t
show_error_count(struct threshold_block
*b
, char *buf
)
708 rdmsr_on_cpu(b
->cpu
, b
->address
, &lo
, &hi
);
710 return sprintf(buf
, "%u\n", ((hi
& THRESHOLD_MAX
) -
711 (THRESHOLD_MAX
- b
->threshold_limit
)));
714 static struct threshold_attr error_count
= {
715 .attr
= {.name
= __stringify(error_count
), .mode
= 0444 },
716 .show
= show_error_count
,
719 #define RW_ATTR(val) \
720 static struct threshold_attr val = { \
721 .attr = {.name = __stringify(val), .mode = 0644 }, \
722 .show = show_## val, \
723 .store = store_## val, \
726 RW_ATTR(interrupt_enable
);
727 RW_ATTR(threshold_limit
);
729 static struct attribute
*default_attrs
[] = {
730 &threshold_limit
.attr
,
732 NULL
, /* possibly interrupt_enable if supported, see below */
736 #define to_block(k) container_of(k, struct threshold_block, kobj)
737 #define to_attr(a) container_of(a, struct threshold_attr, attr)
739 static ssize_t
show(struct kobject
*kobj
, struct attribute
*attr
, char *buf
)
741 struct threshold_block
*b
= to_block(kobj
);
742 struct threshold_attr
*a
= to_attr(attr
);
745 ret
= a
->show
? a
->show(b
, buf
) : -EIO
;
750 static ssize_t
store(struct kobject
*kobj
, struct attribute
*attr
,
751 const char *buf
, size_t count
)
753 struct threshold_block
*b
= to_block(kobj
);
754 struct threshold_attr
*a
= to_attr(attr
);
757 ret
= a
->store
? a
->store(b
, buf
, count
) : -EIO
;
762 static const struct sysfs_ops threshold_ops
= {
767 static struct kobj_type threshold_ktype
= {
768 .sysfs_ops
= &threshold_ops
,
769 .default_attrs
= default_attrs
,
772 static int allocate_threshold_blocks(unsigned int cpu
, unsigned int bank
,
773 unsigned int block
, u32 address
)
775 struct threshold_block
*b
= NULL
;
779 if ((bank
>= mca_cfg
.banks
) || (block
>= NR_BLOCKS
))
782 if (rdmsr_safe_on_cpu(cpu
, address
, &low
, &high
))
785 if (!(high
& MASK_VALID_HI
)) {
792 if (!(high
& MASK_CNTP_HI
) ||
793 (high
& MASK_LOCKED_HI
))
796 b
= kzalloc(sizeof(struct threshold_block
), GFP_KERNEL
);
803 b
->address
= address
;
804 b
->interrupt_enable
= 0;
805 b
->interrupt_capable
= lvt_interrupt_supported(bank
, high
);
806 b
->threshold_limit
= THRESHOLD_MAX
;
808 if (b
->interrupt_capable
) {
809 threshold_ktype
.default_attrs
[2] = &interrupt_enable
.attr
;
810 b
->interrupt_enable
= 1;
812 threshold_ktype
.default_attrs
[2] = NULL
;
815 INIT_LIST_HEAD(&b
->miscj
);
817 if (per_cpu(threshold_banks
, cpu
)[bank
]->blocks
) {
819 &per_cpu(threshold_banks
, cpu
)[bank
]->blocks
->miscj
);
821 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= b
;
824 err
= kobject_init_and_add(&b
->kobj
, &threshold_ktype
,
825 per_cpu(threshold_banks
, cpu
)[bank
]->kobj
,
826 (bank
== 4 ? bank4_names(b
) : th_names
[bank
]));
830 address
= get_block_address(cpu
, address
, low
, high
, bank
, ++block
);
834 err
= allocate_threshold_blocks(cpu
, bank
, block
, address
);
839 kobject_uevent(&b
->kobj
, KOBJ_ADD
);
845 kobject_put(&b
->kobj
);
852 static int __threshold_add_blocks(struct threshold_bank
*b
)
854 struct list_head
*head
= &b
->blocks
->miscj
;
855 struct threshold_block
*pos
= NULL
;
856 struct threshold_block
*tmp
= NULL
;
859 err
= kobject_add(&b
->blocks
->kobj
, b
->kobj
, b
->blocks
->kobj
.name
);
863 list_for_each_entry_safe(pos
, tmp
, head
, miscj
) {
865 err
= kobject_add(&pos
->kobj
, b
->kobj
, pos
->kobj
.name
);
867 list_for_each_entry_safe_reverse(pos
, tmp
, head
, miscj
)
868 kobject_del(&pos
->kobj
);
876 static int threshold_create_bank(unsigned int cpu
, unsigned int bank
)
878 struct device
*dev
= per_cpu(mce_device
, cpu
);
879 struct amd_northbridge
*nb
= NULL
;
880 struct threshold_bank
*b
= NULL
;
881 const char *name
= th_names
[bank
];
884 if (is_shared_bank(bank
)) {
885 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
887 /* threshold descriptor already initialized on this node? */
888 if (nb
&& nb
->bank4
) {
891 err
= kobject_add(b
->kobj
, &dev
->kobj
, name
);
895 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
896 atomic_inc(&b
->cpus
);
898 err
= __threshold_add_blocks(b
);
904 b
= kzalloc(sizeof(struct threshold_bank
), GFP_KERNEL
);
910 b
->kobj
= kobject_create_and_add(name
, &dev
->kobj
);
916 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
918 if (is_shared_bank(bank
)) {
919 atomic_set(&b
->cpus
, 1);
921 /* nb is already initialized, see above */
928 err
= allocate_threshold_blocks(cpu
, bank
, 0, msr_ops
.misc(bank
));
939 /* create dir/files for all valid threshold banks */
940 static int threshold_create_device(unsigned int cpu
)
943 struct threshold_bank
**bp
;
946 bp
= kzalloc(sizeof(struct threshold_bank
*) * mca_cfg
.banks
,
951 per_cpu(threshold_banks
, cpu
) = bp
;
953 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
954 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
956 err
= threshold_create_bank(cpu
, bank
);
964 static void deallocate_threshold_block(unsigned int cpu
,
967 struct threshold_block
*pos
= NULL
;
968 struct threshold_block
*tmp
= NULL
;
969 struct threshold_bank
*head
= per_cpu(threshold_banks
, cpu
)[bank
];
974 list_for_each_entry_safe(pos
, tmp
, &head
->blocks
->miscj
, miscj
) {
975 kobject_put(&pos
->kobj
);
976 list_del(&pos
->miscj
);
980 kfree(per_cpu(threshold_banks
, cpu
)[bank
]->blocks
);
981 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= NULL
;
984 static void __threshold_remove_blocks(struct threshold_bank
*b
)
986 struct threshold_block
*pos
= NULL
;
987 struct threshold_block
*tmp
= NULL
;
989 kobject_del(b
->kobj
);
991 list_for_each_entry_safe(pos
, tmp
, &b
->blocks
->miscj
, miscj
)
992 kobject_del(&pos
->kobj
);
995 static void threshold_remove_bank(unsigned int cpu
, int bank
)
997 struct amd_northbridge
*nb
;
998 struct threshold_bank
*b
;
1000 b
= per_cpu(threshold_banks
, cpu
)[bank
];
1007 if (is_shared_bank(bank
)) {
1008 if (!atomic_dec_and_test(&b
->cpus
)) {
1009 __threshold_remove_blocks(b
);
1010 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
1014 * the last CPU on this node using the shared bank is
1015 * going away, remove that bank now.
1017 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
1022 deallocate_threshold_block(cpu
, bank
);
1025 kobject_del(b
->kobj
);
1026 kobject_put(b
->kobj
);
1028 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
1031 static void threshold_remove_device(unsigned int cpu
)
1035 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
1036 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
1038 threshold_remove_bank(cpu
, bank
);
1040 kfree(per_cpu(threshold_banks
, cpu
));
1043 /* get notified when a cpu comes on/off */
1045 amd_64_threshold_cpu_callback(unsigned long action
, unsigned int cpu
)
1049 case CPU_ONLINE_FROZEN
:
1050 threshold_create_device(cpu
);
1053 case CPU_DEAD_FROZEN
:
1054 threshold_remove_device(cpu
);
1061 static __init
int threshold_init_device(void)
1065 /* to hit CPUs online before the notifier is up */
1066 for_each_online_cpu(lcpu
) {
1067 int err
= threshold_create_device(lcpu
);
1072 threshold_cpu_callback
= amd_64_threshold_cpu_callback
;
1077 * there are 3 funcs which need to be _initcalled in a logic sequence:
1078 * 1. xen_late_init_mcelog
1079 * 2. mcheck_init_device
1080 * 3. threshold_init_device
1082 * xen_late_init_mcelog must register xen_mce_chrdev_device before
1083 * native mce_chrdev_device registration if running under xen platform;
1085 * mcheck_init_device should be inited before threshold_init_device to
1086 * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1088 * so we use following _initcalls
1089 * 1. device_initcall(xen_late_init_mcelog);
1090 * 2. device_initcall_sync(mcheck_init_device);
1091 * 3. late_initcall(threshold_init_device);
1093 * when running under xen, the initcall order is 1,2,3;
1094 * on baremetal, we skip 1 and we do only 2 and 3.
1096 late_initcall(threshold_init_device
);