2 * (c) 2005-2016 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
8 * Maintained by: Borislav Petkov <bp@alien8.de>
10 * All MC4_MISCi registers are shared between cores on a node.
12 #include <linux/interrupt.h>
13 #include <linux/notifier.h>
14 #include <linux/kobject.h>
15 #include <linux/percpu.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/sysfs.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/cpu.h>
22 #include <linux/smp.h>
23 #include <linux/string.h>
25 #include <asm/amd_nb.h>
29 #include <asm/trace/irq_vectors.h>
32 #define THRESHOLD_MAX 0xFFF
33 #define INT_TYPE_APIC 0x00020000
34 #define MASK_VALID_HI 0x80000000
35 #define MASK_CNTP_HI 0x40000000
36 #define MASK_LOCKED_HI 0x20000000
37 #define MASK_LVTOFF_HI 0x00F00000
38 #define MASK_COUNT_EN_HI 0x00080000
39 #define MASK_INT_TYPE_HI 0x00060000
40 #define MASK_OVERFLOW_HI 0x00010000
41 #define MASK_ERR_COUNT_HI 0x00000FFF
42 #define MASK_BLKPTR_LO 0xFF000000
43 #define MCG_XBLK_ADDR 0xC0000400
45 /* Deferred error settings */
46 #define MSR_CU_DEF_ERR 0xC0000410
47 #define MASK_DEF_LVTOFF 0x000000F0
48 #define MASK_DEF_INT_TYPE 0x00000006
49 #define DEF_LVT_OFF 0x2
50 #define DEF_INT_TYPE_APIC 0x2
54 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
55 #define SMCA_THR_LVT_OFF 0xF000
57 static bool thresholding_en
;
59 static const char * const th_names
[] = {
68 static const char * const smca_umc_block_names
[] = {
73 struct smca_bank_name
{
74 const char *name
; /* Short name for sysfs */
75 const char *long_name
; /* Long name for pretty-printing */
78 static struct smca_bank_name smca_names
[] = {
79 [SMCA_LS
] = { "load_store", "Load Store Unit" },
80 [SMCA_IF
] = { "insn_fetch", "Instruction Fetch Unit" },
81 [SMCA_L2_CACHE
] = { "l2_cache", "L2 Cache" },
82 [SMCA_DE
] = { "decode_unit", "Decode Unit" },
83 [SMCA_EX
] = { "execution_unit", "Execution Unit" },
84 [SMCA_FP
] = { "floating_point", "Floating Point Unit" },
85 [SMCA_L3_CACHE
] = { "l3_cache", "L3 Cache" },
86 [SMCA_CS
] = { "coherent_slave", "Coherent Slave" },
87 [SMCA_PIE
] = { "pie", "Power, Interrupts, etc." },
88 [SMCA_UMC
] = { "umc", "Unified Memory Controller" },
89 [SMCA_PB
] = { "param_block", "Parameter Block" },
90 [SMCA_PSP
] = { "psp", "Platform Security Processor" },
91 [SMCA_SMU
] = { "smu", "System Management Unit" },
94 const char *smca_get_name(enum smca_bank_types t
)
96 if (t
>= N_SMCA_BANK_TYPES
)
99 return smca_names
[t
].name
;
102 const char *smca_get_long_name(enum smca_bank_types t
)
104 if (t
>= N_SMCA_BANK_TYPES
)
107 return smca_names
[t
].long_name
;
109 EXPORT_SYMBOL_GPL(smca_get_long_name
);
111 static struct smca_hwid smca_hwid_mcatypes
[] = {
112 /* { bank_type, hwid_mcatype, xec_bitmap } */
114 /* ZN Core (HWID=0xB0) MCA types */
115 { SMCA_LS
, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
116 { SMCA_IF
, HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
117 { SMCA_L2_CACHE
, HWID_MCATYPE(0xB0, 0x2), 0xF },
118 { SMCA_DE
, HWID_MCATYPE(0xB0, 0x3), 0x1FF },
119 /* HWID 0xB0 MCATYPE 0x4 is Reserved */
120 { SMCA_EX
, HWID_MCATYPE(0xB0, 0x5), 0x7FF },
121 { SMCA_FP
, HWID_MCATYPE(0xB0, 0x6), 0x7F },
122 { SMCA_L3_CACHE
, HWID_MCATYPE(0xB0, 0x7), 0xFF },
124 /* Data Fabric MCA types */
125 { SMCA_CS
, HWID_MCATYPE(0x2E, 0x0), 0x1FF },
126 { SMCA_PIE
, HWID_MCATYPE(0x2E, 0x1), 0xF },
128 /* Unified Memory Controller MCA type */
129 { SMCA_UMC
, HWID_MCATYPE(0x96, 0x0), 0x3F },
131 /* Parameter Block MCA type */
132 { SMCA_PB
, HWID_MCATYPE(0x05, 0x0), 0x1 },
134 /* Platform Security Processor MCA type */
135 { SMCA_PSP
, HWID_MCATYPE(0xFF, 0x0), 0x1 },
137 /* System Management Unit MCA type */
138 { SMCA_SMU
, HWID_MCATYPE(0x01, 0x0), 0x1 },
141 struct smca_bank smca_banks
[MAX_NR_BANKS
];
142 EXPORT_SYMBOL_GPL(smca_banks
);
145 * In SMCA enabled processors, we can have multiple banks for a given IP type.
146 * So to define a unique name for each bank, we use a temp c-string to append
147 * the MCA_IPID[InstanceId] to type's name in get_name().
149 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
150 * is greater than 8 plus 1 (for underscore) plus length of longest type name.
152 #define MAX_MCATYPE_NAME_LEN 30
153 static char buf_mcatype
[MAX_MCATYPE_NAME_LEN
];
155 static DEFINE_PER_CPU(struct threshold_bank
**, threshold_banks
);
156 static DEFINE_PER_CPU(unsigned int, bank_map
); /* see which banks are on */
158 static void amd_threshold_interrupt(void);
159 static void amd_deferred_error_interrupt(void);
161 static void default_deferred_error_interrupt(void)
163 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR
);
165 void (*deferred_error_int_vector
)(void) = default_deferred_error_interrupt
;
167 static void smca_configure(unsigned int bank
, unsigned int cpu
)
169 unsigned int i
, hwid_mcatype
;
170 struct smca_hwid
*s_hwid
;
172 u32 smca_config
= MSR_AMD64_SMCA_MCx_CONFIG(bank
);
174 /* Set appropriate bits in MCA_CONFIG */
175 if (!rdmsr_safe(smca_config
, &low
, &high
)) {
177 * OS is required to set the MCAX bit to acknowledge that it is
178 * now using the new MSR ranges and new registers under each
179 * bank. It also means that the OS will configure deferred
180 * errors in the new MCx_CONFIG register. If the bit is not set,
181 * uncorrectable errors will cause a system panic.
183 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
188 * SMCA sets the Deferred Error Interrupt type per bank.
190 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
191 * if the DeferredIntType bit field is available.
193 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
194 * high portion of the MSR). OS should set this to 0x1 to enable
195 * APIC based interrupt. First, check that no interrupt has been
198 if ((low
& BIT(5)) && !((high
>> 5) & 0x3))
201 wrmsr(smca_config
, low
, high
);
204 /* Return early if this bank was already initialized. */
205 if (smca_banks
[bank
].hwid
)
208 if (rdmsr_safe_on_cpu(cpu
, MSR_AMD64_SMCA_MCx_IPID(bank
), &low
, &high
)) {
209 pr_warn("Failed to read MCA_IPID for bank %d\n", bank
);
213 hwid_mcatype
= HWID_MCATYPE(high
& MCI_IPID_HWID
,
214 (high
& MCI_IPID_MCATYPE
) >> 16);
216 for (i
= 0; i
< ARRAY_SIZE(smca_hwid_mcatypes
); i
++) {
217 s_hwid
= &smca_hwid_mcatypes
[i
];
218 if (hwid_mcatype
== s_hwid
->hwid_mcatype
) {
219 smca_banks
[bank
].hwid
= s_hwid
;
220 smca_banks
[bank
].id
= low
;
221 smca_banks
[bank
].sysfs_id
= s_hwid
->count
++;
227 struct thresh_restart
{
228 struct threshold_block
*b
;
235 static inline bool is_shared_bank(int bank
)
238 * Scalable MCA provides for only one core to have access to the MSRs of
244 /* Bank 4 is for northbridge reporting and is thus shared */
248 static const char *bank4_names(const struct threshold_block
*b
)
250 switch (b
->address
) {
262 WARN(1, "Funny MSR: 0x%08x\n", b
->address
);
268 static bool lvt_interrupt_supported(unsigned int bank
, u32 msr_high_bits
)
271 * bank 4 supports APIC LVT interrupts implicitly since forever.
277 * IntP: interrupt present; if this bit is set, the thresholding
278 * bank can generate APIC LVT interrupts
280 return msr_high_bits
& BIT(28);
283 static int lvt_off_valid(struct threshold_block
*b
, int apic
, u32 lo
, u32 hi
)
285 int msr
= (hi
& MASK_LVTOFF_HI
) >> 20;
288 pr_err(FW_BUG
"cpu %d, failed to setup threshold interrupt "
289 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b
->cpu
,
290 b
->bank
, b
->block
, b
->address
, hi
, lo
);
296 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
297 * the BIOS provides the value. The original field where LVT offset
298 * was set is reserved. Return early here:
303 pr_err(FW_BUG
"cpu %d, invalid threshold interrupt offset %d "
304 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
305 b
->cpu
, apic
, b
->bank
, b
->block
, b
->address
, hi
, lo
);
312 /* Reprogram MCx_MISC MSR behind this threshold bank. */
313 static void threshold_restart_bank(void *_tr
)
315 struct thresh_restart
*tr
= _tr
;
318 rdmsr(tr
->b
->address
, lo
, hi
);
320 if (tr
->b
->threshold_limit
< (hi
& THRESHOLD_MAX
))
321 tr
->reset
= 1; /* limit cannot be lower than err count */
323 if (tr
->reset
) { /* reset err count and overflow bit */
325 (hi
& ~(MASK_ERR_COUNT_HI
| MASK_OVERFLOW_HI
)) |
326 (THRESHOLD_MAX
- tr
->b
->threshold_limit
);
327 } else if (tr
->old_limit
) { /* change limit w/o reset */
328 int new_count
= (hi
& THRESHOLD_MAX
) +
329 (tr
->old_limit
- tr
->b
->threshold_limit
);
331 hi
= (hi
& ~MASK_ERR_COUNT_HI
) |
332 (new_count
& THRESHOLD_MAX
);
336 hi
&= ~MASK_INT_TYPE_HI
;
338 if (!tr
->b
->interrupt_capable
)
341 if (tr
->set_lvt_off
) {
342 if (lvt_off_valid(tr
->b
, tr
->lvt_off
, lo
, hi
)) {
343 /* set new lvt offset */
344 hi
&= ~MASK_LVTOFF_HI
;
345 hi
|= tr
->lvt_off
<< 20;
349 if (tr
->b
->interrupt_enable
)
354 hi
|= MASK_COUNT_EN_HI
;
355 wrmsr(tr
->b
->address
, lo
, hi
);
358 static void mce_threshold_block_init(struct threshold_block
*b
, int offset
)
360 struct thresh_restart tr
= {
366 b
->threshold_limit
= THRESHOLD_MAX
;
367 threshold_restart_bank(&tr
);
370 static int setup_APIC_mce_threshold(int reserved
, int new)
372 if (reserved
< 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR
,
373 APIC_EILVT_MSG_FIX
, 0))
379 static int setup_APIC_deferred_error(int reserved
, int new)
381 if (reserved
< 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR
,
382 APIC_EILVT_MSG_FIX
, 0))
388 static void deferred_error_interrupt_enable(struct cpuinfo_x86
*c
)
390 u32 low
= 0, high
= 0;
391 int def_offset
= -1, def_new
;
393 if (rdmsr_safe(MSR_CU_DEF_ERR
, &low
, &high
))
396 def_new
= (low
& MASK_DEF_LVTOFF
) >> 4;
397 if (!(low
& MASK_DEF_LVTOFF
)) {
398 pr_err(FW_BUG
"Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
399 def_new
= DEF_LVT_OFF
;
400 low
= (low
& ~MASK_DEF_LVTOFF
) | (DEF_LVT_OFF
<< 4);
403 def_offset
= setup_APIC_deferred_error(def_offset
, def_new
);
404 if ((def_offset
== def_new
) &&
405 (deferred_error_int_vector
!= amd_deferred_error_interrupt
))
406 deferred_error_int_vector
= amd_deferred_error_interrupt
;
408 low
= (low
& ~MASK_DEF_INT_TYPE
) | DEF_INT_TYPE_APIC
;
409 wrmsr(MSR_CU_DEF_ERR
, low
, high
);
412 static u32
get_block_address(unsigned int cpu
, u32 current_addr
, u32 low
, u32 high
,
413 unsigned int bank
, unsigned int block
)
415 u32 addr
= 0, offset
= 0;
417 if (mce_flags
.smca
) {
419 addr
= MSR_AMD64_SMCA_MCx_MISC(bank
);
422 * For SMCA enabled processors, BLKPTR field of the
423 * first MISC register (MCx_MISC0) indicates presence of
424 * additional MISC register set (MISC1-4).
428 if (rdmsr_safe_on_cpu(cpu
, MSR_AMD64_SMCA_MCx_CONFIG(bank
), &low
, &high
))
431 if (!(low
& MCI_CONFIG_MCAX
))
434 if (!rdmsr_safe_on_cpu(cpu
, MSR_AMD64_SMCA_MCx_MISC(bank
), &low
, &high
) &&
435 (low
& MASK_BLKPTR_LO
))
436 addr
= MSR_AMD64_SMCA_MCx_MISCy(bank
, block
- 1);
441 /* Fall back to method we used for older processors: */
444 addr
= msr_ops
.misc(bank
);
447 offset
= ((low
& MASK_BLKPTR_LO
) >> 21);
449 addr
= MCG_XBLK_ADDR
+ offset
;
452 addr
= ++current_addr
;
458 prepare_threshold_block(unsigned int bank
, unsigned int block
, u32 addr
,
459 int offset
, u32 misc_high
)
461 unsigned int cpu
= smp_processor_id();
462 u32 smca_low
, smca_high
;
463 struct threshold_block b
;
467 per_cpu(bank_map
, cpu
) |= (1 << bank
);
469 memset(&b
, 0, sizeof(b
));
474 b
.interrupt_capable
= lvt_interrupt_supported(bank
, misc_high
);
476 if (!b
.interrupt_capable
)
479 b
.interrupt_enable
= 1;
481 if (!mce_flags
.smca
) {
482 new = (misc_high
& MASK_LVTOFF_HI
) >> 20;
486 /* Gather LVT offset for thresholding: */
487 if (rdmsr_safe(MSR_CU_DEF_ERR
, &smca_low
, &smca_high
))
490 new = (smca_low
& SMCA_THR_LVT_OFF
) >> 12;
493 offset
= setup_APIC_mce_threshold(offset
, new);
495 if ((offset
== new) && (mce_threshold_vector
!= amd_threshold_interrupt
))
496 mce_threshold_vector
= amd_threshold_interrupt
;
499 mce_threshold_block_init(&b
, offset
);
505 /* cpu init entry point, called from mce.c with preempt off */
506 void mce_amd_feature_init(struct cpuinfo_x86
*c
)
508 u32 low
= 0, high
= 0, address
= 0;
509 unsigned int bank
, block
, cpu
= smp_processor_id();
512 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
514 smca_configure(bank
, cpu
);
516 for (block
= 0; block
< NR_BLOCKS
; ++block
) {
517 address
= get_block_address(cpu
, address
, low
, high
, bank
, block
);
521 if (rdmsr_safe(address
, &low
, &high
))
524 if (!(high
& MASK_VALID_HI
))
527 if (!(high
& MASK_CNTP_HI
) ||
528 (high
& MASK_LOCKED_HI
))
531 offset
= prepare_threshold_block(bank
, block
, address
, offset
, high
);
535 if (mce_flags
.succor
)
536 deferred_error_interrupt_enable(c
);
539 int umc_normaddr_to_sysaddr(u64 norm_addr
, u16 nid
, u8 umc
, u64
*sys_addr
)
541 u64 dram_base_addr
, dram_limit_addr
, dram_hole_base
;
542 /* We start from the normalized address */
543 u64 ret_addr
= norm_addr
;
547 u8 die_id_shift
, die_id_mask
, socket_id_shift
, socket_id_mask
;
548 u8 intlv_num_dies
, intlv_num_chan
, intlv_num_sockets
;
549 u8 intlv_addr_sel
, intlv_addr_bit
;
550 u8 num_intlv_bits
, hashed_bit
;
551 u8 lgcy_mmio_hole_en
, base
= 0;
552 u8 cs_mask
, cs_id
= 0;
553 bool hash_enabled
= false;
555 /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
556 if (amd_df_indirect_read(nid
, 0, 0x1B4, umc
, &tmp
))
559 /* Remove HiAddrOffset from normalized address, if enabled: */
561 u64 hi_addr_offset
= (tmp
& GENMASK_ULL(31, 20)) << 8;
563 if (norm_addr
>= hi_addr_offset
) {
564 ret_addr
-= hi_addr_offset
;
569 /* Read D18F0x110 (DramBaseAddress). */
570 if (amd_df_indirect_read(nid
, 0, 0x110 + (8 * base
), umc
, &tmp
))
573 /* Check if address range is valid. */
574 if (!(tmp
& BIT(0))) {
575 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
580 lgcy_mmio_hole_en
= tmp
& BIT(1);
581 intlv_num_chan
= (tmp
>> 4) & 0xF;
582 intlv_addr_sel
= (tmp
>> 8) & 0x7;
583 dram_base_addr
= (tmp
& GENMASK_ULL(31, 12)) << 16;
585 /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
586 if (intlv_addr_sel
> 3) {
587 pr_err("%s: Invalid interleave address select %d.\n",
588 __func__
, intlv_addr_sel
);
592 /* Read D18F0x114 (DramLimitAddress). */
593 if (amd_df_indirect_read(nid
, 0, 0x114 + (8 * base
), umc
, &tmp
))
596 intlv_num_sockets
= (tmp
>> 8) & 0x1;
597 intlv_num_dies
= (tmp
>> 10) & 0x3;
598 dram_limit_addr
= ((tmp
& GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
600 intlv_addr_bit
= intlv_addr_sel
+ 8;
602 /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
603 switch (intlv_num_chan
) {
604 case 0: intlv_num_chan
= 0; break;
605 case 1: intlv_num_chan
= 1; break;
606 case 3: intlv_num_chan
= 2; break;
607 case 5: intlv_num_chan
= 3; break;
608 case 7: intlv_num_chan
= 4; break;
610 case 8: intlv_num_chan
= 1;
614 pr_err("%s: Invalid number of interleaved channels %d.\n",
615 __func__
, intlv_num_chan
);
619 num_intlv_bits
= intlv_num_chan
;
621 if (intlv_num_dies
> 2) {
622 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
623 __func__
, intlv_num_dies
);
627 num_intlv_bits
+= intlv_num_dies
;
629 /* Add a bit if sockets are interleaved. */
630 num_intlv_bits
+= intlv_num_sockets
;
632 /* Assert num_intlv_bits <= 4 */
633 if (num_intlv_bits
> 4) {
634 pr_err("%s: Invalid interleave bits %d.\n",
635 __func__
, num_intlv_bits
);
639 if (num_intlv_bits
> 0) {
640 u64 temp_addr_x
, temp_addr_i
, temp_addr_y
;
641 u8 die_id_bit
, sock_id_bit
, cs_fabric_id
;
644 * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
645 * This is the fabric id for this coherent slave. Use
646 * umc/channel# as instance id of the coherent slave
649 if (amd_df_indirect_read(nid
, 0, 0x50, umc
, &tmp
))
652 cs_fabric_id
= (tmp
>> 8) & 0xFF;
655 /* If interleaved over more than 1 channel: */
656 if (intlv_num_chan
) {
657 die_id_bit
= intlv_num_chan
;
658 cs_mask
= (1 << die_id_bit
) - 1;
659 cs_id
= cs_fabric_id
& cs_mask
;
662 sock_id_bit
= die_id_bit
;
664 /* Read D18F1x208 (SystemFabricIdMask). */
665 if (intlv_num_dies
|| intlv_num_sockets
)
666 if (amd_df_indirect_read(nid
, 1, 0x208, umc
, &tmp
))
669 /* If interleaved over more than 1 die. */
670 if (intlv_num_dies
) {
671 sock_id_bit
= die_id_bit
+ intlv_num_dies
;
672 die_id_shift
= (tmp
>> 24) & 0xF;
673 die_id_mask
= (tmp
>> 8) & 0xFF;
675 cs_id
|= ((cs_fabric_id
& die_id_mask
) >> die_id_shift
) << die_id_bit
;
678 /* If interleaved over more than 1 socket. */
679 if (intlv_num_sockets
) {
680 socket_id_shift
= (tmp
>> 28) & 0xF;
681 socket_id_mask
= (tmp
>> 16) & 0xFF;
683 cs_id
|= ((cs_fabric_id
& socket_id_mask
) >> socket_id_shift
) << sock_id_bit
;
687 * The pre-interleaved address consists of XXXXXXIIIYYYYY
688 * where III is the ID for this CS, and XXXXXXYYYYY are the
689 * address bits from the post-interleaved address.
690 * "num_intlv_bits" has been calculated to tell us how many "I"
691 * bits there are. "intlv_addr_bit" tells us how many "Y" bits
692 * there are (where "I" starts).
694 temp_addr_y
= ret_addr
& GENMASK_ULL(intlv_addr_bit
-1, 0);
695 temp_addr_i
= (cs_id
<< intlv_addr_bit
);
696 temp_addr_x
= (ret_addr
& GENMASK_ULL(63, intlv_addr_bit
)) << num_intlv_bits
;
697 ret_addr
= temp_addr_x
| temp_addr_i
| temp_addr_y
;
700 /* Add dram base address */
701 ret_addr
+= dram_base_addr
;
703 /* If legacy MMIO hole enabled */
704 if (lgcy_mmio_hole_en
) {
705 if (amd_df_indirect_read(nid
, 0, 0x104, umc
, &tmp
))
708 dram_hole_base
= tmp
& GENMASK(31, 24);
709 if (ret_addr
>= dram_hole_base
)
710 ret_addr
+= (BIT_ULL(32) - dram_hole_base
);
714 /* Save some parentheses and grab ls-bit at the end. */
715 hashed_bit
= (ret_addr
>> 12) ^
721 hashed_bit
&= BIT(0);
723 if (hashed_bit
!= ((ret_addr
>> intlv_addr_bit
) & BIT(0)))
724 ret_addr
^= BIT(intlv_addr_bit
);
727 /* Is calculated system address is above DRAM limit address? */
728 if (ret_addr
> dram_limit_addr
)
731 *sys_addr
= ret_addr
;
737 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr
);
739 static void __log_error(unsigned int bank
, u64 status
, u64 addr
, u64 misc
)
750 if (m
.status
& MCI_STATUS_ADDRV
) {
754 * Extract [55:<lsb>] where lsb is the least significant
755 * *valid* bit of the address bits.
757 if (mce_flags
.smca
) {
758 u8 lsb
= (m
.addr
>> 56) & 0x3f;
760 m
.addr
&= GENMASK_ULL(55, lsb
);
764 if (mce_flags
.smca
) {
765 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank
), m
.ipid
);
767 if (m
.status
& MCI_STATUS_SYNDV
)
768 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank
), m
.synd
);
774 asmlinkage __visible
void __irq_entry
smp_deferred_error_interrupt(void)
777 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR
);
778 inc_irq_stat(irq_deferred_error_count
);
779 deferred_error_int_vector();
780 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR
);
785 * Returns true if the logged error is deferred. False, otherwise.
788 _log_error_bank(unsigned int bank
, u32 msr_stat
, u32 msr_addr
, u64 misc
)
790 u64 status
, addr
= 0;
792 rdmsrl(msr_stat
, status
);
793 if (!(status
& MCI_STATUS_VAL
))
796 if (status
& MCI_STATUS_ADDRV
)
797 rdmsrl(msr_addr
, addr
);
799 __log_error(bank
, status
, addr
, misc
);
803 return status
& MCI_STATUS_DEFERRED
;
807 * We have three scenarios for checking for Deferred errors:
809 * 1) Non-SMCA systems check MCA_STATUS and log error if found.
810 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
812 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
815 static void log_error_deferred(unsigned int bank
)
819 defrd
= _log_error_bank(bank
, msr_ops
.status(bank
),
820 msr_ops
.addr(bank
), 0);
825 /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
827 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank
), 0);
832 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
835 _log_error_bank(bank
, MSR_AMD64_SMCA_MCx_DESTAT(bank
),
836 MSR_AMD64_SMCA_MCx_DEADDR(bank
), 0);
839 /* APIC interrupt handler for deferred errors */
840 static void amd_deferred_error_interrupt(void)
844 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
)
845 log_error_deferred(bank
);
848 static void log_error_thresholding(unsigned int bank
, u64 misc
)
850 _log_error_bank(bank
, msr_ops
.status(bank
), msr_ops
.addr(bank
), misc
);
853 static void log_and_reset_block(struct threshold_block
*block
)
855 struct thresh_restart tr
;
856 u32 low
= 0, high
= 0;
861 if (rdmsr_safe(block
->address
, &low
, &high
))
864 if (!(high
& MASK_OVERFLOW_HI
))
867 /* Log the MCE which caused the threshold event. */
868 log_error_thresholding(block
->bank
, ((u64
)high
<< 32) | low
);
870 /* Reset threshold block after logging error. */
871 memset(&tr
, 0, sizeof(tr
));
873 threshold_restart_bank(&tr
);
877 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
878 * goes off when error_count reaches threshold_limit.
880 static void amd_threshold_interrupt(void)
882 struct threshold_block
*first_block
= NULL
, *block
= NULL
, *tmp
= NULL
;
883 unsigned int bank
, cpu
= smp_processor_id();
885 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
886 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
889 first_block
= per_cpu(threshold_banks
, cpu
)[bank
]->blocks
;
894 * The first block is also the head of the list. Check it first
895 * before iterating over the rest.
897 log_and_reset_block(first_block
);
898 list_for_each_entry_safe(block
, tmp
, &first_block
->miscj
, miscj
)
899 log_and_reset_block(block
);
907 struct threshold_attr
{
908 struct attribute attr
;
909 ssize_t (*show
) (struct threshold_block
*, char *);
910 ssize_t (*store
) (struct threshold_block
*, const char *, size_t count
);
913 #define SHOW_FIELDS(name) \
914 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
916 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
918 SHOW_FIELDS(interrupt_enable
)
919 SHOW_FIELDS(threshold_limit
)
922 store_interrupt_enable(struct threshold_block
*b
, const char *buf
, size_t size
)
924 struct thresh_restart tr
;
927 if (!b
->interrupt_capable
)
930 if (kstrtoul(buf
, 0, &new) < 0)
933 b
->interrupt_enable
= !!new;
935 memset(&tr
, 0, sizeof(tr
));
938 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
944 store_threshold_limit(struct threshold_block
*b
, const char *buf
, size_t size
)
946 struct thresh_restart tr
;
949 if (kstrtoul(buf
, 0, &new) < 0)
952 if (new > THRESHOLD_MAX
)
957 memset(&tr
, 0, sizeof(tr
));
958 tr
.old_limit
= b
->threshold_limit
;
959 b
->threshold_limit
= new;
962 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
967 static ssize_t
show_error_count(struct threshold_block
*b
, char *buf
)
971 rdmsr_on_cpu(b
->cpu
, b
->address
, &lo
, &hi
);
973 return sprintf(buf
, "%u\n", ((hi
& THRESHOLD_MAX
) -
974 (THRESHOLD_MAX
- b
->threshold_limit
)));
977 static struct threshold_attr error_count
= {
978 .attr
= {.name
= __stringify(error_count
), .mode
= 0444 },
979 .show
= show_error_count
,
982 #define RW_ATTR(val) \
983 static struct threshold_attr val = { \
984 .attr = {.name = __stringify(val), .mode = 0644 }, \
985 .show = show_## val, \
986 .store = store_## val, \
989 RW_ATTR(interrupt_enable
);
990 RW_ATTR(threshold_limit
);
992 static struct attribute
*default_attrs
[] = {
993 &threshold_limit
.attr
,
995 NULL
, /* possibly interrupt_enable if supported, see below */
999 #define to_block(k) container_of(k, struct threshold_block, kobj)
1000 #define to_attr(a) container_of(a, struct threshold_attr, attr)
1002 static ssize_t
show(struct kobject
*kobj
, struct attribute
*attr
, char *buf
)
1004 struct threshold_block
*b
= to_block(kobj
);
1005 struct threshold_attr
*a
= to_attr(attr
);
1008 ret
= a
->show
? a
->show(b
, buf
) : -EIO
;
1013 static ssize_t
store(struct kobject
*kobj
, struct attribute
*attr
,
1014 const char *buf
, size_t count
)
1016 struct threshold_block
*b
= to_block(kobj
);
1017 struct threshold_attr
*a
= to_attr(attr
);
1020 ret
= a
->store
? a
->store(b
, buf
, count
) : -EIO
;
1025 static const struct sysfs_ops threshold_ops
= {
1030 static struct kobj_type threshold_ktype
= {
1031 .sysfs_ops
= &threshold_ops
,
1032 .default_attrs
= default_attrs
,
1035 static const char *get_name(unsigned int bank
, struct threshold_block
*b
)
1037 unsigned int bank_type
;
1039 if (!mce_flags
.smca
) {
1041 return bank4_names(b
);
1043 return th_names
[bank
];
1046 if (!smca_banks
[bank
].hwid
)
1049 bank_type
= smca_banks
[bank
].hwid
->bank_type
;
1051 if (b
&& bank_type
== SMCA_UMC
) {
1052 if (b
->block
< ARRAY_SIZE(smca_umc_block_names
))
1053 return smca_umc_block_names
[b
->block
];
1057 if (smca_banks
[bank
].hwid
->count
== 1)
1058 return smca_get_name(bank_type
);
1060 snprintf(buf_mcatype
, MAX_MCATYPE_NAME_LEN
,
1061 "%s_%x", smca_get_name(bank_type
),
1062 smca_banks
[bank
].sysfs_id
);
1066 static int allocate_threshold_blocks(unsigned int cpu
, unsigned int bank
,
1067 unsigned int block
, u32 address
)
1069 struct threshold_block
*b
= NULL
;
1073 if ((bank
>= mca_cfg
.banks
) || (block
>= NR_BLOCKS
))
1076 if (rdmsr_safe_on_cpu(cpu
, address
, &low
, &high
))
1079 if (!(high
& MASK_VALID_HI
)) {
1086 if (!(high
& MASK_CNTP_HI
) ||
1087 (high
& MASK_LOCKED_HI
))
1090 b
= kzalloc(sizeof(struct threshold_block
), GFP_KERNEL
);
1097 b
->address
= address
;
1098 b
->interrupt_enable
= 0;
1099 b
->interrupt_capable
= lvt_interrupt_supported(bank
, high
);
1100 b
->threshold_limit
= THRESHOLD_MAX
;
1102 if (b
->interrupt_capable
) {
1103 threshold_ktype
.default_attrs
[2] = &interrupt_enable
.attr
;
1104 b
->interrupt_enable
= 1;
1106 threshold_ktype
.default_attrs
[2] = NULL
;
1109 INIT_LIST_HEAD(&b
->miscj
);
1111 if (per_cpu(threshold_banks
, cpu
)[bank
]->blocks
) {
1113 &per_cpu(threshold_banks
, cpu
)[bank
]->blocks
->miscj
);
1115 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= b
;
1118 err
= kobject_init_and_add(&b
->kobj
, &threshold_ktype
,
1119 per_cpu(threshold_banks
, cpu
)[bank
]->kobj
,
1124 address
= get_block_address(cpu
, address
, low
, high
, bank
, ++block
);
1128 err
= allocate_threshold_blocks(cpu
, bank
, block
, address
);
1133 kobject_uevent(&b
->kobj
, KOBJ_ADD
);
1139 kobject_put(&b
->kobj
);
1140 list_del(&b
->miscj
);
1146 static int __threshold_add_blocks(struct threshold_bank
*b
)
1148 struct list_head
*head
= &b
->blocks
->miscj
;
1149 struct threshold_block
*pos
= NULL
;
1150 struct threshold_block
*tmp
= NULL
;
1153 err
= kobject_add(&b
->blocks
->kobj
, b
->kobj
, b
->blocks
->kobj
.name
);
1157 list_for_each_entry_safe(pos
, tmp
, head
, miscj
) {
1159 err
= kobject_add(&pos
->kobj
, b
->kobj
, pos
->kobj
.name
);
1161 list_for_each_entry_safe_reverse(pos
, tmp
, head
, miscj
)
1162 kobject_del(&pos
->kobj
);
1170 static int threshold_create_bank(unsigned int cpu
, unsigned int bank
)
1172 struct device
*dev
= per_cpu(mce_device
, cpu
);
1173 struct amd_northbridge
*nb
= NULL
;
1174 struct threshold_bank
*b
= NULL
;
1175 const char *name
= get_name(bank
, NULL
);
1181 if (is_shared_bank(bank
)) {
1182 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
1184 /* threshold descriptor already initialized on this node? */
1185 if (nb
&& nb
->bank4
) {
1188 err
= kobject_add(b
->kobj
, &dev
->kobj
, name
);
1192 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
1193 refcount_inc(&b
->cpus
);
1195 err
= __threshold_add_blocks(b
);
1201 b
= kzalloc(sizeof(struct threshold_bank
), GFP_KERNEL
);
1207 b
->kobj
= kobject_create_and_add(name
, &dev
->kobj
);
1213 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
1215 if (is_shared_bank(bank
)) {
1216 refcount_set(&b
->cpus
, 1);
1218 /* nb is already initialized, see above */
1225 err
= allocate_threshold_blocks(cpu
, bank
, 0, msr_ops
.misc(bank
));
1236 static void deallocate_threshold_block(unsigned int cpu
,
1239 struct threshold_block
*pos
= NULL
;
1240 struct threshold_block
*tmp
= NULL
;
1241 struct threshold_bank
*head
= per_cpu(threshold_banks
, cpu
)[bank
];
1246 list_for_each_entry_safe(pos
, tmp
, &head
->blocks
->miscj
, miscj
) {
1247 kobject_put(&pos
->kobj
);
1248 list_del(&pos
->miscj
);
1252 kfree(per_cpu(threshold_banks
, cpu
)[bank
]->blocks
);
1253 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= NULL
;
1256 static void __threshold_remove_blocks(struct threshold_bank
*b
)
1258 struct threshold_block
*pos
= NULL
;
1259 struct threshold_block
*tmp
= NULL
;
1261 kobject_del(b
->kobj
);
1263 list_for_each_entry_safe(pos
, tmp
, &b
->blocks
->miscj
, miscj
)
1264 kobject_del(&pos
->kobj
);
1267 static void threshold_remove_bank(unsigned int cpu
, int bank
)
1269 struct amd_northbridge
*nb
;
1270 struct threshold_bank
*b
;
1272 b
= per_cpu(threshold_banks
, cpu
)[bank
];
1279 if (is_shared_bank(bank
)) {
1280 if (!refcount_dec_and_test(&b
->cpus
)) {
1281 __threshold_remove_blocks(b
);
1282 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
1286 * the last CPU on this node using the shared bank is
1287 * going away, remove that bank now.
1289 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
1294 deallocate_threshold_block(cpu
, bank
);
1297 kobject_del(b
->kobj
);
1298 kobject_put(b
->kobj
);
1300 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
1303 int mce_threshold_remove_device(unsigned int cpu
)
1307 if (!thresholding_en
)
1310 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
1311 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
1313 threshold_remove_bank(cpu
, bank
);
1315 kfree(per_cpu(threshold_banks
, cpu
));
1316 per_cpu(threshold_banks
, cpu
) = NULL
;
1320 /* create dir/files for all valid threshold banks */
1321 int mce_threshold_create_device(unsigned int cpu
)
1324 struct threshold_bank
**bp
;
1327 if (!thresholding_en
)
1330 bp
= per_cpu(threshold_banks
, cpu
);
1334 bp
= kzalloc(sizeof(struct threshold_bank
*) * mca_cfg
.banks
,
1339 per_cpu(threshold_banks
, cpu
) = bp
;
1341 for (bank
= 0; bank
< mca_cfg
.banks
; ++bank
) {
1342 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
1344 err
= threshold_create_bank(cpu
, bank
);
1350 mce_threshold_remove_device(cpu
);
1354 static __init
int threshold_init_device(void)
1358 if (mce_threshold_vector
== amd_threshold_interrupt
)
1359 thresholding_en
= true;
1361 /* to hit CPUs online before the notifier is up */
1362 for_each_online_cpu(lcpu
) {
1363 int err
= mce_threshold_create_device(lcpu
);
1372 * there are 3 funcs which need to be _initcalled in a logic sequence:
1373 * 1. xen_late_init_mcelog
1374 * 2. mcheck_init_device
1375 * 3. threshold_init_device
1377 * xen_late_init_mcelog must register xen_mce_chrdev_device before
1378 * native mce_chrdev_device registration if running under xen platform;
1380 * mcheck_init_device should be inited before threshold_init_device to
1381 * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1383 * so we use following _initcalls
1384 * 1. device_initcall(xen_late_init_mcelog);
1385 * 2. device_initcall_sync(mcheck_init_device);
1386 * 3. late_initcall(threshold_init_device);
1388 * when running under xen, the initcall order is 1,2,3;
1389 * on baremetal, we skip 1 and we do only 2 and 3.
1391 late_initcall(threshold_init_device
);