2 * Intel specific MCE features.
3 * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
4 * Copyright (C) 2008, 2009 Intel Corporation
9 #include <linux/interrupt.h>
10 #include <linux/percpu.h>
11 #include <linux/sched.h>
12 #include <linux/cpumask.h>
14 #include <asm/processor.h>
18 #include "mce-internal.h"
21 * Support for Intel Correct Machine Check Interrupts. This allows
22 * the CPU to raise an interrupt when a corrected machine check happened.
23 * Normally we pick those up using a regular polling timer.
24 * Also supports reliable discovery of shared banks.
28 * CMCI can be delivered to multiple cpus that share a machine check bank
29 * so we need to designate a single cpu to process errors logged in each bank
30 * in the interrupt handler (otherwise we would have many races and potential
31 * double reporting of the same error).
32 * Note that this can change when a cpu is offlined or brought online since
33 * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
34 * disables CMCI on all banks owned by the cpu and clears this bitfield. At
35 * this point, cmci_rediscover() kicks in and a different cpu may end up
36 * taking ownership of some of the shared MCA banks that were previously
37 * owned by the offlined cpu.
39 static DEFINE_PER_CPU(mce_banks_t
, mce_banks_owned
);
42 * CMCI storm detection backoff counter
44 * During storm, we reset this counter to INITIAL_CHECK_INTERVAL in case we've
45 * encountered an error. If not, we decrement it by one. We signal the end of
46 * the CMCI storm when it reaches 0.
48 static DEFINE_PER_CPU(int, cmci_backoff_cnt
);
51 * cmci_discover_lock protects against parallel discovery attempts
52 * which could race against each other.
54 static DEFINE_RAW_SPINLOCK(cmci_discover_lock
);
56 #define CMCI_THRESHOLD 1
57 #define CMCI_POLL_INTERVAL (30 * HZ)
58 #define CMCI_STORM_INTERVAL (HZ)
59 #define CMCI_STORM_THRESHOLD 15
61 static DEFINE_PER_CPU(unsigned long, cmci_time_stamp
);
62 static DEFINE_PER_CPU(unsigned int, cmci_storm_cnt
);
63 static DEFINE_PER_CPU(unsigned int, cmci_storm_state
);
71 static atomic_t cmci_storm_on_cpus
;
73 static int cmci_supported(int *banks
)
77 if (mca_cfg
.cmci_disabled
|| mca_cfg
.ignore_ce
)
81 * Vendor check is not strictly needed, but the initial
82 * initialization is vendor keyed and this
83 * makes sure none of the backdoors are entered otherwise.
85 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
87 if (!cpu_has_apic
|| lapic_get_maxlvt() < 6)
89 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
90 *banks
= min_t(unsigned, MAX_NR_BANKS
, cap
& 0xff);
91 return !!(cap
& MCG_CMCI_P
);
94 bool mce_intel_cmci_poll(void)
96 if (__this_cpu_read(cmci_storm_state
) == CMCI_STORM_NONE
)
100 * Reset the counter if we've logged an error in the last poll
103 if (machine_check_poll(MCP_TIMESTAMP
, this_cpu_ptr(&mce_banks_owned
)))
104 this_cpu_write(cmci_backoff_cnt
, INITIAL_CHECK_INTERVAL
);
106 this_cpu_dec(cmci_backoff_cnt
);
111 void mce_intel_hcpu_update(unsigned long cpu
)
113 if (per_cpu(cmci_storm_state
, cpu
) == CMCI_STORM_ACTIVE
)
114 atomic_dec(&cmci_storm_on_cpus
);
116 per_cpu(cmci_storm_state
, cpu
) = CMCI_STORM_NONE
;
119 unsigned long cmci_intel_adjust_timer(unsigned long interval
)
121 if ((this_cpu_read(cmci_backoff_cnt
) > 0) &&
122 (__this_cpu_read(cmci_storm_state
) == CMCI_STORM_ACTIVE
)) {
124 return CMCI_STORM_INTERVAL
;
127 switch (__this_cpu_read(cmci_storm_state
)) {
128 case CMCI_STORM_ACTIVE
:
131 * We switch back to interrupt mode once the poll timer has
132 * silenced itself. That means no events recorded and the timer
133 * interval is back to our poll interval.
135 __this_cpu_write(cmci_storm_state
, CMCI_STORM_SUBSIDED
);
136 if (!atomic_sub_return(1, &cmci_storm_on_cpus
))
137 pr_notice("CMCI storm subsided: switching to interrupt mode\n");
141 case CMCI_STORM_SUBSIDED
:
143 * We wait for all CPUs to go back to SUBSIDED state. When that
144 * happens we switch back to interrupt mode.
146 if (!atomic_read(&cmci_storm_on_cpus
)) {
147 __this_cpu_write(cmci_storm_state
, CMCI_STORM_NONE
);
151 return CMCI_POLL_INTERVAL
;
154 /* We have shiny weather. Let the poll do whatever it thinks. */
159 static void cmci_storm_disable_banks(void)
161 unsigned long flags
, *owned
;
165 raw_spin_lock_irqsave(&cmci_discover_lock
, flags
);
166 owned
= this_cpu_ptr(mce_banks_owned
);
167 for_each_set_bit(bank
, owned
, MAX_NR_BANKS
) {
168 rdmsrl(MSR_IA32_MCx_CTL2(bank
), val
);
169 val
&= ~MCI_CTL2_CMCI_EN
;
170 wrmsrl(MSR_IA32_MCx_CTL2(bank
), val
);
172 raw_spin_unlock_irqrestore(&cmci_discover_lock
, flags
);
175 static bool cmci_storm_detect(void)
177 unsigned int cnt
= __this_cpu_read(cmci_storm_cnt
);
178 unsigned long ts
= __this_cpu_read(cmci_time_stamp
);
179 unsigned long now
= jiffies
;
182 if (__this_cpu_read(cmci_storm_state
) != CMCI_STORM_NONE
)
185 if (time_before_eq(now
, ts
+ CMCI_STORM_INTERVAL
)) {
189 __this_cpu_write(cmci_time_stamp
, now
);
191 __this_cpu_write(cmci_storm_cnt
, cnt
);
193 if (cnt
<= CMCI_STORM_THRESHOLD
)
196 cmci_storm_disable_banks();
197 __this_cpu_write(cmci_storm_state
, CMCI_STORM_ACTIVE
);
198 r
= atomic_add_return(1, &cmci_storm_on_cpus
);
199 mce_timer_kick(CMCI_STORM_INTERVAL
);
200 this_cpu_write(cmci_backoff_cnt
, INITIAL_CHECK_INTERVAL
);
203 pr_notice("CMCI storm detected: switching to poll mode\n");
208 * The interrupt handler. This is called on every event.
209 * Just call the poller directly to log any events.
210 * This could in theory increase the threshold under high load,
211 * but doesn't for now.
213 static void intel_threshold_interrupt(void)
215 if (cmci_storm_detect())
218 machine_check_poll(MCP_TIMESTAMP
, this_cpu_ptr(&mce_banks_owned
));
223 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
224 * on this CPU. Use the algorithm recommended in the SDM to discover shared
227 static void cmci_discover(int banks
)
229 unsigned long *owned
= (void *)this_cpu_ptr(&mce_banks_owned
);
232 int bios_wrong_thresh
= 0;
234 raw_spin_lock_irqsave(&cmci_discover_lock
, flags
);
235 for (i
= 0; i
< banks
; i
++) {
237 int bios_zero_thresh
= 0;
239 if (test_bit(i
, owned
))
242 /* Skip banks in firmware first mode */
243 if (test_bit(i
, mce_banks_ce_disabled
))
246 rdmsrl(MSR_IA32_MCx_CTL2(i
), val
);
248 /* Already owned by someone else? */
249 if (val
& MCI_CTL2_CMCI_EN
) {
251 __clear_bit(i
, this_cpu_ptr(mce_poll_banks
));
255 if (!mca_cfg
.bios_cmci_threshold
) {
256 val
&= ~MCI_CTL2_CMCI_THRESHOLD_MASK
;
257 val
|= CMCI_THRESHOLD
;
258 } else if (!(val
& MCI_CTL2_CMCI_THRESHOLD_MASK
)) {
260 * If bios_cmci_threshold boot option was specified
261 * but the threshold is zero, we'll try to initialize
264 bios_zero_thresh
= 1;
265 val
|= CMCI_THRESHOLD
;
268 val
|= MCI_CTL2_CMCI_EN
;
269 wrmsrl(MSR_IA32_MCx_CTL2(i
), val
);
270 rdmsrl(MSR_IA32_MCx_CTL2(i
), val
);
272 /* Did the enable bit stick? -- the bank supports CMCI */
273 if (val
& MCI_CTL2_CMCI_EN
) {
275 __clear_bit(i
, this_cpu_ptr(mce_poll_banks
));
277 * We are able to set thresholds for some banks that
278 * had a threshold of 0. This means the BIOS has not
279 * set the thresholds properly or does not work with
280 * this boot option. Note down now and report later.
282 if (mca_cfg
.bios_cmci_threshold
&& bios_zero_thresh
&&
283 (val
& MCI_CTL2_CMCI_THRESHOLD_MASK
))
284 bios_wrong_thresh
= 1;
286 WARN_ON(!test_bit(i
, this_cpu_ptr(mce_poll_banks
)));
289 raw_spin_unlock_irqrestore(&cmci_discover_lock
, flags
);
290 if (mca_cfg
.bios_cmci_threshold
&& bios_wrong_thresh
) {
292 "bios_cmci_threshold: Some banks do not have valid thresholds set\n");
294 "bios_cmci_threshold: Make sure your BIOS supports this boot option\n");
299 * Just in case we missed an event during initialization check
300 * all the CMCI owned banks.
302 void cmci_recheck(void)
307 if (!mce_available(raw_cpu_ptr(&cpu_info
)) || !cmci_supported(&banks
))
310 local_irq_save(flags
);
311 machine_check_poll(MCP_TIMESTAMP
, this_cpu_ptr(&mce_banks_owned
));
312 local_irq_restore(flags
);
315 /* Caller must hold the lock on cmci_discover_lock */
316 static void __cmci_disable_bank(int bank
)
320 if (!test_bit(bank
, this_cpu_ptr(mce_banks_owned
)))
322 rdmsrl(MSR_IA32_MCx_CTL2(bank
), val
);
323 val
&= ~MCI_CTL2_CMCI_EN
;
324 wrmsrl(MSR_IA32_MCx_CTL2(bank
), val
);
325 __clear_bit(bank
, this_cpu_ptr(mce_banks_owned
));
329 * Disable CMCI on this CPU for all banks it owns when it goes down.
330 * This allows other CPUs to claim the banks on rediscovery.
332 void cmci_clear(void)
338 if (!cmci_supported(&banks
))
340 raw_spin_lock_irqsave(&cmci_discover_lock
, flags
);
341 for (i
= 0; i
< banks
; i
++)
342 __cmci_disable_bank(i
);
343 raw_spin_unlock_irqrestore(&cmci_discover_lock
, flags
);
346 static void cmci_rediscover_work_func(void *arg
)
350 /* Recheck banks in case CPUs don't all have the same */
351 if (cmci_supported(&banks
))
352 cmci_discover(banks
);
355 /* After a CPU went down cycle through all the others and rediscover */
356 void cmci_rediscover(void)
360 if (!cmci_supported(&banks
))
363 on_each_cpu(cmci_rediscover_work_func
, NULL
, 1);
367 * Reenable CMCI on this CPU in case a CPU down failed.
369 void cmci_reenable(void)
372 if (cmci_supported(&banks
))
373 cmci_discover(banks
);
376 void cmci_disable_bank(int bank
)
381 if (!cmci_supported(&banks
))
384 raw_spin_lock_irqsave(&cmci_discover_lock
, flags
);
385 __cmci_disable_bank(bank
);
386 raw_spin_unlock_irqrestore(&cmci_discover_lock
, flags
);
389 static void intel_init_cmci(void)
393 if (!cmci_supported(&banks
))
396 mce_threshold_vector
= intel_threshold_interrupt
;
397 cmci_discover(banks
);
399 * For CPU #0 this runs with still disabled APIC, but that's
400 * ok because only the vector is set up. We still do another
401 * check for the banks later for CPU #0 just to make sure
402 * to not miss any events.
404 apic_write(APIC_LVTCMCI
, THRESHOLD_APIC_VECTOR
|APIC_DM_FIXED
);
408 void mce_intel_feature_init(struct cpuinfo_x86
*c
)
410 intel_init_thermal(c
);