arch/x86/kernel/cpu/mcheck/therm_throt.c

   1 /*
   2  * Thermal throttle event support code (such as syslog messaging and rate
   3  * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
   4  *
   5  * This allows consistent reporting of CPU thermal throttle events.
   6  *
   7  * Maintains a counter in /sys that keeps track of the number of thermal
   8  * events, such that the user knows how bad the thermal problem might be
   9  * (since the logging to syslog is rate limited).
  10  *
  11  * Author: Dmitriy Zavin (dmitriyz@google.com)
  12  *
  13  * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
  14  *          Inspired by Ross Biro's and Al Borchers' counter code.
  15  */
  16 #include <linux/interrupt.h>
  17 #include <linux/notifier.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/kernel.h>
  20 #include <linux/percpu.h>
  21 #include <linux/export.h>
  22 #include <linux/types.h>
  23 #include <linux/init.h>
  24 #include <linux/smp.h>
  25 #include <linux/cpu.h>
  26
  27 #include <asm/processor.h>
  28 #include <asm/apic.h>
  29 #include <asm/mce.h>
  30 #include <asm/msr.h>
  31 #include <asm/trace/irq_vectors.h>
  32
  33 /* How long to wait between reporting thermal events */
  34 #define CHECK_INTERVAL          (300 * HZ)
  35
  36 #define THERMAL_THROTTLING_EVENT        0
  37 #define POWER_LIMIT_EVENT               1
  38
  39 /*
  40  * Current thermal event state:
  41  */
  42 struct _thermal_state {
  43         bool                    new_event;
  44         int                     event;
  45         u64                     next_check;
  46         unsigned long           count;
  47         unsigned long           last_count;
  48 };
  49
  50 struct thermal_state {
  51         struct _thermal_state core_throttle;
  52         struct _thermal_state core_power_limit;
  53         struct _thermal_state package_throttle;
  54         struct _thermal_state package_power_limit;
  55         struct _thermal_state core_thresh0;
  56         struct _thermal_state core_thresh1;
  57         struct _thermal_state pkg_thresh0;
  58         struct _thermal_state pkg_thresh1;
  59 };
  60
  61 /* Callback to handle core threshold interrupts */
  62 int (*platform_thermal_notify)(__u64 msr_val);
  63 EXPORT_SYMBOL(platform_thermal_notify);
  64
  65 /* Callback to handle core package threshold_interrupts */
  66 int (*platform_thermal_package_notify)(__u64 msr_val);
  67 EXPORT_SYMBOL_GPL(platform_thermal_package_notify);
  68
  69 /* Callback support of rate control, return true, if
  70  * callback has rate control */
  71 bool (*platform_thermal_package_rate_control)(void);
  72 EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control);
  73
  74
  75 static DEFINE_PER_CPU(struct thermal_state, thermal_state);
  76
  77 static atomic_t therm_throt_en  = ATOMIC_INIT(0);
  78
  79 static u32 lvtthmr_init __read_mostly;
  80
  81 #ifdef CONFIG_SYSFS
  82 #define define_therm_throt_device_one_ro(_name)                         \
  83         static DEVICE_ATTR(_name, 0444,                                 \
  84                            therm_throt_device_show_##_name,             \
  85                                    NULL)                                \
  86
  87 #define define_therm_throt_device_show_func(event, name)                \
  88                                                                         \
  89 static ssize_t therm_throt_device_show_##event##_##name(                \
  90                         struct device *dev,                             \
  91                         struct device_attribute *attr,                  \
  92                         char *buf)                                      \
  93 {                                                                       \
  94         unsigned int cpu = dev->id;                                     \
  95         ssize_t ret;                                                    \
  96                                                                         \
  97         preempt_disable();      /* CPU hotplug */                       \
  98         if (cpu_online(cpu)) {                                          \
  99                 ret = sprintf(buf, "%lu\n",                             \
 100                               per_cpu(thermal_state, cpu).event.name);  \
 101         } else                                                          \
 102                 ret = 0;                                                \
 103         preempt_enable();                                               \
 104                                                                         \
 105         return ret;                                                     \
 106 }
 107
 108 define_therm_throt_device_show_func(core_throttle, count);
 109 define_therm_throt_device_one_ro(core_throttle_count);
 110
 111 define_therm_throt_device_show_func(core_power_limit, count);
 112 define_therm_throt_device_one_ro(core_power_limit_count);
 113
 114 define_therm_throt_device_show_func(package_throttle, count);
 115 define_therm_throt_device_one_ro(package_throttle_count);
 116
 117 define_therm_throt_device_show_func(package_power_limit, count);
 118 define_therm_throt_device_one_ro(package_power_limit_count);
 119
 120 static struct attribute *thermal_throttle_attrs[] = {
 121         &dev_attr_core_throttle_count.attr,
 122         NULL
 123 };
 124
 125 static struct attribute_group thermal_attr_group = {
 126         .attrs  = thermal_throttle_attrs,
 127         .name   = "thermal_throttle"
 128 };
 129 #endif /* CONFIG_SYSFS */
 130
 131 #define CORE_LEVEL      0
 132 #define PACKAGE_LEVEL   1
 133
 134 /***
 135  * therm_throt_process - Process thermal throttling event from interrupt
 136  * @curr: Whether the condition is current or not (boolean), since the
 137  *        thermal interrupt normally gets called both when the thermal
 138  *        event begins and once the event has ended.
 139  *
 140  * This function is called by the thermal interrupt after the
 141  * IRQ has been acknowledged.
 142  *
 143  * It will take care of rate limiting and printing messages to the syslog.
 144  */
 145 static void therm_throt_process(bool new_event, int event, int level)
 146 {
 147         struct _thermal_state *state;
 148         unsigned int this_cpu = smp_processor_id();
 149         bool old_event;
 150         u64 now;
 151         struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
 152
 153         now = get_jiffies_64();
 154         if (level == CORE_LEVEL) {
 155                 if (event == THERMAL_THROTTLING_EVENT)
 156                         state = &pstate->core_throttle;
 157                 else if (event == POWER_LIMIT_EVENT)
 158                         state = &pstate->core_power_limit;
 159                 else
 160                         return;
 161         } else if (level == PACKAGE_LEVEL) {
 162                 if (event == THERMAL_THROTTLING_EVENT)
 163                         state = &pstate->package_throttle;
 164                 else if (event == POWER_LIMIT_EVENT)
 165                         state = &pstate->package_power_limit;
 166                 else
 167                         return;
 168         } else
 169                 return;
 170
 171         old_event = state->new_event;
 172         state->new_event = new_event;
 173
 174         if (new_event)
 175                 state->count++;
 176
 177         if (time_before64(now, state->next_check) &&
 178                         state->count != state->last_count)
 179                 return;
 180
 181         state->next_check = now + CHECK_INTERVAL;
 182         state->last_count = state->count;
 183
 184         /* if we just entered the thermal event */
 185         if (new_event) {
 186                 if (event == THERMAL_THROTTLING_EVENT)
 187                         pr_crit("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
 188                                 this_cpu,
 189                                 level == CORE_LEVEL ? "Core" : "Package",
 190                                 state->count);
 191                 return;
 192         }
 193         if (old_event) {
 194                 if (event == THERMAL_THROTTLING_EVENT)
 195                         pr_info("CPU%d: %s temperature/speed normal\n", this_cpu,
 196                                 level == CORE_LEVEL ? "Core" : "Package");
 197                 return;
 198         }
 199 }
 200
 201 static int thresh_event_valid(int level, int event)
 202 {
 203         struct _thermal_state *state;
 204         unsigned int this_cpu = smp_processor_id();
 205         struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
 206         u64 now = get_jiffies_64();
 207
 208         if (level == PACKAGE_LEVEL)
 209                 state = (event == 0) ? &pstate->pkg_thresh0 :
 210                                                 &pstate->pkg_thresh1;
 211         else
 212                 state = (event == 0) ? &pstate->core_thresh0 :
 213                                                 &pstate->core_thresh1;
 214
 215         if (time_before64(now, state->next_check))
 216                 return 0;
 217
 218         state->next_check = now + CHECK_INTERVAL;
 219
 220         return 1;
 221 }
 222
 223 static bool int_pln_enable;
 224 static int __init int_pln_enable_setup(char *s)
 225 {
 226         int_pln_enable = true;
 227
 228         return 1;
 229 }
 230 __setup("int_pln_enable", int_pln_enable_setup);
 231
 232 #ifdef CONFIG_SYSFS
 233 /* Add/Remove thermal_throttle interface for CPU device: */
 234 static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu)
 235 {
 236         int err;
 237         struct cpuinfo_x86 *c = &cpu_data(cpu);
 238
 239         err = sysfs_create_group(&dev->kobj, &thermal_attr_group);
 240         if (err)
 241                 return err;
 242
 243         if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
 244                 err = sysfs_add_file_to_group(&dev->kobj,
 245                                               &dev_attr_core_power_limit_count.attr,
 246                                               thermal_attr_group.name);
 247         if (cpu_has(c, X86_FEATURE_PTS)) {
 248                 err = sysfs_add_file_to_group(&dev->kobj,
 249                                               &dev_attr_package_throttle_count.attr,
 250                                               thermal_attr_group.name);
 251                 if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
 252                         err = sysfs_add_file_to_group(&dev->kobj,
 253                                         &dev_attr_package_power_limit_count.attr,
 254                                         thermal_attr_group.name);
 255         }
 256
 257         return err;
 258 }
 259
 260 static void thermal_throttle_remove_dev(struct device *dev)
 261 {
 262         sysfs_remove_group(&dev->kobj, &thermal_attr_group);
 263 }
 264
 265 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
 266 static int thermal_throttle_online(unsigned int cpu)
 267 {
 268         struct device *dev = get_cpu_device(cpu);
 269
 270         return thermal_throttle_add_dev(dev, cpu);
 271 }
 272
 273 static int thermal_throttle_offline(unsigned int cpu)
 274 {
 275         struct device *dev = get_cpu_device(cpu);
 276
 277         thermal_throttle_remove_dev(dev);
 278         return 0;
 279 }
 280
 281 static __init int thermal_throttle_init_device(void)
 282 {
 283         int ret;
 284
 285         if (!atomic_read(&therm_throt_en))
 286                 return 0;
 287
 288         ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/therm:online",
 289                                 thermal_throttle_online,
 290                                 thermal_throttle_offline);
 291         return ret < 0 ? ret : 0;
 292 }
 293 device_initcall(thermal_throttle_init_device);
 294
 295 #endif /* CONFIG_SYSFS */
 296
 297 static void notify_package_thresholds(__u64 msr_val)
 298 {
 299         bool notify_thres_0 = false;
 300         bool notify_thres_1 = false;
 301
 302         if (!platform_thermal_package_notify)
 303                 return;
 304
 305         /* lower threshold check */
 306         if (msr_val & THERM_LOG_THRESHOLD0)
 307                 notify_thres_0 = true;
 308         /* higher threshold check */
 309         if (msr_val & THERM_LOG_THRESHOLD1)
 310                 notify_thres_1 = true;
 311
 312         if (!notify_thres_0 && !notify_thres_1)
 313                 return;
 314
 315         if (platform_thermal_package_rate_control &&
 316                 platform_thermal_package_rate_control()) {
 317                 /* Rate control is implemented in callback */
 318                 platform_thermal_package_notify(msr_val);
 319                 return;
 320         }
 321
 322         /* lower threshold reached */
 323         if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0))
 324                 platform_thermal_package_notify(msr_val);
 325         /* higher threshold reached */
 326         if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1))
 327                 platform_thermal_package_notify(msr_val);
 328 }
 329
 330 static void notify_thresholds(__u64 msr_val)
 331 {
 332         /* check whether the interrupt handler is defined;
 333          * otherwise simply return
 334          */
 335         if (!platform_thermal_notify)
 336                 return;
 337
 338         /* lower threshold reached */
 339         if ((msr_val & THERM_LOG_THRESHOLD0) &&
 340                         thresh_event_valid(CORE_LEVEL, 0))
 341                 platform_thermal_notify(msr_val);
 342         /* higher threshold reached */
 343         if ((msr_val & THERM_LOG_THRESHOLD1) &&
 344                         thresh_event_valid(CORE_LEVEL, 1))
 345                 platform_thermal_notify(msr_val);
 346 }
 347
 348 /* Thermal transition interrupt handler */
 349 static void intel_thermal_interrupt(void)
 350 {
 351         __u64 msr_val;
 352
 353         if (static_cpu_has(X86_FEATURE_HWP))
 354                 wrmsrl_safe(MSR_HWP_STATUS, 0);
 355
 356         rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
 357
 358         /* Check for violation of core thermal thresholds*/
 359         notify_thresholds(msr_val);
 360
 361         therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
 362                             THERMAL_THROTTLING_EVENT,
 363                             CORE_LEVEL);
 364
 365         if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
 366                 therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
 367                                         POWER_LIMIT_EVENT,
 368                                         CORE_LEVEL);
 369
 370         if (this_cpu_has(X86_FEATURE_PTS)) {
 371                 rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
 372                 /* check violations of package thermal thresholds */
 373                 notify_package_thresholds(msr_val);
 374                 therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
 375                                         THERMAL_THROTTLING_EVENT,
 376                                         PACKAGE_LEVEL);
 377                 if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
 378                         therm_throt_process(msr_val &
 379                                         PACKAGE_THERM_STATUS_POWER_LIMIT,
 380                                         POWER_LIMIT_EVENT,
 381                                         PACKAGE_LEVEL);
 382         }
 383 }
 384
 385 static void unexpected_thermal_interrupt(void)
 386 {
 387         pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
 388                 smp_processor_id());
 389 }
 390
 391 static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
 392
 393 static inline void __smp_thermal_interrupt(void)
 394 {
 395         inc_irq_stat(irq_thermal_count);
 396         smp_thermal_vector();
 397 }
 398
 399 asmlinkage __visible void __irq_entry
 400 smp_thermal_interrupt(struct pt_regs *regs)
 401 {
 402         entering_irq();
 403         __smp_thermal_interrupt();
 404         exiting_ack_irq();
 405 }
 406
 407 asmlinkage __visible void __irq_entry
 408 smp_trace_thermal_interrupt(struct pt_regs *regs)
 409 {
 410         entering_irq();
 411         trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
 412         __smp_thermal_interrupt();
 413         trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
 414         exiting_ack_irq();
 415 }
 416
 417 /* Thermal monitoring depends on APIC, ACPI and clock modulation */
 418 static int intel_thermal_supported(struct cpuinfo_x86 *c)
 419 {
 420         if (!boot_cpu_has(X86_FEATURE_APIC))
 421                 return 0;
 422         if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
 423                 return 0;
 424         return 1;
 425 }
 426
 427 void __init mcheck_intel_therm_init(void)
 428 {
 429         /*
 430          * This function is only called on boot CPU. Save the init thermal
 431          * LVT value on BSP and use that value to restore APs' thermal LVT
 432          * entry BIOS programmed later
 433          */
 434         if (intel_thermal_supported(&boot_cpu_data))
 435                 lvtthmr_init = apic_read(APIC_LVTTHMR);
 436 }
 437
 438 void intel_init_thermal(struct cpuinfo_x86 *c)
 439 {
 440         unsigned int cpu = smp_processor_id();
 441         int tm2 = 0;
 442         u32 l, h;
 443
 444         if (!intel_thermal_supported(c))
 445                 return;
 446
 447         /*
 448          * First check if its enabled already, in which case there might
 449          * be some SMM goo which handles it, so we can't even put a handler
 450          * since it might be delivered via SMI already:
 451          */
 452         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 453
 454         h = lvtthmr_init;
 455         /*
 456          * The initial value of thermal LVT entries on all APs always reads
 457          * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
 458          * sequence to them and LVT registers are reset to 0s except for
 459          * the mask bits which are set to 1s when APs receive INIT IPI.
 460          * If BIOS takes over the thermal interrupt and sets its interrupt
 461          * delivery mode to SMI (not fixed), it restores the value that the
 462          * BIOS has programmed on AP based on BSP's info we saved since BIOS
 463          * is always setting the same value for all threads/cores.
 464          */
 465         if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
 466                 apic_write(APIC_LVTTHMR, lvtthmr_init);
 467
 468
 469         if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
 470                 if (system_state == SYSTEM_BOOTING)
 471                         pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu);
 472                 return;
 473         }
 474
 475         /* early Pentium M models use different method for enabling TM2 */
 476         if (cpu_has(c, X86_FEATURE_TM2)) {
 477                 if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
 478                         rdmsr(MSR_THERM2_CTL, l, h);
 479                         if (l & MSR_THERM2_CTL_TM_SELECT)
 480                                 tm2 = 1;
 481                 } else if (l & MSR_IA32_MISC_ENABLE_TM2)
 482                         tm2 = 1;
 483         }
 484
 485         /* We'll mask the thermal vector in the lapic till we're ready: */
 486         h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
 487         apic_write(APIC_LVTTHMR, h);
 488
 489         rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
 490         if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
 491                 wrmsr(MSR_IA32_THERM_INTERRUPT,
 492                         (l | (THERM_INT_LOW_ENABLE
 493                         | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
 494         else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
 495                 wrmsr(MSR_IA32_THERM_INTERRUPT,
 496                         l | (THERM_INT_LOW_ENABLE
 497                         | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
 498         else
 499                 wrmsr(MSR_IA32_THERM_INTERRUPT,
 500                       l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
 501
 502         if (cpu_has(c, X86_FEATURE_PTS)) {
 503                 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
 504                 if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
 505                         wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
 506                                 (l | (PACKAGE_THERM_INT_LOW_ENABLE
 507                                 | PACKAGE_THERM_INT_HIGH_ENABLE))
 508                                 & ~PACKAGE_THERM_INT_PLN_ENABLE, h);
 509                 else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
 510                         wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
 511                                 l | (PACKAGE_THERM_INT_LOW_ENABLE
 512                                 | PACKAGE_THERM_INT_HIGH_ENABLE
 513                                 | PACKAGE_THERM_INT_PLN_ENABLE), h);
 514                 else
 515                         wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
 516                               l | (PACKAGE_THERM_INT_LOW_ENABLE
 517                                 | PACKAGE_THERM_INT_HIGH_ENABLE), h);
 518         }
 519
 520         smp_thermal_vector = intel_thermal_interrupt;
 521
 522         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 523         wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
 524
 525         /* Unmask the thermal vector: */
 526         l = apic_read(APIC_LVTTHMR);
 527         apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
 528
 529         pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
 530                       tm2 ? "TM2" : "TM1");
 531
 532         /* enable thermal throttle processing */
 533         atomic_set(&therm_throt_en, 1);
 534 }