2 * Performance counter x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
10 * For licencing details see kernel-base/COPYING
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
24 #include <asm/stacktrace.h>
27 static u64 perf_counter_mask __read_mostly
;
29 struct cpu_hw_counters
{
30 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
31 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
32 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
33 unsigned long interrupts
;
38 * struct x86_pmu - generic x86 pmu
43 int (*handle_irq
)(struct pt_regs
*, int);
44 void (*disable_all
)(void);
45 void (*enable_all
)(void);
46 void (*enable
)(struct hw_perf_counter
*, int);
47 void (*disable
)(struct hw_perf_counter
*, int);
50 u64 (*event_map
)(int);
51 u64 (*raw_event
)(u64
);
54 int num_counters_fixed
;
61 static struct x86_pmu x86_pmu __read_mostly
;
63 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
) = {
68 * Intel PerfMon v3. Used on Core2 and later.
70 static const u64 intel_perfmon_event_map
[] =
72 [PERF_COUNT_CPU_CYCLES
] = 0x003c,
73 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
74 [PERF_COUNT_CACHE_REFERENCES
] = 0x4f2e,
75 [PERF_COUNT_CACHE_MISSES
] = 0x412e,
76 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
77 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
78 [PERF_COUNT_BUS_CYCLES
] = 0x013c,
81 static u64
intel_pmu_event_map(int event
)
83 return intel_perfmon_event_map
[event
];
86 static u64
intel_pmu_raw_event(u64 event
)
88 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
89 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
90 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
92 #define CORE_EVNTSEL_MASK \
93 (CORE_EVNTSEL_EVENT_MASK | \
94 CORE_EVNTSEL_UNIT_MASK | \
95 CORE_EVNTSEL_COUNTER_MASK)
97 return event
& CORE_EVNTSEL_MASK
;
101 * AMD Performance Monitor K7 and later.
103 static const u64 amd_perfmon_event_map
[] =
105 [PERF_COUNT_CPU_CYCLES
] = 0x0076,
106 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
107 [PERF_COUNT_CACHE_REFERENCES
] = 0x0080,
108 [PERF_COUNT_CACHE_MISSES
] = 0x0081,
109 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
110 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
113 static u64
amd_pmu_event_map(int event
)
115 return amd_perfmon_event_map
[event
];
118 static u64
amd_pmu_raw_event(u64 event
)
120 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
121 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
122 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
124 #define K7_EVNTSEL_MASK \
125 (K7_EVNTSEL_EVENT_MASK | \
126 K7_EVNTSEL_UNIT_MASK | \
127 K7_EVNTSEL_COUNTER_MASK)
129 return event
& K7_EVNTSEL_MASK
;
133 * Propagate counter elapsed time into the generic counter.
134 * Can only be executed on the CPU where the counter is active.
135 * Returns the delta events processed.
138 x86_perf_counter_update(struct perf_counter
*counter
,
139 struct hw_perf_counter
*hwc
, int idx
)
141 int shift
= 64 - x86_pmu
.counter_bits
;
142 u64 prev_raw_count
, new_raw_count
;
146 * Careful: an NMI might modify the previous counter value.
148 * Our tactic to handle this is to first atomically read and
149 * exchange a new raw count - then add that new-prev delta
150 * count to the generic counter atomically:
153 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
154 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
156 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
157 new_raw_count
) != prev_raw_count
)
161 * Now we have the new raw value and have updated the prev
162 * timestamp already. We can now calculate the elapsed delta
163 * (counter-)time and add that to the generic counter.
165 * Careful, not all hw sign-extends above the physical width
168 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
171 atomic64_add(delta
, &counter
->count
);
172 atomic64_sub(delta
, &hwc
->period_left
);
174 return new_raw_count
;
177 static atomic_t active_counters
;
178 static DEFINE_MUTEX(pmc_reserve_mutex
);
180 static bool reserve_pmc_hardware(void)
184 if (nmi_watchdog
== NMI_LOCAL_APIC
)
185 disable_lapic_nmi_watchdog();
187 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
188 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
192 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
193 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
200 for (i
--; i
>= 0; i
--)
201 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
203 i
= x86_pmu
.num_counters
;
206 for (i
--; i
>= 0; i
--)
207 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
209 if (nmi_watchdog
== NMI_LOCAL_APIC
)
210 enable_lapic_nmi_watchdog();
215 static void release_pmc_hardware(void)
219 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
220 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
221 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
224 if (nmi_watchdog
== NMI_LOCAL_APIC
)
225 enable_lapic_nmi_watchdog();
228 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
230 if (atomic_dec_and_mutex_lock(&active_counters
, &pmc_reserve_mutex
)) {
231 release_pmc_hardware();
232 mutex_unlock(&pmc_reserve_mutex
);
236 static inline int x86_pmu_initialized(void)
238 return x86_pmu
.handle_irq
!= NULL
;
242 * Setup the hardware configuration for a given hw_event_type
244 static int __hw_perf_counter_init(struct perf_counter
*counter
)
246 struct perf_counter_hw_event
*hw_event
= &counter
->hw_event
;
247 struct hw_perf_counter
*hwc
= &counter
->hw
;
250 if (!x86_pmu_initialized())
254 if (!atomic_inc_not_zero(&active_counters
)) {
255 mutex_lock(&pmc_reserve_mutex
);
256 if (atomic_read(&active_counters
) == 0 && !reserve_pmc_hardware())
259 atomic_inc(&active_counters
);
260 mutex_unlock(&pmc_reserve_mutex
);
267 * (keep 'enabled' bit clear for now)
269 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
272 * Count user and OS events unless requested not to.
274 if (!hw_event
->exclude_user
)
275 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
276 if (!hw_event
->exclude_kernel
)
277 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
280 * If privileged enough, allow NMI events:
284 if (sysctl_perf_counter_priv
&& !capable(CAP_SYS_ADMIN
))
289 atomic64_set(&hwc
->period_left
,
290 min(x86_pmu
.max_period
, hwc
->irq_period
));
293 * Raw event type provide the config in the event structure
295 if (perf_event_raw(hw_event
)) {
296 hwc
->config
|= x86_pmu
.raw_event(perf_event_config(hw_event
));
298 if (perf_event_id(hw_event
) >= x86_pmu
.max_events
)
303 hwc
->config
|= x86_pmu
.event_map(perf_event_id(hw_event
));
306 counter
->destroy
= hw_perf_counter_destroy
;
311 static void intel_pmu_disable_all(void)
313 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
316 static void amd_pmu_disable_all(void)
318 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
326 * ensure we write the disable before we start disabling the
327 * counters proper, so that amd_pmu_enable_counter() does the
332 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
335 if (!test_bit(idx
, cpuc
->active_mask
))
337 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
338 if (!(val
& ARCH_PERFMON_EVENTSEL0_ENABLE
))
340 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
341 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
345 void hw_perf_disable(void)
347 if (!x86_pmu_initialized())
349 return x86_pmu
.disable_all();
352 static void intel_pmu_enable_all(void)
354 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, x86_pmu
.intel_ctrl
);
357 static void amd_pmu_enable_all(void)
359 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
368 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
371 if (!test_bit(idx
, cpuc
->active_mask
))
373 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
374 if (val
& ARCH_PERFMON_EVENTSEL0_ENABLE
)
376 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
377 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
381 void hw_perf_enable(void)
383 if (!x86_pmu_initialized())
385 x86_pmu
.enable_all();
388 static inline u64
intel_pmu_get_status(void)
392 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
397 static inline void intel_pmu_ack_status(u64 ack
)
399 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
402 static inline void x86_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
405 err
= checking_wrmsrl(hwc
->config_base
+ idx
,
406 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
);
409 static inline void x86_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
412 err
= checking_wrmsrl(hwc
->config_base
+ idx
,
417 intel_pmu_disable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
419 int idx
= __idx
- X86_PMC_IDX_FIXED
;
423 mask
= 0xfULL
<< (idx
* 4);
425 rdmsrl(hwc
->config_base
, ctrl_val
);
427 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
431 intel_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
433 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
434 intel_pmu_disable_fixed(hwc
, idx
);
438 x86_pmu_disable_counter(hwc
, idx
);
442 amd_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
444 x86_pmu_disable_counter(hwc
, idx
);
447 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
450 * Set the next IRQ period, based on the hwc->period_left value.
451 * To be called with the counter disabled in hw:
454 x86_perf_counter_set_period(struct perf_counter
*counter
,
455 struct hw_perf_counter
*hwc
, int idx
)
457 s64 left
= atomic64_read(&hwc
->period_left
);
458 s64 period
= min(x86_pmu
.max_period
, hwc
->irq_period
);
462 * If we are way outside a reasoable range then just skip forward:
464 if (unlikely(left
<= -period
)) {
466 atomic64_set(&hwc
->period_left
, left
);
469 if (unlikely(left
<= 0)) {
471 atomic64_set(&hwc
->period_left
, left
);
474 * Quirk: certain CPUs dont like it if just 1 event is left:
476 if (unlikely(left
< 2))
479 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
482 * The hw counter starts counting from this counter offset,
483 * mark it to be able to extra future deltas:
485 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
487 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
488 (u64
)(-left
) & x86_pmu
.counter_mask
);
492 intel_pmu_enable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
494 int idx
= __idx
- X86_PMC_IDX_FIXED
;
495 u64 ctrl_val
, bits
, mask
;
499 * Enable IRQ generation (0x8),
500 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
504 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
506 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
509 mask
= 0xfULL
<< (idx
* 4);
511 rdmsrl(hwc
->config_base
, ctrl_val
);
514 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
517 static void intel_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
519 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
520 intel_pmu_enable_fixed(hwc
, idx
);
524 x86_pmu_enable_counter(hwc
, idx
);
527 static void amd_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
529 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
532 x86_pmu_enable_counter(hwc
, idx
);
534 x86_pmu_disable_counter(hwc
, idx
);
538 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
542 if (!x86_pmu
.num_counters_fixed
)
545 if (unlikely(hwc
->nmi
))
548 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
550 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_INSTRUCTIONS
)))
551 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
552 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_CPU_CYCLES
)))
553 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
554 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_BUS_CYCLES
)))
555 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
561 * Find a PMC slot for the freshly enabled / scheduled in counter:
563 static int x86_pmu_enable(struct perf_counter
*counter
)
565 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
566 struct hw_perf_counter
*hwc
= &counter
->hw
;
569 idx
= fixed_mode_idx(counter
, hwc
);
572 * Try to get the fixed counter, if that is already taken
573 * then try to get a generic counter:
575 if (test_and_set_bit(idx
, cpuc
->used_mask
))
578 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
580 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
581 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
584 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
588 /* Try to get the previous generic counter again */
589 if (test_and_set_bit(idx
, cpuc
->used_mask
)) {
591 idx
= find_first_zero_bit(cpuc
->used_mask
,
592 x86_pmu
.num_counters
);
593 if (idx
== x86_pmu
.num_counters
)
596 set_bit(idx
, cpuc
->used_mask
);
599 hwc
->config_base
= x86_pmu
.eventsel
;
600 hwc
->counter_base
= x86_pmu
.perfctr
;
603 perf_counters_lapic_init(hwc
->nmi
);
605 x86_pmu
.disable(hwc
, idx
);
607 cpuc
->counters
[idx
] = counter
;
608 set_bit(idx
, cpuc
->active_mask
);
610 x86_perf_counter_set_period(counter
, hwc
, idx
);
611 x86_pmu
.enable(hwc
, idx
);
616 void perf_counter_print_debug(void)
618 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
619 struct cpu_hw_counters
*cpuc
;
623 if (!x86_pmu
.num_counters
)
626 local_irq_save(flags
);
628 cpu
= smp_processor_id();
629 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
631 if (x86_pmu
.version
>= 2) {
632 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
633 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
634 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
635 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
638 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
639 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
640 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
641 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
643 pr_info("CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used_mask
);
645 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
646 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
647 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
649 prev_left
= per_cpu(prev_left
[idx
], cpu
);
651 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
653 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
654 cpu
, idx
, pmc_count
);
655 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
656 cpu
, idx
, prev_left
);
658 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
659 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
661 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
662 cpu
, idx
, pmc_count
);
664 local_irq_restore(flags
);
667 static void x86_pmu_disable(struct perf_counter
*counter
)
669 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
670 struct hw_perf_counter
*hwc
= &counter
->hw
;
674 * Must be done before we disable, otherwise the nmi handler
675 * could reenable again:
677 clear_bit(idx
, cpuc
->active_mask
);
678 x86_pmu
.disable(hwc
, idx
);
681 * Make sure the cleared pointer becomes visible before we
682 * (potentially) free the counter:
687 * Drain the remaining delta count out of a counter
688 * that we are disabling:
690 x86_perf_counter_update(counter
, hwc
, idx
);
691 cpuc
->counters
[idx
] = NULL
;
692 clear_bit(idx
, cpuc
->used_mask
);
696 * Save and restart an expired counter. Called by NMI contexts,
697 * so it has to be careful about preempting normal counter ops:
699 static void intel_pmu_save_and_restart(struct perf_counter
*counter
)
701 struct hw_perf_counter
*hwc
= &counter
->hw
;
704 x86_perf_counter_update(counter
, hwc
, idx
);
705 x86_perf_counter_set_period(counter
, hwc
, idx
);
707 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
708 intel_pmu_enable_counter(hwc
, idx
);
712 * Maximum interrupt frequency of 100KHz per CPU
714 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
717 * This handler is triggered by the local APIC, so the APIC IRQ handling
720 static int intel_pmu_handle_irq(struct pt_regs
*regs
, int nmi
)
722 struct cpu_hw_counters
*cpuc
;
723 struct cpu_hw_counters
;
727 cpu
= smp_processor_id();
728 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
731 status
= intel_pmu_get_status();
740 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
744 inc_irq_stat(apic_perf_irqs
);
746 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
747 struct perf_counter
*counter
= cpuc
->counters
[bit
];
749 clear_bit(bit
, (unsigned long *) &status
);
750 if (!test_bit(bit
, cpuc
->active_mask
))
753 intel_pmu_save_and_restart(counter
);
754 if (perf_counter_overflow(counter
, nmi
, regs
, 0))
755 intel_pmu_disable_counter(&counter
->hw
, bit
);
758 intel_pmu_ack_status(ack
);
761 * Repeat if there is more work to be done:
763 status
= intel_pmu_get_status();
767 if (++cpuc
->interrupts
!= PERFMON_MAX_INTERRUPTS
)
773 static int amd_pmu_handle_irq(struct pt_regs
*regs
, int nmi
)
775 int cpu
, idx
, throttle
= 0, handled
= 0;
776 struct cpu_hw_counters
*cpuc
;
777 struct perf_counter
*counter
;
778 struct hw_perf_counter
*hwc
;
781 cpu
= smp_processor_id();
782 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
784 if (++cpuc
->interrupts
== PERFMON_MAX_INTERRUPTS
) {
791 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
794 if (!test_bit(idx
, cpuc
->active_mask
))
797 counter
= cpuc
->counters
[idx
];
800 if (counter
->hw_event
.nmi
!= nmi
)
803 val
= x86_perf_counter_update(counter
, hwc
, idx
);
804 if (val
& (1ULL << (x86_pmu
.counter_bits
- 1)))
807 /* counter overflow */
808 x86_perf_counter_set_period(counter
, hwc
, idx
);
810 inc_irq_stat(apic_perf_irqs
);
811 disable
= perf_counter_overflow(counter
, nmi
, regs
, 0);
814 if (disable
|| throttle
)
815 amd_pmu_disable_counter(hwc
, idx
);
821 void perf_counter_unthrottle(void)
823 struct cpu_hw_counters
*cpuc
;
825 if (!x86_pmu_initialized())
828 cpuc
= &__get_cpu_var(cpu_hw_counters
);
829 if (cpuc
->interrupts
>= PERFMON_MAX_INTERRUPTS
) {
831 * Clear them before re-enabling irqs/NMIs again:
833 cpuc
->interrupts
= 0;
836 cpuc
->interrupts
= 0;
840 void smp_perf_counter_interrupt(struct pt_regs
*regs
)
843 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
845 x86_pmu
.handle_irq(regs
, 0);
849 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
853 inc_irq_stat(apic_pending_irqs
);
854 perf_counter_do_pending();
858 void set_perf_counter_pending(void)
860 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
863 void perf_counters_lapic_init(int nmi
)
867 if (!x86_pmu_initialized())
871 * Enable the performance counter vector in the APIC LVT:
873 apic_val
= apic_read(APIC_LVTERR
);
875 apic_write(APIC_LVTERR
, apic_val
| APIC_LVT_MASKED
);
877 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
879 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
880 apic_write(APIC_LVTERR
, apic_val
);
884 perf_counter_nmi_handler(struct notifier_block
*self
,
885 unsigned long cmd
, void *__args
)
887 struct die_args
*args
= __args
;
888 struct pt_regs
*regs
;
890 if (!atomic_read(&active_counters
))
904 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
906 * Can't rely on the handled return value to say it was our NMI, two
907 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
909 * If the first NMI handles both, the latter will be empty and daze
912 x86_pmu
.handle_irq(regs
, 1);
917 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
918 .notifier_call
= perf_counter_nmi_handler
,
923 static struct x86_pmu intel_pmu
= {
925 .handle_irq
= intel_pmu_handle_irq
,
926 .disable_all
= intel_pmu_disable_all
,
927 .enable_all
= intel_pmu_enable_all
,
928 .enable
= intel_pmu_enable_counter
,
929 .disable
= intel_pmu_disable_counter
,
930 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
931 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
932 .event_map
= intel_pmu_event_map
,
933 .raw_event
= intel_pmu_raw_event
,
934 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
936 * Intel PMCs cannot be accessed sanely above 32 bit width,
937 * so we install an artificial 1<<31 period regardless of
938 * the generic counter period:
940 .max_period
= (1ULL << 31) - 1,
943 static struct x86_pmu amd_pmu
= {
945 .handle_irq
= amd_pmu_handle_irq
,
946 .disable_all
= amd_pmu_disable_all
,
947 .enable_all
= amd_pmu_enable_all
,
948 .enable
= amd_pmu_enable_counter
,
949 .disable
= amd_pmu_disable_counter
,
950 .eventsel
= MSR_K7_EVNTSEL0
,
951 .perfctr
= MSR_K7_PERFCTR0
,
952 .event_map
= amd_pmu_event_map
,
953 .raw_event
= amd_pmu_raw_event
,
954 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
957 .counter_mask
= (1ULL << 48) - 1,
958 /* use highest bit to detect overflow */
959 .max_period
= (1ULL << 47) - 1,
962 static int intel_pmu_init(void)
964 union cpuid10_edx edx
;
965 union cpuid10_eax eax
;
970 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
974 * Check whether the Architectural PerfMon supports
975 * Branch Misses Retired Event or not.
977 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
978 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
981 version
= eax
.split
.version_id
;
986 x86_pmu
.version
= version
;
987 x86_pmu
.num_counters
= eax
.split
.num_counters
;
990 * Quirk: v2 perfmon does not report fixed-purpose counters, so
991 * assume at least 3 counters:
993 x86_pmu
.num_counters_fixed
= max((int)edx
.split
.num_counters_fixed
, 3);
995 x86_pmu
.counter_bits
= eax
.split
.bit_width
;
996 x86_pmu
.counter_mask
= (1ULL << eax
.split
.bit_width
) - 1;
998 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, x86_pmu
.intel_ctrl
);
1003 static int amd_pmu_init(void)
1009 void __init
init_hw_perf_counters(void)
1013 switch (boot_cpu_data
.x86_vendor
) {
1014 case X86_VENDOR_INTEL
:
1015 err
= intel_pmu_init();
1017 case X86_VENDOR_AMD
:
1018 err
= amd_pmu_init();
1026 pr_info("%s Performance Monitoring support detected.\n", x86_pmu
.name
);
1027 pr_info("... version: %d\n", x86_pmu
.version
);
1028 pr_info("... bit width: %d\n", x86_pmu
.counter_bits
);
1030 pr_info("... num counters: %d\n", x86_pmu
.num_counters
);
1031 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1032 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1033 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
1034 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1036 perf_counter_mask
= (1 << x86_pmu
.num_counters
) - 1;
1037 perf_max_counters
= x86_pmu
.num_counters
;
1039 pr_info("... value mask: %016Lx\n", x86_pmu
.counter_mask
);
1040 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1042 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1043 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1044 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
1045 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1047 pr_info("... fixed counters: %d\n", x86_pmu
.num_counters_fixed
);
1049 perf_counter_mask
|=
1050 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1052 pr_info("... counter mask: %016Lx\n", perf_counter_mask
);
1054 perf_counters_lapic_init(0);
1055 register_die_notifier(&perf_counter_nmi_notifier
);
1058 static inline void x86_pmu_read(struct perf_counter
*counter
)
1060 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
1063 static const struct pmu pmu
= {
1064 .enable
= x86_pmu_enable
,
1065 .disable
= x86_pmu_disable
,
1066 .read
= x86_pmu_read
,
1069 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
1073 err
= __hw_perf_counter_init(counter
);
1075 return ERR_PTR(err
);
1085 void callchain_store(struct perf_callchain_entry
*entry
, unsigned long ip
)
1087 if (entry
->nr
< MAX_STACK_DEPTH
)
1088 entry
->ip
[entry
->nr
++] = ip
;
1091 static DEFINE_PER_CPU(struct perf_callchain_entry
, irq_entry
);
1092 static DEFINE_PER_CPU(struct perf_callchain_entry
, nmi_entry
);
1096 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1098 /* Ignore warnings */
1101 static void backtrace_warning(void *data
, char *msg
)
1103 /* Ignore warnings */
1106 static int backtrace_stack(void *data
, char *name
)
1108 /* Don't bother with IRQ stacks for now */
1112 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1114 struct perf_callchain_entry
*entry
= data
;
1117 callchain_store(entry
, addr
);
1120 static const struct stacktrace_ops backtrace_ops
= {
1121 .warning
= backtrace_warning
,
1122 .warning_symbol
= backtrace_warning_symbol
,
1123 .stack
= backtrace_stack
,
1124 .address
= backtrace_address
,
1128 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1134 callchain_store(entry
, instruction_pointer(regs
));
1136 stack
= ((char *)regs
+ sizeof(struct pt_regs
));
1137 #ifdef CONFIG_FRAME_POINTER
1138 bp
= frame_pointer(regs
);
1143 dump_trace(NULL
, regs
, (void *)stack
, bp
, &backtrace_ops
, entry
);
1145 entry
->kernel
= entry
->nr
- nr
;
1149 struct stack_frame
{
1150 const void __user
*next_fp
;
1151 unsigned long return_address
;
1154 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1158 if (!access_ok(VERIFY_READ
, fp
, sizeof(*frame
)))
1162 pagefault_disable();
1163 if (__copy_from_user_inatomic(frame
, fp
, sizeof(*frame
)))
1171 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1173 struct stack_frame frame
;
1174 const void __user
*fp
;
1177 regs
= (struct pt_regs
*)current
->thread
.sp0
- 1;
1178 fp
= (void __user
*)regs
->bp
;
1180 callchain_store(entry
, regs
->ip
);
1182 while (entry
->nr
< MAX_STACK_DEPTH
) {
1183 frame
.next_fp
= NULL
;
1184 frame
.return_address
= 0;
1186 if (!copy_stack_frame(fp
, &frame
))
1189 if ((unsigned long)fp
< user_stack_pointer(regs
))
1192 callchain_store(entry
, frame
.return_address
);
1196 entry
->user
= entry
->nr
- nr
;
1200 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1207 is_user
= user_mode(regs
);
1209 if (!current
|| current
->pid
== 0)
1212 if (is_user
&& current
->state
!= TASK_RUNNING
)
1216 perf_callchain_kernel(regs
, entry
);
1219 perf_callchain_user(regs
, entry
);
1222 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1224 struct perf_callchain_entry
*entry
;
1227 entry
= &__get_cpu_var(nmi_entry
);
1229 entry
= &__get_cpu_var(irq_entry
);
1236 perf_do_callchain(regs
, entry
);