2 * Performance counter x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
10 * For licencing details see kernel-base/COPYING
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
22 #include <linux/highmem.h>
25 #include <asm/stacktrace.h>
28 static u64 perf_counter_mask __read_mostly
;
30 struct cpu_hw_counters
{
31 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
32 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
33 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
34 unsigned long interrupts
;
39 * struct x86_pmu - generic x86 pmu
44 int (*handle_irq
)(struct pt_regs
*);
45 void (*disable_all
)(void);
46 void (*enable_all
)(void);
47 void (*enable
)(struct hw_perf_counter
*, int);
48 void (*disable
)(struct hw_perf_counter
*, int);
51 u64 (*event_map
)(int);
52 u64 (*raw_event
)(u64
);
55 int num_counters_fixed
;
62 static struct x86_pmu x86_pmu __read_mostly
;
64 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
) = {
69 * Intel PerfMon v3. Used on Core2 and later.
71 static const u64 intel_perfmon_event_map
[] =
73 [PERF_COUNT_HW_CPU_CYCLES
] = 0x003c,
74 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
75 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x4f2e,
76 [PERF_COUNT_HW_CACHE_MISSES
] = 0x412e,
77 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
78 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
79 [PERF_COUNT_HW_BUS_CYCLES
] = 0x013c,
82 static u64
intel_pmu_event_map(int event
)
84 return intel_perfmon_event_map
[event
];
88 * Generalized hw caching related event table, filled
89 * in on a per model basis. A value of 0 means
90 * 'not supported', -1 means 'event makes no sense on
91 * this CPU', any other value means the raw event
95 #define C(x) PERF_COUNT_HW_CACHE_##x
97 static u64 __read_mostly hw_cache_event_ids
98 [PERF_COUNT_HW_CACHE_MAX
]
99 [PERF_COUNT_HW_CACHE_OP_MAX
]
100 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
102 static const u64 nehalem_hw_cache_event_ids
103 [PERF_COUNT_HW_CACHE_MAX
]
104 [PERF_COUNT_HW_CACHE_OP_MAX
]
105 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
109 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
110 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
113 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
114 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
116 [ C(OP_PREFETCH
) ] = {
117 [ C(RESULT_ACCESS
) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
118 [ C(RESULT_MISS
) ] = 0x024e, /* L1D_PREFETCH.MISS */
123 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
124 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
127 [ C(RESULT_ACCESS
) ] = -1,
128 [ C(RESULT_MISS
) ] = -1,
130 [ C(OP_PREFETCH
) ] = {
131 [ C(RESULT_ACCESS
) ] = 0x0,
132 [ C(RESULT_MISS
) ] = 0x0,
137 [ C(RESULT_ACCESS
) ] = 0x0324, /* L2_RQSTS.LOADS */
138 [ C(RESULT_MISS
) ] = 0x0224, /* L2_RQSTS.LD_MISS */
141 [ C(RESULT_ACCESS
) ] = 0x0c24, /* L2_RQSTS.RFOS */
142 [ C(RESULT_MISS
) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
144 [ C(OP_PREFETCH
) ] = {
145 [ C(RESULT_ACCESS
) ] = 0x4f2e, /* LLC Reference */
146 [ C(RESULT_MISS
) ] = 0x412e, /* LLC Misses */
151 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
152 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
155 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
156 [ C(RESULT_MISS
) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
158 [ C(OP_PREFETCH
) ] = {
159 [ C(RESULT_ACCESS
) ] = 0x0,
160 [ C(RESULT_MISS
) ] = 0x0,
165 [ C(RESULT_ACCESS
) ] = 0x01c0, /* INST_RETIRED.ANY_P */
166 [ C(RESULT_MISS
) ] = 0x20c8, /* ITLB_MISS_RETIRED */
169 [ C(RESULT_ACCESS
) ] = -1,
170 [ C(RESULT_MISS
) ] = -1,
172 [ C(OP_PREFETCH
) ] = {
173 [ C(RESULT_ACCESS
) ] = -1,
174 [ C(RESULT_MISS
) ] = -1,
179 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
180 [ C(RESULT_MISS
) ] = 0x03e8, /* BPU_CLEARS.ANY */
183 [ C(RESULT_ACCESS
) ] = -1,
184 [ C(RESULT_MISS
) ] = -1,
186 [ C(OP_PREFETCH
) ] = {
187 [ C(RESULT_ACCESS
) ] = -1,
188 [ C(RESULT_MISS
) ] = -1,
193 static const u64 core2_hw_cache_event_ids
194 [PERF_COUNT_HW_CACHE_MAX
]
195 [PERF_COUNT_HW_CACHE_OP_MAX
]
196 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
200 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
201 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
204 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
205 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
207 [ C(OP_PREFETCH
) ] = {
208 [ C(RESULT_ACCESS
) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
209 [ C(RESULT_MISS
) ] = 0,
214 [ C(RESULT_ACCESS
) ] = 0x0080, /* L1I.READS */
215 [ C(RESULT_MISS
) ] = 0x0081, /* L1I.MISSES */
218 [ C(RESULT_ACCESS
) ] = -1,
219 [ C(RESULT_MISS
) ] = -1,
221 [ C(OP_PREFETCH
) ] = {
222 [ C(RESULT_ACCESS
) ] = 0,
223 [ C(RESULT_MISS
) ] = 0,
228 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
229 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
232 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
233 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
235 [ C(OP_PREFETCH
) ] = {
236 [ C(RESULT_ACCESS
) ] = 0,
237 [ C(RESULT_MISS
) ] = 0,
242 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
243 [ C(RESULT_MISS
) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
246 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
247 [ C(RESULT_MISS
) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
249 [ C(OP_PREFETCH
) ] = {
250 [ C(RESULT_ACCESS
) ] = 0,
251 [ C(RESULT_MISS
) ] = 0,
256 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
257 [ C(RESULT_MISS
) ] = 0x1282, /* ITLBMISSES */
260 [ C(RESULT_ACCESS
) ] = -1,
261 [ C(RESULT_MISS
) ] = -1,
263 [ C(OP_PREFETCH
) ] = {
264 [ C(RESULT_ACCESS
) ] = -1,
265 [ C(RESULT_MISS
) ] = -1,
270 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
271 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
274 [ C(RESULT_ACCESS
) ] = -1,
275 [ C(RESULT_MISS
) ] = -1,
277 [ C(OP_PREFETCH
) ] = {
278 [ C(RESULT_ACCESS
) ] = -1,
279 [ C(RESULT_MISS
) ] = -1,
284 static const u64 atom_hw_cache_event_ids
285 [PERF_COUNT_HW_CACHE_MAX
]
286 [PERF_COUNT_HW_CACHE_OP_MAX
]
287 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
291 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE.LD */
292 [ C(RESULT_MISS
) ] = 0,
295 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE.ST */
296 [ C(RESULT_MISS
) ] = 0,
298 [ C(OP_PREFETCH
) ] = {
299 [ C(RESULT_ACCESS
) ] = 0x0,
300 [ C(RESULT_MISS
) ] = 0,
305 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
306 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
309 [ C(RESULT_ACCESS
) ] = -1,
310 [ C(RESULT_MISS
) ] = -1,
312 [ C(OP_PREFETCH
) ] = {
313 [ C(RESULT_ACCESS
) ] = 0,
314 [ C(RESULT_MISS
) ] = 0,
319 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
320 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
323 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
324 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
326 [ C(OP_PREFETCH
) ] = {
327 [ C(RESULT_ACCESS
) ] = 0,
328 [ C(RESULT_MISS
) ] = 0,
333 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
334 [ C(RESULT_MISS
) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
337 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
338 [ C(RESULT_MISS
) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
340 [ C(OP_PREFETCH
) ] = {
341 [ C(RESULT_ACCESS
) ] = 0,
342 [ C(RESULT_MISS
) ] = 0,
347 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
348 [ C(RESULT_MISS
) ] = 0x0282, /* ITLB.MISSES */
351 [ C(RESULT_ACCESS
) ] = -1,
352 [ C(RESULT_MISS
) ] = -1,
354 [ C(OP_PREFETCH
) ] = {
355 [ C(RESULT_ACCESS
) ] = -1,
356 [ C(RESULT_MISS
) ] = -1,
361 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
362 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
365 [ C(RESULT_ACCESS
) ] = -1,
366 [ C(RESULT_MISS
) ] = -1,
368 [ C(OP_PREFETCH
) ] = {
369 [ C(RESULT_ACCESS
) ] = -1,
370 [ C(RESULT_MISS
) ] = -1,
375 static u64
intel_pmu_raw_event(u64 event
)
377 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
378 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
379 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
380 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
381 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
383 #define CORE_EVNTSEL_MASK \
384 (CORE_EVNTSEL_EVENT_MASK | \
385 CORE_EVNTSEL_UNIT_MASK | \
386 CORE_EVNTSEL_EDGE_MASK | \
387 CORE_EVNTSEL_INV_MASK | \
388 CORE_EVNTSEL_COUNTER_MASK)
390 return event
& CORE_EVNTSEL_MASK
;
393 static const u64 amd_hw_cache_event_ids
394 [PERF_COUNT_HW_CACHE_MAX
]
395 [PERF_COUNT_HW_CACHE_OP_MAX
]
396 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
400 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
401 [ C(RESULT_MISS
) ] = 0x0041, /* Data Cache Misses */
404 [ C(RESULT_ACCESS
) ] = 0x0142, /* Data Cache Refills :system */
405 [ C(RESULT_MISS
) ] = 0,
407 [ C(OP_PREFETCH
) ] = {
408 [ C(RESULT_ACCESS
) ] = 0x0267, /* Data Prefetcher :attempts */
409 [ C(RESULT_MISS
) ] = 0x0167, /* Data Prefetcher :cancelled */
414 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction cache fetches */
415 [ C(RESULT_MISS
) ] = 0x0081, /* Instruction cache misses */
418 [ C(RESULT_ACCESS
) ] = -1,
419 [ C(RESULT_MISS
) ] = -1,
421 [ C(OP_PREFETCH
) ] = {
422 [ C(RESULT_ACCESS
) ] = 0x014B, /* Prefetch Instructions :Load */
423 [ C(RESULT_MISS
) ] = 0,
428 [ C(RESULT_ACCESS
) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
429 [ C(RESULT_MISS
) ] = 0x037E, /* L2 Cache Misses : IC+DC */
432 [ C(RESULT_ACCESS
) ] = 0x017F, /* L2 Fill/Writeback */
433 [ C(RESULT_MISS
) ] = 0,
435 [ C(OP_PREFETCH
) ] = {
436 [ C(RESULT_ACCESS
) ] = 0,
437 [ C(RESULT_MISS
) ] = 0,
442 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
443 [ C(RESULT_MISS
) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
446 [ C(RESULT_ACCESS
) ] = 0,
447 [ C(RESULT_MISS
) ] = 0,
449 [ C(OP_PREFETCH
) ] = {
450 [ C(RESULT_ACCESS
) ] = 0,
451 [ C(RESULT_MISS
) ] = 0,
456 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction fecthes */
457 [ C(RESULT_MISS
) ] = 0x0085, /* Instr. fetch ITLB misses */
460 [ C(RESULT_ACCESS
) ] = -1,
461 [ C(RESULT_MISS
) ] = -1,
463 [ C(OP_PREFETCH
) ] = {
464 [ C(RESULT_ACCESS
) ] = -1,
465 [ C(RESULT_MISS
) ] = -1,
470 [ C(RESULT_ACCESS
) ] = 0x00c2, /* Retired Branch Instr. */
471 [ C(RESULT_MISS
) ] = 0x00c3, /* Retired Mispredicted BI */
474 [ C(RESULT_ACCESS
) ] = -1,
475 [ C(RESULT_MISS
) ] = -1,
477 [ C(OP_PREFETCH
) ] = {
478 [ C(RESULT_ACCESS
) ] = -1,
479 [ C(RESULT_MISS
) ] = -1,
485 * AMD Performance Monitor K7 and later.
487 static const u64 amd_perfmon_event_map
[] =
489 [PERF_COUNT_HW_CPU_CYCLES
] = 0x0076,
490 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
491 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x0080,
492 [PERF_COUNT_HW_CACHE_MISSES
] = 0x0081,
493 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
494 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
497 static u64
amd_pmu_event_map(int event
)
499 return amd_perfmon_event_map
[event
];
502 static u64
amd_pmu_raw_event(u64 event
)
504 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
505 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
506 #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
507 #define K7_EVNTSEL_INV_MASK 0x000800000ULL
508 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
510 #define K7_EVNTSEL_MASK \
511 (K7_EVNTSEL_EVENT_MASK | \
512 K7_EVNTSEL_UNIT_MASK | \
513 K7_EVNTSEL_EDGE_MASK | \
514 K7_EVNTSEL_INV_MASK | \
515 K7_EVNTSEL_COUNTER_MASK)
517 return event
& K7_EVNTSEL_MASK
;
521 * Propagate counter elapsed time into the generic counter.
522 * Can only be executed on the CPU where the counter is active.
523 * Returns the delta events processed.
526 x86_perf_counter_update(struct perf_counter
*counter
,
527 struct hw_perf_counter
*hwc
, int idx
)
529 int shift
= 64 - x86_pmu
.counter_bits
;
530 u64 prev_raw_count
, new_raw_count
;
534 * Careful: an NMI might modify the previous counter value.
536 * Our tactic to handle this is to first atomically read and
537 * exchange a new raw count - then add that new-prev delta
538 * count to the generic counter atomically:
541 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
542 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
544 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
545 new_raw_count
) != prev_raw_count
)
549 * Now we have the new raw value and have updated the prev
550 * timestamp already. We can now calculate the elapsed delta
551 * (counter-)time and add that to the generic counter.
553 * Careful, not all hw sign-extends above the physical width
556 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
559 atomic64_add(delta
, &counter
->count
);
560 atomic64_sub(delta
, &hwc
->period_left
);
562 return new_raw_count
;
565 static atomic_t active_counters
;
566 static DEFINE_MUTEX(pmc_reserve_mutex
);
568 static bool reserve_pmc_hardware(void)
572 if (nmi_watchdog
== NMI_LOCAL_APIC
)
573 disable_lapic_nmi_watchdog();
575 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
576 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
580 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
581 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
588 for (i
--; i
>= 0; i
--)
589 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
591 i
= x86_pmu
.num_counters
;
594 for (i
--; i
>= 0; i
--)
595 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
597 if (nmi_watchdog
== NMI_LOCAL_APIC
)
598 enable_lapic_nmi_watchdog();
603 static void release_pmc_hardware(void)
607 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
608 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
609 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
612 if (nmi_watchdog
== NMI_LOCAL_APIC
)
613 enable_lapic_nmi_watchdog();
616 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
618 if (atomic_dec_and_mutex_lock(&active_counters
, &pmc_reserve_mutex
)) {
619 release_pmc_hardware();
620 mutex_unlock(&pmc_reserve_mutex
);
624 static inline int x86_pmu_initialized(void)
626 return x86_pmu
.handle_irq
!= NULL
;
630 set_ext_hw_attr(struct hw_perf_counter
*hwc
, struct perf_counter_attr
*attr
)
632 unsigned int cache_type
, cache_op
, cache_result
;
635 config
= attr
->config
;
637 cache_type
= (config
>> 0) & 0xff;
638 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
641 cache_op
= (config
>> 8) & 0xff;
642 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
645 cache_result
= (config
>> 16) & 0xff;
646 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
649 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
663 * Setup the hardware configuration for a given attr_type
665 static int __hw_perf_counter_init(struct perf_counter
*counter
)
667 struct perf_counter_attr
*attr
= &counter
->attr
;
668 struct hw_perf_counter
*hwc
= &counter
->hw
;
671 if (!x86_pmu_initialized())
675 if (!atomic_inc_not_zero(&active_counters
)) {
676 mutex_lock(&pmc_reserve_mutex
);
677 if (atomic_read(&active_counters
) == 0 && !reserve_pmc_hardware())
680 atomic_inc(&active_counters
);
681 mutex_unlock(&pmc_reserve_mutex
);
688 * (keep 'enabled' bit clear for now)
690 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
693 * Count user and OS events unless requested not to.
695 if (!attr
->exclude_user
)
696 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
697 if (!attr
->exclude_kernel
)
698 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
700 if (!hwc
->sample_period
) {
701 hwc
->sample_period
= x86_pmu
.max_period
;
702 hwc
->last_period
= hwc
->sample_period
;
703 atomic64_set(&hwc
->period_left
, hwc
->sample_period
);
706 counter
->destroy
= hw_perf_counter_destroy
;
709 * Raw event type provide the config in the event structure
711 if (attr
->type
== PERF_TYPE_RAW
) {
712 hwc
->config
|= x86_pmu
.raw_event(attr
->config
);
716 if (attr
->type
== PERF_TYPE_HW_CACHE
)
717 return set_ext_hw_attr(hwc
, attr
);
719 if (attr
->config
>= x86_pmu
.max_events
)
724 hwc
->config
|= x86_pmu
.event_map(attr
->config
);
729 static void intel_pmu_disable_all(void)
731 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
734 static void amd_pmu_disable_all(void)
736 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
744 * ensure we write the disable before we start disabling the
745 * counters proper, so that amd_pmu_enable_counter() does the
750 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
753 if (!test_bit(idx
, cpuc
->active_mask
))
755 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
756 if (!(val
& ARCH_PERFMON_EVENTSEL0_ENABLE
))
758 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
759 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
763 void hw_perf_disable(void)
765 if (!x86_pmu_initialized())
767 return x86_pmu
.disable_all();
770 static void intel_pmu_enable_all(void)
772 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, x86_pmu
.intel_ctrl
);
775 static void amd_pmu_enable_all(void)
777 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
786 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
789 if (!test_bit(idx
, cpuc
->active_mask
))
791 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
792 if (val
& ARCH_PERFMON_EVENTSEL0_ENABLE
)
794 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
795 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
799 void hw_perf_enable(void)
801 if (!x86_pmu_initialized())
803 x86_pmu
.enable_all();
806 static inline u64
intel_pmu_get_status(void)
810 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
815 static inline void intel_pmu_ack_status(u64 ack
)
817 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
820 static inline void x86_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
823 err
= checking_wrmsrl(hwc
->config_base
+ idx
,
824 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
);
827 static inline void x86_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
830 err
= checking_wrmsrl(hwc
->config_base
+ idx
,
835 intel_pmu_disable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
837 int idx
= __idx
- X86_PMC_IDX_FIXED
;
841 mask
= 0xfULL
<< (idx
* 4);
843 rdmsrl(hwc
->config_base
, ctrl_val
);
845 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
849 intel_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
851 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
852 intel_pmu_disable_fixed(hwc
, idx
);
856 x86_pmu_disable_counter(hwc
, idx
);
860 amd_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
862 x86_pmu_disable_counter(hwc
, idx
);
865 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
868 * Set the next IRQ period, based on the hwc->period_left value.
869 * To be called with the counter disabled in hw:
872 x86_perf_counter_set_period(struct perf_counter
*counter
,
873 struct hw_perf_counter
*hwc
, int idx
)
875 s64 left
= atomic64_read(&hwc
->period_left
);
876 s64 period
= hwc
->sample_period
;
880 * If we are way outside a reasoable range then just skip forward:
882 if (unlikely(left
<= -period
)) {
884 atomic64_set(&hwc
->period_left
, left
);
885 hwc
->last_period
= period
;
889 if (unlikely(left
<= 0)) {
891 atomic64_set(&hwc
->period_left
, left
);
892 hwc
->last_period
= period
;
896 * Quirk: certain CPUs dont like it if just 1 event is left:
898 if (unlikely(left
< 2))
901 if (left
> x86_pmu
.max_period
)
902 left
= x86_pmu
.max_period
;
904 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
907 * The hw counter starts counting from this counter offset,
908 * mark it to be able to extra future deltas:
910 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
912 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
913 (u64
)(-left
) & x86_pmu
.counter_mask
);
915 perf_counter_update_userpage(counter
);
921 intel_pmu_enable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
923 int idx
= __idx
- X86_PMC_IDX_FIXED
;
924 u64 ctrl_val
, bits
, mask
;
928 * Enable IRQ generation (0x8),
929 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
933 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
935 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
938 mask
= 0xfULL
<< (idx
* 4);
940 rdmsrl(hwc
->config_base
, ctrl_val
);
943 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
946 static void intel_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
948 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
949 intel_pmu_enable_fixed(hwc
, idx
);
953 x86_pmu_enable_counter(hwc
, idx
);
956 static void amd_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
958 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
961 x86_pmu_enable_counter(hwc
, idx
);
963 x86_pmu_disable_counter(hwc
, idx
);
967 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
971 if (!x86_pmu
.num_counters_fixed
)
974 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
976 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_INSTRUCTIONS
)))
977 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
978 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_CPU_CYCLES
)))
979 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
980 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_BUS_CYCLES
)))
981 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
987 * Find a PMC slot for the freshly enabled / scheduled in counter:
989 static int x86_pmu_enable(struct perf_counter
*counter
)
991 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
992 struct hw_perf_counter
*hwc
= &counter
->hw
;
995 idx
= fixed_mode_idx(counter
, hwc
);
998 * Try to get the fixed counter, if that is already taken
999 * then try to get a generic counter:
1001 if (test_and_set_bit(idx
, cpuc
->used_mask
))
1004 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1006 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
1007 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1010 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
1014 /* Try to get the previous generic counter again */
1015 if (test_and_set_bit(idx
, cpuc
->used_mask
)) {
1017 idx
= find_first_zero_bit(cpuc
->used_mask
,
1018 x86_pmu
.num_counters
);
1019 if (idx
== x86_pmu
.num_counters
)
1022 set_bit(idx
, cpuc
->used_mask
);
1025 hwc
->config_base
= x86_pmu
.eventsel
;
1026 hwc
->counter_base
= x86_pmu
.perfctr
;
1029 perf_counters_lapic_init();
1031 x86_pmu
.disable(hwc
, idx
);
1033 cpuc
->counters
[idx
] = counter
;
1034 set_bit(idx
, cpuc
->active_mask
);
1036 x86_perf_counter_set_period(counter
, hwc
, idx
);
1037 x86_pmu
.enable(hwc
, idx
);
1039 perf_counter_update_userpage(counter
);
1044 static void x86_pmu_unthrottle(struct perf_counter
*counter
)
1046 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1047 struct hw_perf_counter
*hwc
= &counter
->hw
;
1049 if (WARN_ON_ONCE(hwc
->idx
>= X86_PMC_IDX_MAX
||
1050 cpuc
->counters
[hwc
->idx
] != counter
))
1053 x86_pmu
.enable(hwc
, hwc
->idx
);
1056 void perf_counter_print_debug(void)
1058 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1059 struct cpu_hw_counters
*cpuc
;
1060 unsigned long flags
;
1063 if (!x86_pmu
.num_counters
)
1066 local_irq_save(flags
);
1068 cpu
= smp_processor_id();
1069 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
1071 if (x86_pmu
.version
>= 2) {
1072 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1073 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1074 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1075 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1078 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1079 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1080 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1081 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1083 pr_info("CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used_mask
);
1085 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1086 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1087 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1089 prev_left
= per_cpu(prev_left
[idx
], cpu
);
1091 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1092 cpu
, idx
, pmc_ctrl
);
1093 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1094 cpu
, idx
, pmc_count
);
1095 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1096 cpu
, idx
, prev_left
);
1098 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1099 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1101 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1102 cpu
, idx
, pmc_count
);
1104 local_irq_restore(flags
);
1107 static void x86_pmu_disable(struct perf_counter
*counter
)
1109 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1110 struct hw_perf_counter
*hwc
= &counter
->hw
;
1114 * Must be done before we disable, otherwise the nmi handler
1115 * could reenable again:
1117 clear_bit(idx
, cpuc
->active_mask
);
1118 x86_pmu
.disable(hwc
, idx
);
1121 * Make sure the cleared pointer becomes visible before we
1122 * (potentially) free the counter:
1127 * Drain the remaining delta count out of a counter
1128 * that we are disabling:
1130 x86_perf_counter_update(counter
, hwc
, idx
);
1131 cpuc
->counters
[idx
] = NULL
;
1132 clear_bit(idx
, cpuc
->used_mask
);
1134 perf_counter_update_userpage(counter
);
1138 * Save and restart an expired counter. Called by NMI contexts,
1139 * so it has to be careful about preempting normal counter ops:
1141 static int intel_pmu_save_and_restart(struct perf_counter
*counter
)
1143 struct hw_perf_counter
*hwc
= &counter
->hw
;
1147 x86_perf_counter_update(counter
, hwc
, idx
);
1148 ret
= x86_perf_counter_set_period(counter
, hwc
, idx
);
1150 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
1151 intel_pmu_enable_counter(hwc
, idx
);
1156 static void intel_pmu_reset(void)
1158 unsigned long flags
;
1161 if (!x86_pmu
.num_counters
)
1164 local_irq_save(flags
);
1166 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1168 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1169 checking_wrmsrl(x86_pmu
.eventsel
+ idx
, 0ull);
1170 checking_wrmsrl(x86_pmu
.perfctr
+ idx
, 0ull);
1172 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1173 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, 0ull);
1176 local_irq_restore(flags
);
1181 * This handler is triggered by the local APIC, so the APIC IRQ handling
1184 static int intel_pmu_handle_irq(struct pt_regs
*regs
)
1186 struct perf_sample_data data
;
1187 struct cpu_hw_counters
*cpuc
;
1188 int bit
, cpu
, loops
;
1194 cpu
= smp_processor_id();
1195 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
1198 status
= intel_pmu_get_status();
1206 if (++loops
> 100) {
1207 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
1208 perf_counter_print_debug();
1214 inc_irq_stat(apic_perf_irqs
);
1216 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
1217 struct perf_counter
*counter
= cpuc
->counters
[bit
];
1219 clear_bit(bit
, (unsigned long *) &status
);
1220 if (!test_bit(bit
, cpuc
->active_mask
))
1223 if (!intel_pmu_save_and_restart(counter
))
1226 data
.period
= counter
->hw
.last_period
;
1228 if (perf_counter_overflow(counter
, 1, &data
))
1229 intel_pmu_disable_counter(&counter
->hw
, bit
);
1232 intel_pmu_ack_status(ack
);
1235 * Repeat if there is more work to be done:
1237 status
= intel_pmu_get_status();
1246 static int amd_pmu_handle_irq(struct pt_regs
*regs
)
1248 struct perf_sample_data data
;
1249 struct cpu_hw_counters
*cpuc
;
1250 struct perf_counter
*counter
;
1251 struct hw_perf_counter
*hwc
;
1252 int cpu
, idx
, handled
= 0;
1258 cpu
= smp_processor_id();
1259 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
1261 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1262 if (!test_bit(idx
, cpuc
->active_mask
))
1265 counter
= cpuc
->counters
[idx
];
1268 val
= x86_perf_counter_update(counter
, hwc
, idx
);
1269 if (val
& (1ULL << (x86_pmu
.counter_bits
- 1)))
1276 data
.period
= counter
->hw
.last_period
;
1278 if (!x86_perf_counter_set_period(counter
, hwc
, idx
))
1281 if (perf_counter_overflow(counter
, 1, &data
))
1282 amd_pmu_disable_counter(hwc
, idx
);
1286 inc_irq_stat(apic_perf_irqs
);
1291 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
1295 inc_irq_stat(apic_pending_irqs
);
1296 perf_counter_do_pending();
1300 void set_perf_counter_pending(void)
1302 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
1305 void perf_counters_lapic_init(void)
1307 if (!x86_pmu_initialized())
1311 * Always use NMI for PMU
1313 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1316 static int __kprobes
1317 perf_counter_nmi_handler(struct notifier_block
*self
,
1318 unsigned long cmd
, void *__args
)
1320 struct die_args
*args
= __args
;
1321 struct pt_regs
*regs
;
1323 if (!atomic_read(&active_counters
))
1337 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1339 * Can't rely on the handled return value to say it was our NMI, two
1340 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
1342 * If the first NMI handles both, the latter will be empty and daze
1345 x86_pmu
.handle_irq(regs
);
1350 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
1351 .notifier_call
= perf_counter_nmi_handler
,
1356 static struct x86_pmu intel_pmu
= {
1358 .handle_irq
= intel_pmu_handle_irq
,
1359 .disable_all
= intel_pmu_disable_all
,
1360 .enable_all
= intel_pmu_enable_all
,
1361 .enable
= intel_pmu_enable_counter
,
1362 .disable
= intel_pmu_disable_counter
,
1363 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
1364 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
1365 .event_map
= intel_pmu_event_map
,
1366 .raw_event
= intel_pmu_raw_event
,
1367 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
1369 * Intel PMCs cannot be accessed sanely above 32 bit width,
1370 * so we install an artificial 1<<31 period regardless of
1371 * the generic counter period:
1373 .max_period
= (1ULL << 31) - 1,
1376 static struct x86_pmu amd_pmu
= {
1378 .handle_irq
= amd_pmu_handle_irq
,
1379 .disable_all
= amd_pmu_disable_all
,
1380 .enable_all
= amd_pmu_enable_all
,
1381 .enable
= amd_pmu_enable_counter
,
1382 .disable
= amd_pmu_disable_counter
,
1383 .eventsel
= MSR_K7_EVNTSEL0
,
1384 .perfctr
= MSR_K7_PERFCTR0
,
1385 .event_map
= amd_pmu_event_map
,
1386 .raw_event
= amd_pmu_raw_event
,
1387 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
1390 .counter_mask
= (1ULL << 48) - 1,
1391 /* use highest bit to detect overflow */
1392 .max_period
= (1ULL << 47) - 1,
1395 static int intel_pmu_init(void)
1397 union cpuid10_edx edx
;
1398 union cpuid10_eax eax
;
1399 unsigned int unused
;
1403 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
1407 * Check whether the Architectural PerfMon supports
1408 * Branch Misses Retired Event or not.
1410 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
1411 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
1414 version
= eax
.split
.version_id
;
1418 x86_pmu
= intel_pmu
;
1419 x86_pmu
.version
= version
;
1420 x86_pmu
.num_counters
= eax
.split
.num_counters
;
1421 x86_pmu
.counter_bits
= eax
.split
.bit_width
;
1422 x86_pmu
.counter_mask
= (1ULL << eax
.split
.bit_width
) - 1;
1425 * Quirk: v2 perfmon does not report fixed-purpose counters, so
1426 * assume at least 3 counters:
1428 x86_pmu
.num_counters_fixed
= max((int)edx
.split
.num_counters_fixed
, 3);
1431 * Install the hw-cache-events table:
1433 switch (boot_cpu_data
.x86_model
) {
1434 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1435 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1436 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1437 case 29: /* six-core 45 nm xeon "Dunnington" */
1438 memcpy(hw_cache_event_ids
, core2_hw_cache_event_ids
,
1439 sizeof(hw_cache_event_ids
));
1441 pr_cont("Core2 events, ");
1445 memcpy(hw_cache_event_ids
, nehalem_hw_cache_event_ids
,
1446 sizeof(hw_cache_event_ids
));
1448 pr_cont("Nehalem/Corei7 events, ");
1451 memcpy(hw_cache_event_ids
, atom_hw_cache_event_ids
,
1452 sizeof(hw_cache_event_ids
));
1454 pr_cont("Atom events, ");
1460 static int amd_pmu_init(void)
1462 /* Performance-monitoring supported from K7 and later: */
1463 if (boot_cpu_data
.x86
< 6)
1468 /* Events are common for all AMDs */
1469 memcpy(hw_cache_event_ids
, amd_hw_cache_event_ids
,
1470 sizeof(hw_cache_event_ids
));
1475 void __init
init_hw_perf_counters(void)
1479 pr_info("Performance Counters: ");
1481 switch (boot_cpu_data
.x86_vendor
) {
1482 case X86_VENDOR_INTEL
:
1483 err
= intel_pmu_init();
1485 case X86_VENDOR_AMD
:
1486 err
= amd_pmu_init();
1492 pr_cont("no PMU driver, software counters only.\n");
1496 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1498 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1499 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
1500 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1501 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1503 perf_counter_mask
= (1 << x86_pmu
.num_counters
) - 1;
1504 perf_max_counters
= x86_pmu
.num_counters
;
1506 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1507 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
1508 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1509 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1512 perf_counter_mask
|=
1513 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1514 x86_pmu
.intel_ctrl
= perf_counter_mask
;
1516 perf_counters_lapic_init();
1517 register_die_notifier(&perf_counter_nmi_notifier
);
1519 pr_info("... version: %d\n", x86_pmu
.version
);
1520 pr_info("... bit width: %d\n", x86_pmu
.counter_bits
);
1521 pr_info("... generic counters: %d\n", x86_pmu
.num_counters
);
1522 pr_info("... value mask: %016Lx\n", x86_pmu
.counter_mask
);
1523 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1524 pr_info("... fixed-purpose counters: %d\n", x86_pmu
.num_counters_fixed
);
1525 pr_info("... counter mask: %016Lx\n", perf_counter_mask
);
1528 static inline void x86_pmu_read(struct perf_counter
*counter
)
1530 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
1533 static const struct pmu pmu
= {
1534 .enable
= x86_pmu_enable
,
1535 .disable
= x86_pmu_disable
,
1536 .read
= x86_pmu_read
,
1537 .unthrottle
= x86_pmu_unthrottle
,
1540 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
1544 err
= __hw_perf_counter_init(counter
);
1546 return ERR_PTR(err
);
1556 void callchain_store(struct perf_callchain_entry
*entry
, u64 ip
)
1558 if (entry
->nr
< PERF_MAX_STACK_DEPTH
)
1559 entry
->ip
[entry
->nr
++] = ip
;
1562 static DEFINE_PER_CPU(struct perf_callchain_entry
, irq_entry
);
1563 static DEFINE_PER_CPU(struct perf_callchain_entry
, nmi_entry
);
1564 static DEFINE_PER_CPU(int, in_nmi_frame
);
1568 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1570 /* Ignore warnings */
1573 static void backtrace_warning(void *data
, char *msg
)
1575 /* Ignore warnings */
1578 static int backtrace_stack(void *data
, char *name
)
1580 per_cpu(in_nmi_frame
, smp_processor_id()) =
1581 x86_is_stack_id(NMI_STACK
, name
);
1586 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1588 struct perf_callchain_entry
*entry
= data
;
1590 if (per_cpu(in_nmi_frame
, smp_processor_id()))
1594 callchain_store(entry
, addr
);
1597 static const struct stacktrace_ops backtrace_ops
= {
1598 .warning
= backtrace_warning
,
1599 .warning_symbol
= backtrace_warning_symbol
,
1600 .stack
= backtrace_stack
,
1601 .address
= backtrace_address
,
1604 #include "../dumpstack.h"
1607 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1609 callchain_store(entry
, PERF_CONTEXT_KERNEL
);
1610 callchain_store(entry
, regs
->ip
);
1612 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
1616 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1618 static unsigned long
1619 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
1621 unsigned long offset
, addr
= (unsigned long)from
;
1622 int type
= in_nmi() ? KM_NMI
: KM_IRQ0
;
1623 unsigned long size
, len
= 0;
1629 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
1633 offset
= addr
& (PAGE_SIZE
- 1);
1634 size
= min(PAGE_SIZE
- offset
, n
- len
);
1636 map
= kmap_atomic(page
, type
);
1637 memcpy(to
, map
+offset
, size
);
1638 kunmap_atomic(map
, type
);
1650 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1652 unsigned long bytes
;
1654 bytes
= copy_from_user_nmi(frame
, fp
, sizeof(*frame
));
1656 return bytes
== sizeof(*frame
);
1660 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1662 struct stack_frame frame
;
1663 const void __user
*fp
;
1665 if (!user_mode(regs
))
1666 regs
= task_pt_regs(current
);
1668 fp
= (void __user
*)regs
->bp
;
1670 callchain_store(entry
, PERF_CONTEXT_USER
);
1671 callchain_store(entry
, regs
->ip
);
1673 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1674 frame
.next_frame
= NULL
;
1675 frame
.return_address
= 0;
1677 if (!copy_stack_frame(fp
, &frame
))
1680 if ((unsigned long)fp
< regs
->sp
)
1683 callchain_store(entry
, frame
.return_address
);
1684 fp
= frame
.next_frame
;
1689 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1696 is_user
= user_mode(regs
);
1698 if (!current
|| current
->pid
== 0)
1701 if (is_user
&& current
->state
!= TASK_RUNNING
)
1705 perf_callchain_kernel(regs
, entry
);
1708 perf_callchain_user(regs
, entry
);
1711 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1713 struct perf_callchain_entry
*entry
;
1716 entry
= &__get_cpu_var(nmi_entry
);
1718 entry
= &__get_cpu_var(irq_entry
);
1722 perf_do_callchain(regs
, entry
);