2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
37 #define wrmsrl(msr, val) \
39 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
40 (unsigned long)(val)); \
41 native_write_msr((msr), (u32)((u64)(val)), \
42 (u32)((u64)(val) >> 32)); \
47 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
50 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
52 unsigned long offset
, addr
= (unsigned long)from
;
53 unsigned long size
, len
= 0;
59 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
63 offset
= addr
& (PAGE_SIZE
- 1);
64 size
= min(PAGE_SIZE
- offset
, n
- len
);
66 map
= kmap_atomic(page
);
67 memcpy(to
, map
+offset
, size
);
80 struct event_constraint
{
82 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
91 int nb_id
; /* NorthBridge id */
92 int refcnt
; /* reference count */
93 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
94 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
99 #define MAX_LBR_ENTRIES 16
101 struct cpu_hw_events
{
103 * Generic x86 PMC bits
105 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
106 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
107 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
113 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
114 u64 tags
[X86_PMC_IDX_MAX
];
115 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
117 unsigned int group_flag
;
120 * Intel DebugStore bits
122 struct debug_store
*ds
;
130 struct perf_branch_stack lbr_stack
;
131 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
134 * Intel percore register state.
135 * Coordinate shared resources between HT threads.
137 int percore_used
; /* Used by this CPU? */
138 struct intel_percore
*per_core
;
143 struct amd_nb
*amd_nb
;
146 #define __EVENT_CONSTRAINT(c, n, m, w) {\
147 { .idxmsk64 = (n) }, \
153 #define EVENT_CONSTRAINT(c, n, m) \
154 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
157 * Constraint on the Event code.
159 #define INTEL_EVENT_CONSTRAINT(c, n) \
160 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
163 * Constraint on the Event code + UMask + fixed-mask
165 * filter mask to validate fixed counter events.
166 * the following filters disqualify for fixed counters:
170 * The other filters are supported by fixed counters.
171 * The any-thread option is supported starting with v3.
173 #define FIXED_EVENT_CONSTRAINT(c, n) \
174 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
177 * Constraint on the Event code + UMask
179 #define INTEL_UEVENT_CONSTRAINT(c, n) \
180 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
181 #define PEBS_EVENT_CONSTRAINT(c, n) \
182 INTEL_UEVENT_CONSTRAINT(c, n)
184 #define EVENT_CONSTRAINT_END \
185 EVENT_CONSTRAINT(0, 0, 0)
187 #define for_each_event_constraint(e, c) \
188 for ((e) = (c); (e)->weight; (e)++)
191 * Extra registers for specific events.
192 * Some events need large masks and require external MSRs.
193 * Define a mapping to these extra registers.
202 #define EVENT_EXTRA_REG(e, ms, m, vm) { \
205 .config_mask = (m), \
206 .valid_mask = (vm), \
208 #define INTEL_EVENT_EXTRA_REG(event, msr, vm) \
209 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm)
210 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0)
212 union perf_capabilities
{
216 u64 pebs_arch_reg
: 1;
224 * struct x86_pmu - generic x86 pmu
228 * Generic x86 PMC bits
232 int (*handle_irq
)(struct pt_regs
*);
233 void (*disable_all
)(void);
234 void (*enable_all
)(int added
);
235 void (*enable
)(struct perf_event
*);
236 void (*disable
)(struct perf_event
*);
237 int (*hw_config
)(struct perf_event
*event
);
238 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
241 u64 (*event_map
)(int);
244 int num_counters_fixed
;
249 struct event_constraint
*
250 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
251 struct perf_event
*event
);
253 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
254 struct perf_event
*event
);
255 struct event_constraint
*event_constraints
;
256 struct event_constraint
*percore_constraints
;
257 void (*quirks
)(void);
258 int perfctr_second_write
;
260 int (*cpu_prepare
)(int cpu
);
261 void (*cpu_starting
)(int cpu
);
262 void (*cpu_dying
)(int cpu
);
263 void (*cpu_dead
)(int cpu
);
266 * Intel Arch Perfmon v2+
269 union perf_capabilities intel_cap
;
272 * Intel DebugStore bits
275 int bts_active
, pebs_active
;
276 int pebs_record_size
;
277 void (*drain_pebs
)(struct pt_regs
*regs
);
278 struct event_constraint
*pebs_constraints
;
283 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
284 int lbr_nr
; /* hardware stack size */
287 * Extra registers for events
289 struct extra_reg
*extra_regs
;
292 static struct x86_pmu x86_pmu __read_mostly
;
294 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
298 static int x86_perf_event_set_period(struct perf_event
*event
);
301 * Generalized hw caching related hw_event table, filled
302 * in on a per model basis. A value of 0 means
303 * 'not supported', -1 means 'hw_event makes no sense on
304 * this CPU', any other value means the raw hw_event
308 #define C(x) PERF_COUNT_HW_CACHE_##x
310 static u64 __read_mostly hw_cache_event_ids
311 [PERF_COUNT_HW_CACHE_MAX
]
312 [PERF_COUNT_HW_CACHE_OP_MAX
]
313 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
314 static u64 __read_mostly hw_cache_extra_regs
315 [PERF_COUNT_HW_CACHE_MAX
]
316 [PERF_COUNT_HW_CACHE_OP_MAX
]
317 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
320 * Propagate event elapsed time into the generic event.
321 * Can only be executed on the CPU where the event is active.
322 * Returns the delta events processed.
325 x86_perf_event_update(struct perf_event
*event
)
327 struct hw_perf_event
*hwc
= &event
->hw
;
328 int shift
= 64 - x86_pmu
.cntval_bits
;
329 u64 prev_raw_count
, new_raw_count
;
333 if (idx
== X86_PMC_IDX_FIXED_BTS
)
337 * Careful: an NMI might modify the previous event value.
339 * Our tactic to handle this is to first atomically read and
340 * exchange a new raw count - then add that new-prev delta
341 * count to the generic event atomically:
344 prev_raw_count
= local64_read(&hwc
->prev_count
);
345 rdmsrl(hwc
->event_base
, new_raw_count
);
347 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
348 new_raw_count
) != prev_raw_count
)
352 * Now we have the new raw value and have updated the prev
353 * timestamp already. We can now calculate the elapsed delta
354 * (event-)time and add that to the generic event.
356 * Careful, not all hw sign-extends above the physical width
359 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
362 local64_add(delta
, &event
->count
);
363 local64_sub(delta
, &hwc
->period_left
);
365 return new_raw_count
;
368 /* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */
369 static inline int x86_pmu_addr_offset(int index
)
371 if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE
))
376 static inline unsigned int x86_pmu_config_addr(int index
)
378 return x86_pmu
.eventsel
+ x86_pmu_addr_offset(index
);
381 static inline unsigned int x86_pmu_event_addr(int index
)
383 return x86_pmu
.perfctr
+ x86_pmu_addr_offset(index
);
387 * Find and validate any extra registers to set up.
389 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
391 struct extra_reg
*er
;
393 event
->hw
.extra_reg
= 0;
394 event
->hw
.extra_config
= 0;
396 if (!x86_pmu
.extra_regs
)
399 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
400 if (er
->event
!= (config
& er
->config_mask
))
402 if (event
->attr
.config1
& ~er
->valid_mask
)
404 event
->hw
.extra_reg
= er
->msr
;
405 event
->hw
.extra_config
= event
->attr
.config1
;
411 static atomic_t active_events
;
412 static DEFINE_MUTEX(pmc_reserve_mutex
);
414 #ifdef CONFIG_X86_LOCAL_APIC
416 static bool reserve_pmc_hardware(void)
420 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
421 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
425 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
426 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
433 for (i
--; i
>= 0; i
--)
434 release_evntsel_nmi(x86_pmu_config_addr(i
));
436 i
= x86_pmu
.num_counters
;
439 for (i
--; i
>= 0; i
--)
440 release_perfctr_nmi(x86_pmu_event_addr(i
));
445 static void release_pmc_hardware(void)
449 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
450 release_perfctr_nmi(x86_pmu_event_addr(i
));
451 release_evntsel_nmi(x86_pmu_config_addr(i
));
457 static bool reserve_pmc_hardware(void) { return true; }
458 static void release_pmc_hardware(void) {}
462 static bool check_hw_exists(void)
464 u64 val
, val_new
= 0;
468 * Check to see if the BIOS enabled any of the counters, if so
471 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
472 reg
= x86_pmu_config_addr(i
);
473 ret
= rdmsrl_safe(reg
, &val
);
476 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
)
480 if (x86_pmu
.num_counters_fixed
) {
481 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
482 ret
= rdmsrl_safe(reg
, &val
);
485 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
486 if (val
& (0x03 << i
*4))
492 * Now write a value and read it back to see if it matches,
493 * this is needed to detect certain hardware emulators (qemu/kvm)
494 * that don't trap on the MSR access and always return 0s.
497 ret
= checking_wrmsrl(x86_pmu_event_addr(0), val
);
498 ret
|= rdmsrl_safe(x86_pmu_event_addr(0), &val_new
);
499 if (ret
|| val
!= val_new
)
505 printk(KERN_CONT
"Broken BIOS detected, using software events only.\n");
506 printk(KERN_ERR FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg
, val
);
510 printk(KERN_CONT
"Broken PMU hardware detected, using software events only.\n");
514 static void reserve_ds_buffers(void);
515 static void release_ds_buffers(void);
517 static void hw_perf_event_destroy(struct perf_event
*event
)
519 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
520 release_pmc_hardware();
521 release_ds_buffers();
522 mutex_unlock(&pmc_reserve_mutex
);
526 static inline int x86_pmu_initialized(void)
528 return x86_pmu
.handle_irq
!= NULL
;
532 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
534 struct perf_event_attr
*attr
= &event
->attr
;
535 unsigned int cache_type
, cache_op
, cache_result
;
538 config
= attr
->config
;
540 cache_type
= (config
>> 0) & 0xff;
541 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
544 cache_op
= (config
>> 8) & 0xff;
545 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
548 cache_result
= (config
>> 16) & 0xff;
549 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
552 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
561 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
562 return x86_pmu_extra_regs(val
, event
);
565 static int x86_setup_perfctr(struct perf_event
*event
)
567 struct perf_event_attr
*attr
= &event
->attr
;
568 struct hw_perf_event
*hwc
= &event
->hw
;
571 if (!is_sampling_event(event
)) {
572 hwc
->sample_period
= x86_pmu
.max_period
;
573 hwc
->last_period
= hwc
->sample_period
;
574 local64_set(&hwc
->period_left
, hwc
->sample_period
);
577 * If we have a PMU initialized but no APIC
578 * interrupts, we cannot sample hardware
579 * events (user-space has to fall back and
580 * sample via a hrtimer based software event):
586 if (attr
->type
== PERF_TYPE_RAW
)
587 return x86_pmu_extra_regs(event
->attr
.config
, event
);
589 if (attr
->type
== PERF_TYPE_HW_CACHE
)
590 return set_ext_hw_attr(hwc
, event
);
592 if (attr
->config
>= x86_pmu
.max_events
)
598 config
= x86_pmu
.event_map(attr
->config
);
609 if ((attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
) &&
610 (hwc
->sample_period
== 1)) {
611 /* BTS is not supported by this architecture. */
612 if (!x86_pmu
.bts_active
)
615 /* BTS is currently only allowed for user-mode. */
616 if (!attr
->exclude_kernel
)
620 hwc
->config
|= config
;
625 static int x86_pmu_hw_config(struct perf_event
*event
)
627 if (event
->attr
.precise_ip
) {
630 /* Support for constant skid */
631 if (x86_pmu
.pebs_active
) {
634 /* Support for IP fixup */
639 if (event
->attr
.precise_ip
> precise
)
645 * (keep 'enabled' bit clear for now)
647 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
650 * Count user and OS events unless requested not to
652 if (!event
->attr
.exclude_user
)
653 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
654 if (!event
->attr
.exclude_kernel
)
655 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
657 if (event
->attr
.type
== PERF_TYPE_RAW
)
658 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
660 return x86_setup_perfctr(event
);
664 * Setup the hardware configuration for a given attr_type
666 static int __x86_pmu_event_init(struct perf_event
*event
)
670 if (!x86_pmu_initialized())
674 if (!atomic_inc_not_zero(&active_events
)) {
675 mutex_lock(&pmc_reserve_mutex
);
676 if (atomic_read(&active_events
) == 0) {
677 if (!reserve_pmc_hardware())
680 reserve_ds_buffers();
683 atomic_inc(&active_events
);
684 mutex_unlock(&pmc_reserve_mutex
);
689 event
->destroy
= hw_perf_event_destroy
;
692 event
->hw
.last_cpu
= -1;
693 event
->hw
.last_tag
= ~0ULL;
695 return x86_pmu
.hw_config(event
);
698 static void x86_pmu_disable_all(void)
700 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
703 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
706 if (!test_bit(idx
, cpuc
->active_mask
))
708 rdmsrl(x86_pmu_config_addr(idx
), val
);
709 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
711 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
712 wrmsrl(x86_pmu_config_addr(idx
), val
);
716 static void x86_pmu_disable(struct pmu
*pmu
)
718 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
720 if (!x86_pmu_initialized())
730 x86_pmu
.disable_all();
733 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
737 wrmsrl(hwc
->extra_reg
, hwc
->extra_config
);
738 wrmsrl(hwc
->config_base
, hwc
->config
| enable_mask
);
741 static void x86_pmu_enable_all(int added
)
743 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
746 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
747 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
749 if (!test_bit(idx
, cpuc
->active_mask
))
752 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
756 static struct pmu pmu
;
758 static inline int is_x86_event(struct perf_event
*event
)
760 return event
->pmu
== &pmu
;
763 static int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
765 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
766 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
767 int i
, j
, w
, wmax
, num
= 0;
768 struct hw_perf_event
*hwc
;
770 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
772 for (i
= 0; i
< n
; i
++) {
773 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
778 * fastpath, try to reuse previous register
780 for (i
= 0; i
< n
; i
++) {
781 hwc
= &cpuc
->event_list
[i
]->hw
;
788 /* constraint still honored */
789 if (!test_bit(hwc
->idx
, c
->idxmsk
))
792 /* not already used */
793 if (test_bit(hwc
->idx
, used_mask
))
796 __set_bit(hwc
->idx
, used_mask
);
798 assign
[i
] = hwc
->idx
;
807 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
810 * weight = number of possible counters
812 * 1 = most constrained, only works on one counter
813 * wmax = least constrained, works on any counter
815 * assign events to counters starting with most
816 * constrained events.
818 wmax
= x86_pmu
.num_counters
;
821 * when fixed event counters are present,
822 * wmax is incremented by 1 to account
823 * for one more choice
825 if (x86_pmu
.num_counters_fixed
)
828 for (w
= 1, num
= n
; num
&& w
<= wmax
; w
++) {
830 for (i
= 0; num
&& i
< n
; i
++) {
832 hwc
= &cpuc
->event_list
[i
]->hw
;
837 for_each_set_bit(j
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
838 if (!test_bit(j
, used_mask
))
842 if (j
== X86_PMC_IDX_MAX
)
845 __set_bit(j
, used_mask
);
854 * scheduling failed or is just a simulation,
855 * free resources if necessary
857 if (!assign
|| num
) {
858 for (i
= 0; i
< n
; i
++) {
859 if (x86_pmu
.put_event_constraints
)
860 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
863 return num
? -ENOSPC
: 0;
867 * dogrp: true if must collect siblings events (group)
868 * returns total number of events and error code
870 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
872 struct perf_event
*event
;
875 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
877 /* current number of events already accepted */
880 if (is_x86_event(leader
)) {
883 cpuc
->event_list
[n
] = leader
;
889 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
890 if (!is_x86_event(event
) ||
891 event
->state
<= PERF_EVENT_STATE_OFF
)
897 cpuc
->event_list
[n
] = event
;
903 static inline void x86_assign_hw_event(struct perf_event
*event
,
904 struct cpu_hw_events
*cpuc
, int i
)
906 struct hw_perf_event
*hwc
= &event
->hw
;
908 hwc
->idx
= cpuc
->assign
[i
];
909 hwc
->last_cpu
= smp_processor_id();
910 hwc
->last_tag
= ++cpuc
->tags
[i
];
912 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
913 hwc
->config_base
= 0;
915 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
916 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
917 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
;
919 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
920 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
924 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
925 struct cpu_hw_events
*cpuc
,
928 return hwc
->idx
== cpuc
->assign
[i
] &&
929 hwc
->last_cpu
== smp_processor_id() &&
930 hwc
->last_tag
== cpuc
->tags
[i
];
933 static void x86_pmu_start(struct perf_event
*event
, int flags
);
934 static void x86_pmu_stop(struct perf_event
*event
, int flags
);
936 static void x86_pmu_enable(struct pmu
*pmu
)
938 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
939 struct perf_event
*event
;
940 struct hw_perf_event
*hwc
;
941 int i
, added
= cpuc
->n_added
;
943 if (!x86_pmu_initialized())
950 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
952 * apply assignment obtained either from
953 * hw_perf_group_sched_in() or x86_pmu_enable()
955 * step1: save events moving to new counters
956 * step2: reprogram moved events into new counters
958 for (i
= 0; i
< n_running
; i
++) {
959 event
= cpuc
->event_list
[i
];
963 * we can avoid reprogramming counter if:
964 * - assigned same counter as last time
965 * - running on same CPU as last time
966 * - no other event has used the counter since
968 if (hwc
->idx
== -1 ||
969 match_prev_assignment(hwc
, cpuc
, i
))
973 * Ensure we don't accidentally enable a stopped
974 * counter simply because we rescheduled.
976 if (hwc
->state
& PERF_HES_STOPPED
)
977 hwc
->state
|= PERF_HES_ARCH
;
979 x86_pmu_stop(event
, PERF_EF_UPDATE
);
982 for (i
= 0; i
< cpuc
->n_events
; i
++) {
983 event
= cpuc
->event_list
[i
];
986 if (!match_prev_assignment(hwc
, cpuc
, i
))
987 x86_assign_hw_event(event
, cpuc
, i
);
988 else if (i
< n_running
)
991 if (hwc
->state
& PERF_HES_ARCH
)
994 x86_pmu_start(event
, PERF_EF_RELOAD
);
997 perf_events_lapic_init();
1003 x86_pmu
.enable_all(added
);
1006 static inline void x86_pmu_disable_event(struct perf_event
*event
)
1008 struct hw_perf_event
*hwc
= &event
->hw
;
1010 wrmsrl(hwc
->config_base
, hwc
->config
);
1013 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1016 * Set the next IRQ period, based on the hwc->period_left value.
1017 * To be called with the event disabled in hw:
1020 x86_perf_event_set_period(struct perf_event
*event
)
1022 struct hw_perf_event
*hwc
= &event
->hw
;
1023 s64 left
= local64_read(&hwc
->period_left
);
1024 s64 period
= hwc
->sample_period
;
1025 int ret
= 0, idx
= hwc
->idx
;
1027 if (idx
== X86_PMC_IDX_FIXED_BTS
)
1031 * If we are way outside a reasonable range then just skip forward:
1033 if (unlikely(left
<= -period
)) {
1035 local64_set(&hwc
->period_left
, left
);
1036 hwc
->last_period
= period
;
1040 if (unlikely(left
<= 0)) {
1042 local64_set(&hwc
->period_left
, left
);
1043 hwc
->last_period
= period
;
1047 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1049 if (unlikely(left
< 2))
1052 if (left
> x86_pmu
.max_period
)
1053 left
= x86_pmu
.max_period
;
1055 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1058 * The hw event starts counting from this event offset,
1059 * mark it to be able to extra future deltas:
1061 local64_set(&hwc
->prev_count
, (u64
)-left
);
1063 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1066 * Due to erratum on certan cpu we need
1067 * a second write to be sure the register
1068 * is updated properly
1070 if (x86_pmu
.perfctr_second_write
) {
1071 wrmsrl(hwc
->event_base
,
1072 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1075 perf_event_update_userpage(event
);
1080 static void x86_pmu_enable_event(struct perf_event
*event
)
1082 if (__this_cpu_read(cpu_hw_events
.enabled
))
1083 __x86_pmu_enable_event(&event
->hw
,
1084 ARCH_PERFMON_EVENTSEL_ENABLE
);
1088 * Add a single event to the PMU.
1090 * The event is added to the group of enabled events
1091 * but only if it can be scehduled with existing events.
1093 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1095 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1096 struct hw_perf_event
*hwc
;
1097 int assign
[X86_PMC_IDX_MAX
];
1102 perf_pmu_disable(event
->pmu
);
1103 n0
= cpuc
->n_events
;
1104 ret
= n
= collect_events(cpuc
, event
, false);
1108 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1109 if (!(flags
& PERF_EF_START
))
1110 hwc
->state
|= PERF_HES_ARCH
;
1113 * If group events scheduling transaction was started,
1114 * skip the schedulability test here, it will be peformed
1115 * at commit time (->commit_txn) as a whole
1117 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1120 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1124 * copy new assignment, now we know it is possible
1125 * will be used by hw_perf_enable()
1127 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1131 cpuc
->n_added
+= n
- n0
;
1132 cpuc
->n_txn
+= n
- n0
;
1136 perf_pmu_enable(event
->pmu
);
1140 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1142 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1143 int idx
= event
->hw
.idx
;
1145 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1148 if (WARN_ON_ONCE(idx
== -1))
1151 if (flags
& PERF_EF_RELOAD
) {
1152 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1153 x86_perf_event_set_period(event
);
1156 event
->hw
.state
= 0;
1158 cpuc
->events
[idx
] = event
;
1159 __set_bit(idx
, cpuc
->active_mask
);
1160 __set_bit(idx
, cpuc
->running
);
1161 x86_pmu
.enable(event
);
1162 perf_event_update_userpage(event
);
1165 void perf_event_print_debug(void)
1167 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1169 struct cpu_hw_events
*cpuc
;
1170 unsigned long flags
;
1173 if (!x86_pmu
.num_counters
)
1176 local_irq_save(flags
);
1178 cpu
= smp_processor_id();
1179 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1181 if (x86_pmu
.version
>= 2) {
1182 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1183 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1184 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1185 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1186 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1189 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1190 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1191 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1192 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1193 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1195 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1197 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1198 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1199 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1201 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1203 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1204 cpu
, idx
, pmc_ctrl
);
1205 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1206 cpu
, idx
, pmc_count
);
1207 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1208 cpu
, idx
, prev_left
);
1210 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1211 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1213 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1214 cpu
, idx
, pmc_count
);
1216 local_irq_restore(flags
);
1219 static void x86_pmu_stop(struct perf_event
*event
, int flags
)
1221 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1222 struct hw_perf_event
*hwc
= &event
->hw
;
1224 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1225 x86_pmu
.disable(event
);
1226 cpuc
->events
[hwc
->idx
] = NULL
;
1227 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1228 hwc
->state
|= PERF_HES_STOPPED
;
1231 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1233 * Drain the remaining delta count out of a event
1234 * that we are disabling:
1236 x86_perf_event_update(event
);
1237 hwc
->state
|= PERF_HES_UPTODATE
;
1241 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1243 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1247 * If we're called during a txn, we don't need to do anything.
1248 * The events never got scheduled and ->cancel_txn will truncate
1251 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1254 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1256 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1257 if (event
== cpuc
->event_list
[i
]) {
1259 if (x86_pmu
.put_event_constraints
)
1260 x86_pmu
.put_event_constraints(cpuc
, event
);
1262 while (++i
< cpuc
->n_events
)
1263 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1269 perf_event_update_userpage(event
);
1272 static int x86_pmu_handle_irq(struct pt_regs
*regs
)
1274 struct perf_sample_data data
;
1275 struct cpu_hw_events
*cpuc
;
1276 struct perf_event
*event
;
1277 int idx
, handled
= 0;
1280 perf_sample_data_init(&data
, 0);
1282 cpuc
= &__get_cpu_var(cpu_hw_events
);
1284 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1285 if (!test_bit(idx
, cpuc
->active_mask
)) {
1287 * Though we deactivated the counter some cpus
1288 * might still deliver spurious interrupts still
1289 * in flight. Catch them:
1291 if (__test_and_clear_bit(idx
, cpuc
->running
))
1296 event
= cpuc
->events
[idx
];
1298 val
= x86_perf_event_update(event
);
1299 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1306 data
.period
= event
->hw
.last_period
;
1308 if (!x86_perf_event_set_period(event
))
1311 if (perf_event_overflow(event
, 1, &data
, regs
))
1312 x86_pmu_stop(event
, 0);
1316 inc_irq_stat(apic_perf_irqs
);
1321 void perf_events_lapic_init(void)
1323 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1327 * Always use NMI for PMU
1329 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1332 struct pmu_nmi_state
{
1333 unsigned int marked
;
1337 static DEFINE_PER_CPU(struct pmu_nmi_state
, pmu_nmi
);
1339 static int __kprobes
1340 perf_event_nmi_handler(struct notifier_block
*self
,
1341 unsigned long cmd
, void *__args
)
1343 struct die_args
*args
= __args
;
1344 unsigned int this_nmi
;
1347 if (!atomic_read(&active_events
))
1353 case DIE_NMIUNKNOWN
:
1354 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1355 if (this_nmi
!= __this_cpu_read(pmu_nmi
.marked
))
1356 /* let the kernel handle the unknown nmi */
1359 * This one is a PMU back-to-back nmi. Two events
1360 * trigger 'simultaneously' raising two back-to-back
1361 * NMIs. If the first NMI handles both, the latter
1362 * will be empty and daze the CPU. So, we drop it to
1363 * avoid false-positive 'unknown nmi' messages.
1370 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1372 handled
= x86_pmu
.handle_irq(args
->regs
);
1376 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1377 if ((handled
> 1) ||
1378 /* the next nmi could be a back-to-back nmi */
1379 ((__this_cpu_read(pmu_nmi
.marked
) == this_nmi
) &&
1380 (__this_cpu_read(pmu_nmi
.handled
) > 1))) {
1382 * We could have two subsequent back-to-back nmis: The
1383 * first handles more than one counter, the 2nd
1384 * handles only one counter and the 3rd handles no
1387 * This is the 2nd nmi because the previous was
1388 * handling more than one counter. We will mark the
1389 * next (3rd) and then drop it if unhandled.
1391 __this_cpu_write(pmu_nmi
.marked
, this_nmi
+ 1);
1392 __this_cpu_write(pmu_nmi
.handled
, handled
);
1398 static __read_mostly
struct notifier_block perf_event_nmi_notifier
= {
1399 .notifier_call
= perf_event_nmi_handler
,
1401 .priority
= NMI_LOCAL_LOW_PRIOR
,
1404 static struct event_constraint unconstrained
;
1405 static struct event_constraint emptyconstraint
;
1407 static struct event_constraint
*
1408 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
)
1410 struct event_constraint
*c
;
1412 if (x86_pmu
.event_constraints
) {
1413 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1414 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
1419 return &unconstrained
;
1422 #include "perf_event_amd.c"
1423 #include "perf_event_p6.c"
1424 #include "perf_event_p4.c"
1425 #include "perf_event_intel_lbr.c"
1426 #include "perf_event_intel_ds.c"
1427 #include "perf_event_intel.c"
1429 static int __cpuinit
1430 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1432 unsigned int cpu
= (long)hcpu
;
1433 int ret
= NOTIFY_OK
;
1435 switch (action
& ~CPU_TASKS_FROZEN
) {
1436 case CPU_UP_PREPARE
:
1437 if (x86_pmu
.cpu_prepare
)
1438 ret
= x86_pmu
.cpu_prepare(cpu
);
1442 if (x86_pmu
.cpu_starting
)
1443 x86_pmu
.cpu_starting(cpu
);
1447 if (x86_pmu
.cpu_dying
)
1448 x86_pmu
.cpu_dying(cpu
);
1451 case CPU_UP_CANCELED
:
1453 if (x86_pmu
.cpu_dead
)
1454 x86_pmu
.cpu_dead(cpu
);
1464 static void __init
pmu_check_apic(void)
1470 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1471 pr_info("no hardware sampling interrupt available.\n");
1474 static int __init
init_hw_perf_events(void)
1476 struct event_constraint
*c
;
1479 pr_info("Performance Events: ");
1481 switch (boot_cpu_data
.x86_vendor
) {
1482 case X86_VENDOR_INTEL
:
1483 err
= intel_pmu_init();
1485 case X86_VENDOR_AMD
:
1486 err
= amd_pmu_init();
1492 pr_cont("no PMU driver, software events only.\n");
1498 /* sanity check that the hardware exists or is emulated */
1499 if (!check_hw_exists())
1502 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1507 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1508 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1509 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1510 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1512 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1514 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1515 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1516 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1517 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1520 x86_pmu
.intel_ctrl
|=
1521 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1523 perf_events_lapic_init();
1524 register_die_notifier(&perf_event_nmi_notifier
);
1526 unconstrained
= (struct event_constraint
)
1527 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1528 0, x86_pmu
.num_counters
);
1530 if (x86_pmu
.event_constraints
) {
1531 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1532 if (c
->cmask
!= X86_RAW_EVENT_MASK
)
1535 c
->idxmsk64
|= (1ULL << x86_pmu
.num_counters
) - 1;
1536 c
->weight
+= x86_pmu
.num_counters
;
1540 pr_info("... version: %d\n", x86_pmu
.version
);
1541 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1542 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1543 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1544 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1545 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1546 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1548 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1549 perf_cpu_notifier(x86_pmu_notifier
);
1553 early_initcall(init_hw_perf_events
);
1555 static inline void x86_pmu_read(struct perf_event
*event
)
1557 x86_perf_event_update(event
);
1561 * Start group events scheduling transaction
1562 * Set the flag to make pmu::enable() not perform the
1563 * schedulability test, it will be performed at commit time
1565 static void x86_pmu_start_txn(struct pmu
*pmu
)
1567 perf_pmu_disable(pmu
);
1568 __this_cpu_or(cpu_hw_events
.group_flag
, PERF_EVENT_TXN
);
1569 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1573 * Stop group events scheduling transaction
1574 * Clear the flag and pmu::enable() will perform the
1575 * schedulability test.
1577 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1579 __this_cpu_and(cpu_hw_events
.group_flag
, ~PERF_EVENT_TXN
);
1581 * Truncate the collected events.
1583 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1584 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1585 perf_pmu_enable(pmu
);
1589 * Commit group events scheduling transaction
1590 * Perform the group schedulability test as a whole
1591 * Return 0 if success
1593 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1595 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1596 int assign
[X86_PMC_IDX_MAX
];
1601 if (!x86_pmu_initialized())
1604 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1609 * copy new assignment, now we know it is possible
1610 * will be used by hw_perf_enable()
1612 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1614 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1615 perf_pmu_enable(pmu
);
1620 * validate that we can schedule this event
1622 static int validate_event(struct perf_event
*event
)
1624 struct cpu_hw_events
*fake_cpuc
;
1625 struct event_constraint
*c
;
1628 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1632 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1634 if (!c
|| !c
->weight
)
1637 if (x86_pmu
.put_event_constraints
)
1638 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1646 * validate a single event group
1648 * validation include:
1649 * - check events are compatible which each other
1650 * - events do not compete for the same counter
1651 * - number of events <= number of counters
1653 * validation ensures the group can be loaded onto the
1654 * PMU if it was the only group available.
1656 static int validate_group(struct perf_event
*event
)
1658 struct perf_event
*leader
= event
->group_leader
;
1659 struct cpu_hw_events
*fake_cpuc
;
1663 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1668 * the event is not yet connected with its
1669 * siblings therefore we must first collect
1670 * existing siblings, then add the new event
1671 * before we can simulate the scheduling
1674 n
= collect_events(fake_cpuc
, leader
, true);
1678 fake_cpuc
->n_events
= n
;
1679 n
= collect_events(fake_cpuc
, event
, false);
1683 fake_cpuc
->n_events
= n
;
1685 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1693 static int x86_pmu_event_init(struct perf_event
*event
)
1698 switch (event
->attr
.type
) {
1700 case PERF_TYPE_HARDWARE
:
1701 case PERF_TYPE_HW_CACHE
:
1708 err
= __x86_pmu_event_init(event
);
1711 * we temporarily connect event to its pmu
1712 * such that validate_group() can classify
1713 * it as an x86 event using is_x86_event()
1718 if (event
->group_leader
!= event
)
1719 err
= validate_group(event
);
1721 err
= validate_event(event
);
1727 event
->destroy(event
);
1733 static struct pmu pmu
= {
1734 .pmu_enable
= x86_pmu_enable
,
1735 .pmu_disable
= x86_pmu_disable
,
1737 .event_init
= x86_pmu_event_init
,
1741 .start
= x86_pmu_start
,
1742 .stop
= x86_pmu_stop
,
1743 .read
= x86_pmu_read
,
1745 .start_txn
= x86_pmu_start_txn
,
1746 .cancel_txn
= x86_pmu_cancel_txn
,
1747 .commit_txn
= x86_pmu_commit_txn
,
1755 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1757 /* Ignore warnings */
1760 static void backtrace_warning(void *data
, char *msg
)
1762 /* Ignore warnings */
1765 static int backtrace_stack(void *data
, char *name
)
1770 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1772 struct perf_callchain_entry
*entry
= data
;
1774 perf_callchain_store(entry
, addr
);
1777 static const struct stacktrace_ops backtrace_ops
= {
1778 .warning
= backtrace_warning
,
1779 .warning_symbol
= backtrace_warning_symbol
,
1780 .stack
= backtrace_stack
,
1781 .address
= backtrace_address
,
1782 .walk_stack
= print_context_stack_bp
,
1786 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1788 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1789 /* TODO: We don't support guest os callchain now */
1793 perf_callchain_store(entry
, regs
->ip
);
1795 dump_trace(NULL
, regs
, NULL
, &backtrace_ops
, entry
);
1798 #ifdef CONFIG_COMPAT
1800 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1802 /* 32-bit process in 64-bit kernel. */
1803 struct stack_frame_ia32 frame
;
1804 const void __user
*fp
;
1806 if (!test_thread_flag(TIF_IA32
))
1809 fp
= compat_ptr(regs
->bp
);
1810 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1811 unsigned long bytes
;
1812 frame
.next_frame
= 0;
1813 frame
.return_address
= 0;
1815 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1816 if (bytes
!= sizeof(frame
))
1819 if (fp
< compat_ptr(regs
->sp
))
1822 perf_callchain_store(entry
, frame
.return_address
);
1823 fp
= compat_ptr(frame
.next_frame
);
1829 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1836 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1838 struct stack_frame frame
;
1839 const void __user
*fp
;
1841 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1842 /* TODO: We don't support guest os callchain now */
1846 fp
= (void __user
*)regs
->bp
;
1848 perf_callchain_store(entry
, regs
->ip
);
1850 if (perf_callchain_user32(regs
, entry
))
1853 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1854 unsigned long bytes
;
1855 frame
.next_frame
= NULL
;
1856 frame
.return_address
= 0;
1858 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1859 if (bytes
!= sizeof(frame
))
1862 if ((unsigned long)fp
< regs
->sp
)
1865 perf_callchain_store(entry
, frame
.return_address
);
1866 fp
= frame
.next_frame
;
1870 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1874 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
1875 ip
= perf_guest_cbs
->get_guest_ip();
1877 ip
= instruction_pointer(regs
);
1882 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1886 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1887 if (perf_guest_cbs
->is_user_mode())
1888 misc
|= PERF_RECORD_MISC_GUEST_USER
;
1890 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
1892 if (user_mode(regs
))
1893 misc
|= PERF_RECORD_MISC_USER
;
1895 misc
|= PERF_RECORD_MISC_KERNEL
;
1898 if (regs
->flags
& PERF_EFLAGS_EXACT
)
1899 misc
|= PERF_RECORD_MISC_EXACT_IP
;