2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/timer.h>
36 #include "perf_event.h"
38 struct x86_pmu x86_pmu __read_mostly
;
40 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
44 u64 __read_mostly hw_cache_event_ids
45 [PERF_COUNT_HW_CACHE_MAX
]
46 [PERF_COUNT_HW_CACHE_OP_MAX
]
47 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
48 u64 __read_mostly hw_cache_extra_regs
49 [PERF_COUNT_HW_CACHE_MAX
]
50 [PERF_COUNT_HW_CACHE_OP_MAX
]
51 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
54 * Propagate event elapsed time into the generic event.
55 * Can only be executed on the CPU where the event is active.
56 * Returns the delta events processed.
58 u64
x86_perf_event_update(struct perf_event
*event
)
60 struct hw_perf_event
*hwc
= &event
->hw
;
61 int shift
= 64 - x86_pmu
.cntval_bits
;
62 u64 prev_raw_count
, new_raw_count
;
66 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
70 * Careful: an NMI might modify the previous event value.
72 * Our tactic to handle this is to first atomically read and
73 * exchange a new raw count - then add that new-prev delta
74 * count to the generic event atomically:
77 prev_raw_count
= local64_read(&hwc
->prev_count
);
78 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
80 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
81 new_raw_count
) != prev_raw_count
)
85 * Now we have the new raw value and have updated the prev
86 * timestamp already. We can now calculate the elapsed delta
87 * (event-)time and add that to the generic event.
89 * Careful, not all hw sign-extends above the physical width
92 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
95 local64_add(delta
, &event
->count
);
96 local64_sub(delta
, &hwc
->period_left
);
102 * Find and validate any extra registers to set up.
104 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
106 struct hw_perf_event_extra
*reg
;
107 struct extra_reg
*er
;
109 reg
= &event
->hw
.extra_reg
;
111 if (!x86_pmu
.extra_regs
)
114 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
115 if (er
->event
!= (config
& er
->config_mask
))
117 if (event
->attr
.config1
& ~er
->valid_mask
)
121 reg
->config
= event
->attr
.config1
;
128 static atomic_t active_events
;
129 static DEFINE_MUTEX(pmc_reserve_mutex
);
131 #ifdef CONFIG_X86_LOCAL_APIC
133 static bool reserve_pmc_hardware(void)
137 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
138 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
142 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
143 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
150 for (i
--; i
>= 0; i
--)
151 release_evntsel_nmi(x86_pmu_config_addr(i
));
153 i
= x86_pmu
.num_counters
;
156 for (i
--; i
>= 0; i
--)
157 release_perfctr_nmi(x86_pmu_event_addr(i
));
162 static void release_pmc_hardware(void)
166 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
167 release_perfctr_nmi(x86_pmu_event_addr(i
));
168 release_evntsel_nmi(x86_pmu_config_addr(i
));
174 static bool reserve_pmc_hardware(void) { return true; }
175 static void release_pmc_hardware(void) {}
179 static bool check_hw_exists(void)
181 u64 val
, val_new
= ~0;
185 * Check to see if the BIOS enabled any of the counters, if so
188 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
189 reg
= x86_pmu_config_addr(i
);
190 ret
= rdmsrl_safe(reg
, &val
);
193 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
)
197 if (x86_pmu
.num_counters_fixed
) {
198 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
199 ret
= rdmsrl_safe(reg
, &val
);
202 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
203 if (val
& (0x03 << i
*4))
209 * Now write a value and read it back to see if it matches,
210 * this is needed to detect certain hardware emulators (qemu/kvm)
211 * that don't trap on the MSR access and always return 0s.
214 reg
= x86_pmu_event_addr(0);
215 ret
= wrmsrl_safe(reg
, val
);
216 ret
|= rdmsrl_safe(reg
, &val_new
);
217 if (ret
|| val
!= val_new
)
224 * We still allow the PMU driver to operate:
226 printk(KERN_CONT
"Broken BIOS detected, complain to your hardware vendor.\n");
227 printk(KERN_ERR FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg
, val
);
232 printk(KERN_CONT
"Broken PMU hardware detected, using software events only.\n");
233 printk(KERN_ERR
"Failed to access perfctr msr (MSR %x is %Lx)\n", reg
, val_new
);
238 static void hw_perf_event_destroy(struct perf_event
*event
)
240 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
241 release_pmc_hardware();
242 release_ds_buffers();
243 mutex_unlock(&pmc_reserve_mutex
);
247 static inline int x86_pmu_initialized(void)
249 return x86_pmu
.handle_irq
!= NULL
;
253 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
255 struct perf_event_attr
*attr
= &event
->attr
;
256 unsigned int cache_type
, cache_op
, cache_result
;
259 config
= attr
->config
;
261 cache_type
= (config
>> 0) & 0xff;
262 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
265 cache_op
= (config
>> 8) & 0xff;
266 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
269 cache_result
= (config
>> 16) & 0xff;
270 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
273 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
282 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
283 return x86_pmu_extra_regs(val
, event
);
286 int x86_setup_perfctr(struct perf_event
*event
)
288 struct perf_event_attr
*attr
= &event
->attr
;
289 struct hw_perf_event
*hwc
= &event
->hw
;
292 if (!is_sampling_event(event
)) {
293 hwc
->sample_period
= x86_pmu
.max_period
;
294 hwc
->last_period
= hwc
->sample_period
;
295 local64_set(&hwc
->period_left
, hwc
->sample_period
);
298 * If we have a PMU initialized but no APIC
299 * interrupts, we cannot sample hardware
300 * events (user-space has to fall back and
301 * sample via a hrtimer based software event):
307 if (attr
->type
== PERF_TYPE_RAW
)
308 return x86_pmu_extra_regs(event
->attr
.config
, event
);
310 if (attr
->type
== PERF_TYPE_HW_CACHE
)
311 return set_ext_hw_attr(hwc
, event
);
313 if (attr
->config
>= x86_pmu
.max_events
)
319 config
= x86_pmu
.event_map(attr
->config
);
330 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
331 !attr
->freq
&& hwc
->sample_period
== 1) {
332 /* BTS is not supported by this architecture. */
333 if (!x86_pmu
.bts_active
)
336 /* BTS is currently only allowed for user-mode. */
337 if (!attr
->exclude_kernel
)
341 hwc
->config
|= config
;
347 * check that branch_sample_type is compatible with
348 * settings needed for precise_ip > 1 which implies
349 * using the LBR to capture ALL taken branches at the
350 * priv levels of the measurement
352 static inline int precise_br_compat(struct perf_event
*event
)
354 u64 m
= event
->attr
.branch_sample_type
;
357 /* must capture all branches */
358 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
361 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
363 if (!event
->attr
.exclude_user
)
364 b
|= PERF_SAMPLE_BRANCH_USER
;
366 if (!event
->attr
.exclude_kernel
)
367 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
370 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
376 int x86_pmu_hw_config(struct perf_event
*event
)
378 if (event
->attr
.precise_ip
) {
381 /* Support for constant skid */
382 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
385 /* Support for IP fixup */
390 if (event
->attr
.precise_ip
> precise
)
393 * check that PEBS LBR correction does not conflict with
394 * whatever the user is asking with attr->branch_sample_type
396 if (event
->attr
.precise_ip
> 1) {
397 u64
*br_type
= &event
->attr
.branch_sample_type
;
399 if (has_branch_stack(event
)) {
400 if (!precise_br_compat(event
))
403 /* branch_sample_type is compatible */
407 * user did not specify branch_sample_type
409 * For PEBS fixups, we capture all
410 * the branches at the priv level of the
413 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
415 if (!event
->attr
.exclude_user
)
416 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
418 if (!event
->attr
.exclude_kernel
)
419 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
426 * (keep 'enabled' bit clear for now)
428 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
431 * Count user and OS events unless requested not to
433 if (!event
->attr
.exclude_user
)
434 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
435 if (!event
->attr
.exclude_kernel
)
436 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
438 if (event
->attr
.type
== PERF_TYPE_RAW
)
439 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
441 return x86_setup_perfctr(event
);
445 * Setup the hardware configuration for a given attr_type
447 static int __x86_pmu_event_init(struct perf_event
*event
)
451 if (!x86_pmu_initialized())
455 if (!atomic_inc_not_zero(&active_events
)) {
456 mutex_lock(&pmc_reserve_mutex
);
457 if (atomic_read(&active_events
) == 0) {
458 if (!reserve_pmc_hardware())
461 reserve_ds_buffers();
464 atomic_inc(&active_events
);
465 mutex_unlock(&pmc_reserve_mutex
);
470 event
->destroy
= hw_perf_event_destroy
;
473 event
->hw
.last_cpu
= -1;
474 event
->hw
.last_tag
= ~0ULL;
477 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
478 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
480 return x86_pmu
.hw_config(event
);
483 void x86_pmu_disable_all(void)
485 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
488 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
491 if (!test_bit(idx
, cpuc
->active_mask
))
493 rdmsrl(x86_pmu_config_addr(idx
), val
);
494 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
496 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
497 wrmsrl(x86_pmu_config_addr(idx
), val
);
501 static void x86_pmu_disable(struct pmu
*pmu
)
503 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
505 if (!x86_pmu_initialized())
515 x86_pmu
.disable_all();
518 void x86_pmu_enable_all(int added
)
520 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
523 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
524 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
526 if (!test_bit(idx
, cpuc
->active_mask
))
529 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
533 static struct pmu pmu
;
535 static inline int is_x86_event(struct perf_event
*event
)
537 return event
->pmu
== &pmu
;
541 * Event scheduler state:
543 * Assign events iterating over all events and counters, beginning
544 * with events with least weights first. Keep the current iterator
545 * state in struct sched_state.
549 int event
; /* event index */
550 int counter
; /* counter index */
551 int unassigned
; /* number of events to be assigned left */
552 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
555 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
556 #define SCHED_STATES_MAX 2
561 struct event_constraint
**constraints
;
562 struct sched_state state
;
564 struct sched_state saved
[SCHED_STATES_MAX
];
568 * Initialize interator that runs through all events and counters.
570 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**c
,
571 int num
, int wmin
, int wmax
)
575 memset(sched
, 0, sizeof(*sched
));
576 sched
->max_events
= num
;
577 sched
->max_weight
= wmax
;
578 sched
->constraints
= c
;
580 for (idx
= 0; idx
< num
; idx
++) {
581 if (c
[idx
]->weight
== wmin
)
585 sched
->state
.event
= idx
; /* start with min weight */
586 sched
->state
.weight
= wmin
;
587 sched
->state
.unassigned
= num
;
590 static void perf_sched_save_state(struct perf_sched
*sched
)
592 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
595 sched
->saved
[sched
->saved_states
] = sched
->state
;
596 sched
->saved_states
++;
599 static bool perf_sched_restore_state(struct perf_sched
*sched
)
601 if (!sched
->saved_states
)
604 sched
->saved_states
--;
605 sched
->state
= sched
->saved
[sched
->saved_states
];
607 /* continue with next counter: */
608 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
614 * Select a counter for the current event to schedule. Return true on
617 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
619 struct event_constraint
*c
;
622 if (!sched
->state
.unassigned
)
625 if (sched
->state
.event
>= sched
->max_events
)
628 c
= sched
->constraints
[sched
->state
.event
];
630 /* Prefer fixed purpose counters */
631 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
632 idx
= INTEL_PMC_IDX_FIXED
;
633 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
634 if (!__test_and_set_bit(idx
, sched
->state
.used
))
638 /* Grab the first unused counter starting with idx */
639 idx
= sched
->state
.counter
;
640 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
641 if (!__test_and_set_bit(idx
, sched
->state
.used
))
648 sched
->state
.counter
= idx
;
651 perf_sched_save_state(sched
);
656 static bool perf_sched_find_counter(struct perf_sched
*sched
)
658 while (!__perf_sched_find_counter(sched
)) {
659 if (!perf_sched_restore_state(sched
))
667 * Go through all unassigned events and find the next one to schedule.
668 * Take events with the least weight first. Return true on success.
670 static bool perf_sched_next_event(struct perf_sched
*sched
)
672 struct event_constraint
*c
;
674 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
679 sched
->state
.event
++;
680 if (sched
->state
.event
>= sched
->max_events
) {
682 sched
->state
.event
= 0;
683 sched
->state
.weight
++;
684 if (sched
->state
.weight
> sched
->max_weight
)
687 c
= sched
->constraints
[sched
->state
.event
];
688 } while (c
->weight
!= sched
->state
.weight
);
690 sched
->state
.counter
= 0; /* start with first counter */
696 * Assign a counter for each event.
698 int perf_assign_events(struct event_constraint
**constraints
, int n
,
699 int wmin
, int wmax
, int *assign
)
701 struct perf_sched sched
;
703 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
);
706 if (!perf_sched_find_counter(&sched
))
709 assign
[sched
.state
.event
] = sched
.state
.counter
;
710 } while (perf_sched_next_event(&sched
));
712 return sched
.state
.unassigned
;
715 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
717 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
718 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
719 int i
, wmin
, wmax
, num
= 0;
720 struct hw_perf_event
*hwc
;
722 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
724 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
725 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
727 wmin
= min(wmin
, c
->weight
);
728 wmax
= max(wmax
, c
->weight
);
732 * fastpath, try to reuse previous register
734 for (i
= 0; i
< n
; i
++) {
735 hwc
= &cpuc
->event_list
[i
]->hw
;
742 /* constraint still honored */
743 if (!test_bit(hwc
->idx
, c
->idxmsk
))
746 /* not already used */
747 if (test_bit(hwc
->idx
, used_mask
))
750 __set_bit(hwc
->idx
, used_mask
);
752 assign
[i
] = hwc
->idx
;
757 num
= perf_assign_events(constraints
, n
, wmin
, wmax
, assign
);
760 * scheduling failed or is just a simulation,
761 * free resources if necessary
763 if (!assign
|| num
) {
764 for (i
= 0; i
< n
; i
++) {
765 if (x86_pmu
.put_event_constraints
)
766 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
769 return num
? -EINVAL
: 0;
773 * dogrp: true if must collect siblings events (group)
774 * returns total number of events and error code
776 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
778 struct perf_event
*event
;
781 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
783 /* current number of events already accepted */
786 if (is_x86_event(leader
)) {
789 cpuc
->event_list
[n
] = leader
;
795 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
796 if (!is_x86_event(event
) ||
797 event
->state
<= PERF_EVENT_STATE_OFF
)
803 cpuc
->event_list
[n
] = event
;
809 static inline void x86_assign_hw_event(struct perf_event
*event
,
810 struct cpu_hw_events
*cpuc
, int i
)
812 struct hw_perf_event
*hwc
= &event
->hw
;
814 hwc
->idx
= cpuc
->assign
[i
];
815 hwc
->last_cpu
= smp_processor_id();
816 hwc
->last_tag
= ++cpuc
->tags
[i
];
818 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
819 hwc
->config_base
= 0;
821 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
822 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
823 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
824 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
826 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
827 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
828 hwc
->event_base_rdpmc
= hwc
->idx
;
832 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
833 struct cpu_hw_events
*cpuc
,
836 return hwc
->idx
== cpuc
->assign
[i
] &&
837 hwc
->last_cpu
== smp_processor_id() &&
838 hwc
->last_tag
== cpuc
->tags
[i
];
841 static void x86_pmu_start(struct perf_event
*event
, int flags
);
843 static void x86_pmu_enable(struct pmu
*pmu
)
845 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
846 struct perf_event
*event
;
847 struct hw_perf_event
*hwc
;
848 int i
, added
= cpuc
->n_added
;
850 if (!x86_pmu_initialized())
857 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
859 * apply assignment obtained either from
860 * hw_perf_group_sched_in() or x86_pmu_enable()
862 * step1: save events moving to new counters
863 * step2: reprogram moved events into new counters
865 for (i
= 0; i
< n_running
; i
++) {
866 event
= cpuc
->event_list
[i
];
870 * we can avoid reprogramming counter if:
871 * - assigned same counter as last time
872 * - running on same CPU as last time
873 * - no other event has used the counter since
875 if (hwc
->idx
== -1 ||
876 match_prev_assignment(hwc
, cpuc
, i
))
880 * Ensure we don't accidentally enable a stopped
881 * counter simply because we rescheduled.
883 if (hwc
->state
& PERF_HES_STOPPED
)
884 hwc
->state
|= PERF_HES_ARCH
;
886 x86_pmu_stop(event
, PERF_EF_UPDATE
);
889 for (i
= 0; i
< cpuc
->n_events
; i
++) {
890 event
= cpuc
->event_list
[i
];
893 if (!match_prev_assignment(hwc
, cpuc
, i
))
894 x86_assign_hw_event(event
, cpuc
, i
);
895 else if (i
< n_running
)
898 if (hwc
->state
& PERF_HES_ARCH
)
901 x86_pmu_start(event
, PERF_EF_RELOAD
);
904 perf_events_lapic_init();
910 x86_pmu
.enable_all(added
);
913 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
916 * Set the next IRQ period, based on the hwc->period_left value.
917 * To be called with the event disabled in hw:
919 int x86_perf_event_set_period(struct perf_event
*event
)
921 struct hw_perf_event
*hwc
= &event
->hw
;
922 s64 left
= local64_read(&hwc
->period_left
);
923 s64 period
= hwc
->sample_period
;
924 int ret
= 0, idx
= hwc
->idx
;
926 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
930 * If we are way outside a reasonable range then just skip forward:
932 if (unlikely(left
<= -period
)) {
934 local64_set(&hwc
->period_left
, left
);
935 hwc
->last_period
= period
;
939 if (unlikely(left
<= 0)) {
941 local64_set(&hwc
->period_left
, left
);
942 hwc
->last_period
= period
;
946 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
948 if (unlikely(left
< 2))
951 if (left
> x86_pmu
.max_period
)
952 left
= x86_pmu
.max_period
;
954 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
957 * The hw event starts counting from this event offset,
958 * mark it to be able to extra future deltas:
960 local64_set(&hwc
->prev_count
, (u64
)-left
);
962 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
965 * Due to erratum on certan cpu we need
966 * a second write to be sure the register
967 * is updated properly
969 if (x86_pmu
.perfctr_second_write
) {
970 wrmsrl(hwc
->event_base
,
971 (u64
)(-left
) & x86_pmu
.cntval_mask
);
974 perf_event_update_userpage(event
);
979 void x86_pmu_enable_event(struct perf_event
*event
)
981 if (__this_cpu_read(cpu_hw_events
.enabled
))
982 __x86_pmu_enable_event(&event
->hw
,
983 ARCH_PERFMON_EVENTSEL_ENABLE
);
987 * Add a single event to the PMU.
989 * The event is added to the group of enabled events
990 * but only if it can be scehduled with existing events.
992 static int x86_pmu_add(struct perf_event
*event
, int flags
)
994 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
995 struct hw_perf_event
*hwc
;
996 int assign
[X86_PMC_IDX_MAX
];
1001 perf_pmu_disable(event
->pmu
);
1002 n0
= cpuc
->n_events
;
1003 ret
= n
= collect_events(cpuc
, event
, false);
1007 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1008 if (!(flags
& PERF_EF_START
))
1009 hwc
->state
|= PERF_HES_ARCH
;
1012 * If group events scheduling transaction was started,
1013 * skip the schedulability test here, it will be performed
1014 * at commit time (->commit_txn) as a whole
1016 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1019 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1023 * copy new assignment, now we know it is possible
1024 * will be used by hw_perf_enable()
1026 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1030 cpuc
->n_added
+= n
- n0
;
1031 cpuc
->n_txn
+= n
- n0
;
1035 perf_pmu_enable(event
->pmu
);
1039 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1041 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1042 int idx
= event
->hw
.idx
;
1044 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1047 if (WARN_ON_ONCE(idx
== -1))
1050 if (flags
& PERF_EF_RELOAD
) {
1051 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1052 x86_perf_event_set_period(event
);
1055 event
->hw
.state
= 0;
1057 cpuc
->events
[idx
] = event
;
1058 __set_bit(idx
, cpuc
->active_mask
);
1059 __set_bit(idx
, cpuc
->running
);
1060 x86_pmu
.enable(event
);
1061 perf_event_update_userpage(event
);
1064 void perf_event_print_debug(void)
1066 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1068 struct cpu_hw_events
*cpuc
;
1069 unsigned long flags
;
1072 if (!x86_pmu
.num_counters
)
1075 local_irq_save(flags
);
1077 cpu
= smp_processor_id();
1078 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1080 if (x86_pmu
.version
>= 2) {
1081 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1082 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1083 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1084 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1085 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1088 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1089 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1090 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1091 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1092 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1094 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1096 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1097 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1098 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1100 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1102 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1103 cpu
, idx
, pmc_ctrl
);
1104 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1105 cpu
, idx
, pmc_count
);
1106 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1107 cpu
, idx
, prev_left
);
1109 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1110 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1112 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1113 cpu
, idx
, pmc_count
);
1115 local_irq_restore(flags
);
1118 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1120 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1121 struct hw_perf_event
*hwc
= &event
->hw
;
1123 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1124 x86_pmu
.disable(event
);
1125 cpuc
->events
[hwc
->idx
] = NULL
;
1126 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1127 hwc
->state
|= PERF_HES_STOPPED
;
1130 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1132 * Drain the remaining delta count out of a event
1133 * that we are disabling:
1135 x86_perf_event_update(event
);
1136 hwc
->state
|= PERF_HES_UPTODATE
;
1140 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1142 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1146 * If we're called during a txn, we don't need to do anything.
1147 * The events never got scheduled and ->cancel_txn will truncate
1150 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1153 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1155 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1156 if (event
== cpuc
->event_list
[i
]) {
1158 if (x86_pmu
.put_event_constraints
)
1159 x86_pmu
.put_event_constraints(cpuc
, event
);
1161 while (++i
< cpuc
->n_events
)
1162 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1168 perf_event_update_userpage(event
);
1171 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1173 struct perf_sample_data data
;
1174 struct cpu_hw_events
*cpuc
;
1175 struct perf_event
*event
;
1176 int idx
, handled
= 0;
1179 cpuc
= &__get_cpu_var(cpu_hw_events
);
1182 * Some chipsets need to unmask the LVTPC in a particular spot
1183 * inside the nmi handler. As a result, the unmasking was pushed
1184 * into all the nmi handlers.
1186 * This generic handler doesn't seem to have any issues where the
1187 * unmasking occurs so it was left at the top.
1189 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1191 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1192 if (!test_bit(idx
, cpuc
->active_mask
)) {
1194 * Though we deactivated the counter some cpus
1195 * might still deliver spurious interrupts still
1196 * in flight. Catch them:
1198 if (__test_and_clear_bit(idx
, cpuc
->running
))
1203 event
= cpuc
->events
[idx
];
1205 val
= x86_perf_event_update(event
);
1206 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1213 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1215 if (!x86_perf_event_set_period(event
))
1218 if (perf_event_overflow(event
, &data
, regs
))
1219 x86_pmu_stop(event
, 0);
1223 inc_irq_stat(apic_perf_irqs
);
1228 void perf_events_lapic_init(void)
1230 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1234 * Always use NMI for PMU
1236 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1239 static int __kprobes
1240 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1242 if (!atomic_read(&active_events
))
1245 return x86_pmu
.handle_irq(regs
);
1248 struct event_constraint emptyconstraint
;
1249 struct event_constraint unconstrained
;
1251 static int __cpuinit
1252 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1254 unsigned int cpu
= (long)hcpu
;
1255 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1256 int ret
= NOTIFY_OK
;
1258 switch (action
& ~CPU_TASKS_FROZEN
) {
1259 case CPU_UP_PREPARE
:
1260 cpuc
->kfree_on_online
= NULL
;
1261 if (x86_pmu
.cpu_prepare
)
1262 ret
= x86_pmu
.cpu_prepare(cpu
);
1266 if (x86_pmu
.attr_rdpmc
)
1267 set_in_cr4(X86_CR4_PCE
);
1268 if (x86_pmu
.cpu_starting
)
1269 x86_pmu
.cpu_starting(cpu
);
1273 kfree(cpuc
->kfree_on_online
);
1277 if (x86_pmu
.cpu_dying
)
1278 x86_pmu
.cpu_dying(cpu
);
1281 case CPU_UP_CANCELED
:
1283 if (x86_pmu
.cpu_dead
)
1284 x86_pmu
.cpu_dead(cpu
);
1294 static void __init
pmu_check_apic(void)
1300 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1301 pr_info("no hardware sampling interrupt available.\n");
1304 static struct attribute_group x86_pmu_format_group
= {
1309 static int __init
init_hw_perf_events(void)
1311 struct x86_pmu_quirk
*quirk
;
1314 pr_info("Performance Events: ");
1316 switch (boot_cpu_data
.x86_vendor
) {
1317 case X86_VENDOR_INTEL
:
1318 err
= intel_pmu_init();
1320 case X86_VENDOR_AMD
:
1321 err
= amd_pmu_init();
1327 pr_cont("no PMU driver, software events only.\n");
1333 /* sanity check that the hardware exists or is emulated */
1334 if (!check_hw_exists())
1337 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1339 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1342 if (!x86_pmu
.intel_ctrl
)
1343 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1345 perf_events_lapic_init();
1346 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1348 unconstrained
= (struct event_constraint
)
1349 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1350 0, x86_pmu
.num_counters
, 0);
1352 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1353 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1355 pr_info("... version: %d\n", x86_pmu
.version
);
1356 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1357 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1358 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1359 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1360 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1361 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1363 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1364 perf_cpu_notifier(x86_pmu_notifier
);
1368 early_initcall(init_hw_perf_events
);
1370 static inline void x86_pmu_read(struct perf_event
*event
)
1372 x86_perf_event_update(event
);
1376 * Start group events scheduling transaction
1377 * Set the flag to make pmu::enable() not perform the
1378 * schedulability test, it will be performed at commit time
1380 static void x86_pmu_start_txn(struct pmu
*pmu
)
1382 perf_pmu_disable(pmu
);
1383 __this_cpu_or(cpu_hw_events
.group_flag
, PERF_EVENT_TXN
);
1384 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1388 * Stop group events scheduling transaction
1389 * Clear the flag and pmu::enable() will perform the
1390 * schedulability test.
1392 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1394 __this_cpu_and(cpu_hw_events
.group_flag
, ~PERF_EVENT_TXN
);
1396 * Truncate the collected events.
1398 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1399 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1400 perf_pmu_enable(pmu
);
1404 * Commit group events scheduling transaction
1405 * Perform the group schedulability test as a whole
1406 * Return 0 if success
1408 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1410 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1411 int assign
[X86_PMC_IDX_MAX
];
1416 if (!x86_pmu_initialized())
1419 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1424 * copy new assignment, now we know it is possible
1425 * will be used by hw_perf_enable()
1427 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1429 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1430 perf_pmu_enable(pmu
);
1434 * a fake_cpuc is used to validate event groups. Due to
1435 * the extra reg logic, we need to also allocate a fake
1436 * per_core and per_cpu structure. Otherwise, group events
1437 * using extra reg may conflict without the kernel being
1438 * able to catch this when the last event gets added to
1441 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1443 kfree(cpuc
->shared_regs
);
1447 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1449 struct cpu_hw_events
*cpuc
;
1450 int cpu
= raw_smp_processor_id();
1452 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1454 return ERR_PTR(-ENOMEM
);
1456 /* only needed, if we have extra_regs */
1457 if (x86_pmu
.extra_regs
) {
1458 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1459 if (!cpuc
->shared_regs
)
1465 free_fake_cpuc(cpuc
);
1466 return ERR_PTR(-ENOMEM
);
1470 * validate that we can schedule this event
1472 static int validate_event(struct perf_event
*event
)
1474 struct cpu_hw_events
*fake_cpuc
;
1475 struct event_constraint
*c
;
1478 fake_cpuc
= allocate_fake_cpuc();
1479 if (IS_ERR(fake_cpuc
))
1480 return PTR_ERR(fake_cpuc
);
1482 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1484 if (!c
|| !c
->weight
)
1487 if (x86_pmu
.put_event_constraints
)
1488 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1490 free_fake_cpuc(fake_cpuc
);
1496 * validate a single event group
1498 * validation include:
1499 * - check events are compatible which each other
1500 * - events do not compete for the same counter
1501 * - number of events <= number of counters
1503 * validation ensures the group can be loaded onto the
1504 * PMU if it was the only group available.
1506 static int validate_group(struct perf_event
*event
)
1508 struct perf_event
*leader
= event
->group_leader
;
1509 struct cpu_hw_events
*fake_cpuc
;
1510 int ret
= -EINVAL
, n
;
1512 fake_cpuc
= allocate_fake_cpuc();
1513 if (IS_ERR(fake_cpuc
))
1514 return PTR_ERR(fake_cpuc
);
1516 * the event is not yet connected with its
1517 * siblings therefore we must first collect
1518 * existing siblings, then add the new event
1519 * before we can simulate the scheduling
1521 n
= collect_events(fake_cpuc
, leader
, true);
1525 fake_cpuc
->n_events
= n
;
1526 n
= collect_events(fake_cpuc
, event
, false);
1530 fake_cpuc
->n_events
= n
;
1532 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1535 free_fake_cpuc(fake_cpuc
);
1539 static int x86_pmu_event_init(struct perf_event
*event
)
1544 switch (event
->attr
.type
) {
1546 case PERF_TYPE_HARDWARE
:
1547 case PERF_TYPE_HW_CACHE
:
1554 err
= __x86_pmu_event_init(event
);
1557 * we temporarily connect event to its pmu
1558 * such that validate_group() can classify
1559 * it as an x86 event using is_x86_event()
1564 if (event
->group_leader
!= event
)
1565 err
= validate_group(event
);
1567 err
= validate_event(event
);
1573 event
->destroy(event
);
1579 static int x86_pmu_event_idx(struct perf_event
*event
)
1581 int idx
= event
->hw
.idx
;
1583 if (!x86_pmu
.attr_rdpmc
)
1586 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
1587 idx
-= INTEL_PMC_IDX_FIXED
;
1594 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
1595 struct device_attribute
*attr
,
1598 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
1601 static void change_rdpmc(void *info
)
1603 bool enable
= !!(unsigned long)info
;
1606 set_in_cr4(X86_CR4_PCE
);
1608 clear_in_cr4(X86_CR4_PCE
);
1611 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
1612 struct device_attribute
*attr
,
1613 const char *buf
, size_t count
)
1618 ret
= kstrtoul(buf
, 0, &val
);
1622 if (!!val
!= !!x86_pmu
.attr_rdpmc
) {
1623 x86_pmu
.attr_rdpmc
= !!val
;
1624 smp_call_function(change_rdpmc
, (void *)val
, 1);
1630 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
1632 static struct attribute
*x86_pmu_attrs
[] = {
1633 &dev_attr_rdpmc
.attr
,
1637 static struct attribute_group x86_pmu_attr_group
= {
1638 .attrs
= x86_pmu_attrs
,
1641 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
1642 &x86_pmu_attr_group
,
1643 &x86_pmu_format_group
,
1647 static void x86_pmu_flush_branch_stack(void)
1649 if (x86_pmu
.flush_branch_stack
)
1650 x86_pmu
.flush_branch_stack();
1653 void perf_check_microcode(void)
1655 if (x86_pmu
.check_microcode
)
1656 x86_pmu
.check_microcode();
1658 EXPORT_SYMBOL_GPL(perf_check_microcode
);
1660 static struct pmu pmu
= {
1661 .pmu_enable
= x86_pmu_enable
,
1662 .pmu_disable
= x86_pmu_disable
,
1664 .attr_groups
= x86_pmu_attr_groups
,
1666 .event_init
= x86_pmu_event_init
,
1670 .start
= x86_pmu_start
,
1671 .stop
= x86_pmu_stop
,
1672 .read
= x86_pmu_read
,
1674 .start_txn
= x86_pmu_start_txn
,
1675 .cancel_txn
= x86_pmu_cancel_txn
,
1676 .commit_txn
= x86_pmu_commit_txn
,
1678 .event_idx
= x86_pmu_event_idx
,
1679 .flush_branch_stack
= x86_pmu_flush_branch_stack
,
1682 void arch_perf_update_userpage(struct perf_event_mmap_page
*userpg
, u64 now
)
1684 userpg
->cap_usr_time
= 0;
1685 userpg
->cap_usr_rdpmc
= x86_pmu
.attr_rdpmc
;
1686 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
1688 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
1691 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
1694 userpg
->cap_usr_time
= 1;
1695 userpg
->time_mult
= this_cpu_read(cyc2ns
);
1696 userpg
->time_shift
= CYC2NS_SCALE_FACTOR
;
1697 userpg
->time_offset
= this_cpu_read(cyc2ns_offset
) - now
;
1704 static int backtrace_stack(void *data
, char *name
)
1709 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1711 struct perf_callchain_entry
*entry
= data
;
1713 perf_callchain_store(entry
, addr
);
1716 static const struct stacktrace_ops backtrace_ops
= {
1717 .stack
= backtrace_stack
,
1718 .address
= backtrace_address
,
1719 .walk_stack
= print_context_stack_bp
,
1723 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1725 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1726 /* TODO: We don't support guest os callchain now */
1730 perf_callchain_store(entry
, regs
->ip
);
1732 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
1736 valid_user_frame(const void __user
*fp
, unsigned long size
)
1738 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
1741 #ifdef CONFIG_COMPAT
1743 #include <asm/compat.h>
1746 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1748 /* 32-bit process in 64-bit kernel. */
1749 struct stack_frame_ia32 frame
;
1750 const void __user
*fp
;
1752 if (!test_thread_flag(TIF_IA32
))
1755 fp
= compat_ptr(regs
->bp
);
1756 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1757 unsigned long bytes
;
1758 frame
.next_frame
= 0;
1759 frame
.return_address
= 0;
1761 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1762 if (bytes
!= sizeof(frame
))
1765 if (!valid_user_frame(fp
, sizeof(frame
)))
1768 perf_callchain_store(entry
, frame
.return_address
);
1769 fp
= compat_ptr(frame
.next_frame
);
1775 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1782 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1784 struct stack_frame frame
;
1785 const void __user
*fp
;
1787 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1788 /* TODO: We don't support guest os callchain now */
1792 fp
= (void __user
*)regs
->bp
;
1794 perf_callchain_store(entry
, regs
->ip
);
1799 if (perf_callchain_user32(regs
, entry
))
1802 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1803 unsigned long bytes
;
1804 frame
.next_frame
= NULL
;
1805 frame
.return_address
= 0;
1807 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1808 if (bytes
!= sizeof(frame
))
1811 if (!valid_user_frame(fp
, sizeof(frame
)))
1814 perf_callchain_store(entry
, frame
.return_address
);
1815 fp
= frame
.next_frame
;
1819 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1823 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
1824 ip
= perf_guest_cbs
->get_guest_ip();
1826 ip
= instruction_pointer(regs
);
1831 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1835 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1836 if (perf_guest_cbs
->is_user_mode())
1837 misc
|= PERF_RECORD_MISC_GUEST_USER
;
1839 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
1841 if (!kernel_ip(regs
->ip
))
1842 misc
|= PERF_RECORD_MISC_USER
;
1844 misc
|= PERF_RECORD_MISC_KERNEL
;
1847 if (regs
->flags
& PERF_EFLAGS_EXACT
)
1848 misc
|= PERF_RECORD_MISC_EXACT_IP
;
1853 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
1855 cap
->version
= x86_pmu
.version
;
1856 cap
->num_counters_gp
= x86_pmu
.num_counters
;
1857 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
1858 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
1859 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
1860 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
1861 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
1863 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);