2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/tlbflush.h>
35 #include <asm/timer.h>
39 #include "perf_event.h"
41 struct x86_pmu x86_pmu __read_mostly
;
43 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
47 u64 __read_mostly hw_cache_event_ids
48 [PERF_COUNT_HW_CACHE_MAX
]
49 [PERF_COUNT_HW_CACHE_OP_MAX
]
50 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
51 u64 __read_mostly hw_cache_extra_regs
52 [PERF_COUNT_HW_CACHE_MAX
]
53 [PERF_COUNT_HW_CACHE_OP_MAX
]
54 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
57 * Propagate event elapsed time into the generic event.
58 * Can only be executed on the CPU where the event is active.
59 * Returns the delta events processed.
61 u64
x86_perf_event_update(struct perf_event
*event
)
63 struct hw_perf_event
*hwc
= &event
->hw
;
64 int shift
= 64 - x86_pmu
.cntval_bits
;
65 u64 prev_raw_count
, new_raw_count
;
69 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
73 * Careful: an NMI might modify the previous event value.
75 * Our tactic to handle this is to first atomically read and
76 * exchange a new raw count - then add that new-prev delta
77 * count to the generic event atomically:
80 prev_raw_count
= local64_read(&hwc
->prev_count
);
81 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
83 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
84 new_raw_count
) != prev_raw_count
)
88 * Now we have the new raw value and have updated the prev
89 * timestamp already. We can now calculate the elapsed delta
90 * (event-)time and add that to the generic event.
92 * Careful, not all hw sign-extends above the physical width
95 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
98 local64_add(delta
, &event
->count
);
99 local64_sub(delta
, &hwc
->period_left
);
101 return new_raw_count
;
105 * Find and validate any extra registers to set up.
107 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
109 struct hw_perf_event_extra
*reg
;
110 struct extra_reg
*er
;
112 reg
= &event
->hw
.extra_reg
;
114 if (!x86_pmu
.extra_regs
)
117 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
118 if (er
->event
!= (config
& er
->config_mask
))
120 if (event
->attr
.config1
& ~er
->valid_mask
)
122 /* Check if the extra msrs can be safely accessed*/
123 if (!er
->extra_msr_access
)
127 reg
->config
= event
->attr
.config1
;
134 static atomic_t active_events
;
135 static DEFINE_MUTEX(pmc_reserve_mutex
);
137 #ifdef CONFIG_X86_LOCAL_APIC
139 static bool reserve_pmc_hardware(void)
143 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
144 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
148 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
149 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
156 for (i
--; i
>= 0; i
--)
157 release_evntsel_nmi(x86_pmu_config_addr(i
));
159 i
= x86_pmu
.num_counters
;
162 for (i
--; i
>= 0; i
--)
163 release_perfctr_nmi(x86_pmu_event_addr(i
));
168 static void release_pmc_hardware(void)
172 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
173 release_perfctr_nmi(x86_pmu_event_addr(i
));
174 release_evntsel_nmi(x86_pmu_config_addr(i
));
180 static bool reserve_pmc_hardware(void) { return true; }
181 static void release_pmc_hardware(void) {}
185 static bool check_hw_exists(void)
187 u64 val
, val_fail
, val_new
= ~0;
188 int i
, reg
, reg_fail
, ret
= 0;
192 * Check to see if the BIOS enabled any of the counters, if so
195 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
196 reg
= x86_pmu_config_addr(i
);
197 ret
= rdmsrl_safe(reg
, &val
);
200 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
207 if (x86_pmu
.num_counters_fixed
) {
208 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
209 ret
= rdmsrl_safe(reg
, &val
);
212 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
213 if (val
& (0x03 << i
*4)) {
222 * Read the current value, change it and read it back to see if it
223 * matches, this is needed to detect certain hardware emulators
224 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
226 reg
= x86_pmu_event_addr(0);
227 if (rdmsrl_safe(reg
, &val
))
230 ret
= wrmsrl_safe(reg
, val
);
231 ret
|= rdmsrl_safe(reg
, &val_new
);
232 if (ret
|| val
!= val_new
)
236 * We still allow the PMU driver to operate:
239 printk(KERN_CONT
"Broken BIOS detected, complain to your hardware vendor.\n");
240 printk(KERN_ERR FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail
, val_fail
);
246 printk(KERN_CONT
"Broken PMU hardware detected, using software events only.\n");
247 printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
248 boot_cpu_has(X86_FEATURE_HYPERVISOR
) ? KERN_INFO
: KERN_ERR
,
254 static void hw_perf_event_destroy(struct perf_event
*event
)
256 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
257 release_pmc_hardware();
258 release_ds_buffers();
259 mutex_unlock(&pmc_reserve_mutex
);
263 static inline int x86_pmu_initialized(void)
265 return x86_pmu
.handle_irq
!= NULL
;
269 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
271 struct perf_event_attr
*attr
= &event
->attr
;
272 unsigned int cache_type
, cache_op
, cache_result
;
275 config
= attr
->config
;
277 cache_type
= (config
>> 0) & 0xff;
278 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
281 cache_op
= (config
>> 8) & 0xff;
282 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
285 cache_result
= (config
>> 16) & 0xff;
286 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
289 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
298 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
299 return x86_pmu_extra_regs(val
, event
);
302 int x86_setup_perfctr(struct perf_event
*event
)
304 struct perf_event_attr
*attr
= &event
->attr
;
305 struct hw_perf_event
*hwc
= &event
->hw
;
308 if (!is_sampling_event(event
)) {
309 hwc
->sample_period
= x86_pmu
.max_period
;
310 hwc
->last_period
= hwc
->sample_period
;
311 local64_set(&hwc
->period_left
, hwc
->sample_period
);
314 if (attr
->type
== PERF_TYPE_RAW
)
315 return x86_pmu_extra_regs(event
->attr
.config
, event
);
317 if (attr
->type
== PERF_TYPE_HW_CACHE
)
318 return set_ext_hw_attr(hwc
, event
);
320 if (attr
->config
>= x86_pmu
.max_events
)
326 config
= x86_pmu
.event_map(attr
->config
);
337 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
338 !attr
->freq
&& hwc
->sample_period
== 1) {
339 /* BTS is not supported by this architecture. */
340 if (!x86_pmu
.bts_active
)
343 /* BTS is currently only allowed for user-mode. */
344 if (!attr
->exclude_kernel
)
348 hwc
->config
|= config
;
354 * check that branch_sample_type is compatible with
355 * settings needed for precise_ip > 1 which implies
356 * using the LBR to capture ALL taken branches at the
357 * priv levels of the measurement
359 static inline int precise_br_compat(struct perf_event
*event
)
361 u64 m
= event
->attr
.branch_sample_type
;
364 /* must capture all branches */
365 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
368 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
370 if (!event
->attr
.exclude_user
)
371 b
|= PERF_SAMPLE_BRANCH_USER
;
373 if (!event
->attr
.exclude_kernel
)
374 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
377 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
383 int x86_pmu_hw_config(struct perf_event
*event
)
385 if (event
->attr
.precise_ip
) {
388 /* Support for constant skid */
389 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
392 /* Support for IP fixup */
393 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
397 if (event
->attr
.precise_ip
> precise
)
400 * check that PEBS LBR correction does not conflict with
401 * whatever the user is asking with attr->branch_sample_type
403 if (event
->attr
.precise_ip
> 1 &&
404 x86_pmu
.intel_cap
.pebs_format
< 2) {
405 u64
*br_type
= &event
->attr
.branch_sample_type
;
407 if (has_branch_stack(event
)) {
408 if (!precise_br_compat(event
))
411 /* branch_sample_type is compatible */
415 * user did not specify branch_sample_type
417 * For PEBS fixups, we capture all
418 * the branches at the priv level of the
421 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
423 if (!event
->attr
.exclude_user
)
424 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
426 if (!event
->attr
.exclude_kernel
)
427 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
434 * (keep 'enabled' bit clear for now)
436 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
439 * Count user and OS events unless requested not to
441 if (!event
->attr
.exclude_user
)
442 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
443 if (!event
->attr
.exclude_kernel
)
444 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
446 if (event
->attr
.type
== PERF_TYPE_RAW
)
447 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
449 return x86_setup_perfctr(event
);
453 * Setup the hardware configuration for a given attr_type
455 static int __x86_pmu_event_init(struct perf_event
*event
)
459 if (!x86_pmu_initialized())
463 if (!atomic_inc_not_zero(&active_events
)) {
464 mutex_lock(&pmc_reserve_mutex
);
465 if (atomic_read(&active_events
) == 0) {
466 if (!reserve_pmc_hardware())
469 reserve_ds_buffers();
472 atomic_inc(&active_events
);
473 mutex_unlock(&pmc_reserve_mutex
);
478 event
->destroy
= hw_perf_event_destroy
;
481 event
->hw
.last_cpu
= -1;
482 event
->hw
.last_tag
= ~0ULL;
485 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
486 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
488 return x86_pmu
.hw_config(event
);
491 void x86_pmu_disable_all(void)
493 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
496 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
499 if (!test_bit(idx
, cpuc
->active_mask
))
501 rdmsrl(x86_pmu_config_addr(idx
), val
);
502 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
504 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
505 wrmsrl(x86_pmu_config_addr(idx
), val
);
509 static void x86_pmu_disable(struct pmu
*pmu
)
511 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
513 if (!x86_pmu_initialized())
523 x86_pmu
.disable_all();
526 void x86_pmu_enable_all(int added
)
528 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
531 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
532 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
534 if (!test_bit(idx
, cpuc
->active_mask
))
537 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
541 static struct pmu pmu
;
543 static inline int is_x86_event(struct perf_event
*event
)
545 return event
->pmu
== &pmu
;
549 * Event scheduler state:
551 * Assign events iterating over all events and counters, beginning
552 * with events with least weights first. Keep the current iterator
553 * state in struct sched_state.
557 int event
; /* event index */
558 int counter
; /* counter index */
559 int unassigned
; /* number of events to be assigned left */
560 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
563 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
564 #define SCHED_STATES_MAX 2
569 struct perf_event
**events
;
570 struct sched_state state
;
572 struct sched_state saved
[SCHED_STATES_MAX
];
576 * Initialize interator that runs through all events and counters.
578 static void perf_sched_init(struct perf_sched
*sched
, struct perf_event
**events
,
579 int num
, int wmin
, int wmax
)
583 memset(sched
, 0, sizeof(*sched
));
584 sched
->max_events
= num
;
585 sched
->max_weight
= wmax
;
586 sched
->events
= events
;
588 for (idx
= 0; idx
< num
; idx
++) {
589 if (events
[idx
]->hw
.constraint
->weight
== wmin
)
593 sched
->state
.event
= idx
; /* start with min weight */
594 sched
->state
.weight
= wmin
;
595 sched
->state
.unassigned
= num
;
598 static void perf_sched_save_state(struct perf_sched
*sched
)
600 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
603 sched
->saved
[sched
->saved_states
] = sched
->state
;
604 sched
->saved_states
++;
607 static bool perf_sched_restore_state(struct perf_sched
*sched
)
609 if (!sched
->saved_states
)
612 sched
->saved_states
--;
613 sched
->state
= sched
->saved
[sched
->saved_states
];
615 /* continue with next counter: */
616 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
622 * Select a counter for the current event to schedule. Return true on
625 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
627 struct event_constraint
*c
;
630 if (!sched
->state
.unassigned
)
633 if (sched
->state
.event
>= sched
->max_events
)
636 c
= sched
->events
[sched
->state
.event
]->hw
.constraint
;
637 /* Prefer fixed purpose counters */
638 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
639 idx
= INTEL_PMC_IDX_FIXED
;
640 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
641 if (!__test_and_set_bit(idx
, sched
->state
.used
))
645 /* Grab the first unused counter starting with idx */
646 idx
= sched
->state
.counter
;
647 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
648 if (!__test_and_set_bit(idx
, sched
->state
.used
))
655 sched
->state
.counter
= idx
;
658 perf_sched_save_state(sched
);
663 static bool perf_sched_find_counter(struct perf_sched
*sched
)
665 while (!__perf_sched_find_counter(sched
)) {
666 if (!perf_sched_restore_state(sched
))
674 * Go through all unassigned events and find the next one to schedule.
675 * Take events with the least weight first. Return true on success.
677 static bool perf_sched_next_event(struct perf_sched
*sched
)
679 struct event_constraint
*c
;
681 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
686 sched
->state
.event
++;
687 if (sched
->state
.event
>= sched
->max_events
) {
689 sched
->state
.event
= 0;
690 sched
->state
.weight
++;
691 if (sched
->state
.weight
> sched
->max_weight
)
694 c
= sched
->events
[sched
->state
.event
]->hw
.constraint
;
695 } while (c
->weight
!= sched
->state
.weight
);
697 sched
->state
.counter
= 0; /* start with first counter */
703 * Assign a counter for each event.
705 int perf_assign_events(struct perf_event
**events
, int n
,
706 int wmin
, int wmax
, int *assign
)
708 struct perf_sched sched
;
710 perf_sched_init(&sched
, events
, n
, wmin
, wmax
);
713 if (!perf_sched_find_counter(&sched
))
716 assign
[sched
.state
.event
] = sched
.state
.counter
;
717 } while (perf_sched_next_event(&sched
));
719 return sched
.state
.unassigned
;
721 EXPORT_SYMBOL_GPL(perf_assign_events
);
723 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
725 struct event_constraint
*c
;
726 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
727 struct perf_event
*e
;
728 int i
, wmin
, wmax
, num
= 0;
729 struct hw_perf_event
*hwc
;
731 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
733 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
734 hwc
= &cpuc
->event_list
[i
]->hw
;
735 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
738 wmin
= min(wmin
, c
->weight
);
739 wmax
= max(wmax
, c
->weight
);
743 * fastpath, try to reuse previous register
745 for (i
= 0; i
< n
; i
++) {
746 hwc
= &cpuc
->event_list
[i
]->hw
;
753 /* constraint still honored */
754 if (!test_bit(hwc
->idx
, c
->idxmsk
))
757 /* not already used */
758 if (test_bit(hwc
->idx
, used_mask
))
761 __set_bit(hwc
->idx
, used_mask
);
763 assign
[i
] = hwc
->idx
;
768 num
= perf_assign_events(cpuc
->event_list
, n
, wmin
,
772 * Mark the event as committed, so we do not put_constraint()
773 * in case new events are added and fail scheduling.
775 if (!num
&& assign
) {
776 for (i
= 0; i
< n
; i
++) {
777 e
= cpuc
->event_list
[i
];
778 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
782 * scheduling failed or is just a simulation,
783 * free resources if necessary
785 if (!assign
|| num
) {
786 for (i
= 0; i
< n
; i
++) {
787 e
= cpuc
->event_list
[i
];
789 * do not put_constraint() on comitted events,
790 * because they are good to go
792 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
795 if (x86_pmu
.put_event_constraints
)
796 x86_pmu
.put_event_constraints(cpuc
, e
);
799 return num
? -EINVAL
: 0;
803 * dogrp: true if must collect siblings events (group)
804 * returns total number of events and error code
806 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
808 struct perf_event
*event
;
811 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
813 /* current number of events already accepted */
816 if (is_x86_event(leader
)) {
819 cpuc
->event_list
[n
] = leader
;
825 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
826 if (!is_x86_event(event
) ||
827 event
->state
<= PERF_EVENT_STATE_OFF
)
833 cpuc
->event_list
[n
] = event
;
839 static inline void x86_assign_hw_event(struct perf_event
*event
,
840 struct cpu_hw_events
*cpuc
, int i
)
842 struct hw_perf_event
*hwc
= &event
->hw
;
844 hwc
->idx
= cpuc
->assign
[i
];
845 hwc
->last_cpu
= smp_processor_id();
846 hwc
->last_tag
= ++cpuc
->tags
[i
];
848 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
849 hwc
->config_base
= 0;
851 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
852 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
853 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
854 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
856 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
857 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
858 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
862 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
863 struct cpu_hw_events
*cpuc
,
866 return hwc
->idx
== cpuc
->assign
[i
] &&
867 hwc
->last_cpu
== smp_processor_id() &&
868 hwc
->last_tag
== cpuc
->tags
[i
];
871 static void x86_pmu_start(struct perf_event
*event
, int flags
);
873 static void x86_pmu_enable(struct pmu
*pmu
)
875 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
876 struct perf_event
*event
;
877 struct hw_perf_event
*hwc
;
878 int i
, added
= cpuc
->n_added
;
880 if (!x86_pmu_initialized())
887 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
889 * apply assignment obtained either from
890 * hw_perf_group_sched_in() or x86_pmu_enable()
892 * step1: save events moving to new counters
894 for (i
= 0; i
< n_running
; i
++) {
895 event
= cpuc
->event_list
[i
];
899 * we can avoid reprogramming counter if:
900 * - assigned same counter as last time
901 * - running on same CPU as last time
902 * - no other event has used the counter since
904 if (hwc
->idx
== -1 ||
905 match_prev_assignment(hwc
, cpuc
, i
))
909 * Ensure we don't accidentally enable a stopped
910 * counter simply because we rescheduled.
912 if (hwc
->state
& PERF_HES_STOPPED
)
913 hwc
->state
|= PERF_HES_ARCH
;
915 x86_pmu_stop(event
, PERF_EF_UPDATE
);
919 * step2: reprogram moved events into new counters
921 for (i
= 0; i
< cpuc
->n_events
; i
++) {
922 event
= cpuc
->event_list
[i
];
925 if (!match_prev_assignment(hwc
, cpuc
, i
))
926 x86_assign_hw_event(event
, cpuc
, i
);
927 else if (i
< n_running
)
930 if (hwc
->state
& PERF_HES_ARCH
)
933 x86_pmu_start(event
, PERF_EF_RELOAD
);
936 perf_events_lapic_init();
942 x86_pmu
.enable_all(added
);
945 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
948 * Set the next IRQ period, based on the hwc->period_left value.
949 * To be called with the event disabled in hw:
951 int x86_perf_event_set_period(struct perf_event
*event
)
953 struct hw_perf_event
*hwc
= &event
->hw
;
954 s64 left
= local64_read(&hwc
->period_left
);
955 s64 period
= hwc
->sample_period
;
956 int ret
= 0, idx
= hwc
->idx
;
958 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
962 * If we are way outside a reasonable range then just skip forward:
964 if (unlikely(left
<= -period
)) {
966 local64_set(&hwc
->period_left
, left
);
967 hwc
->last_period
= period
;
971 if (unlikely(left
<= 0)) {
973 local64_set(&hwc
->period_left
, left
);
974 hwc
->last_period
= period
;
978 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
980 if (unlikely(left
< 2))
983 if (left
> x86_pmu
.max_period
)
984 left
= x86_pmu
.max_period
;
986 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
989 * The hw event starts counting from this event offset,
990 * mark it to be able to extra future deltas:
992 local64_set(&hwc
->prev_count
, (u64
)-left
);
994 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
997 * Due to erratum on certan cpu we need
998 * a second write to be sure the register
999 * is updated properly
1001 if (x86_pmu
.perfctr_second_write
) {
1002 wrmsrl(hwc
->event_base
,
1003 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1006 perf_event_update_userpage(event
);
1011 void x86_pmu_enable_event(struct perf_event
*event
)
1013 if (__this_cpu_read(cpu_hw_events
.enabled
))
1014 __x86_pmu_enable_event(&event
->hw
,
1015 ARCH_PERFMON_EVENTSEL_ENABLE
);
1019 * Add a single event to the PMU.
1021 * The event is added to the group of enabled events
1022 * but only if it can be scehduled with existing events.
1024 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1026 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1027 struct hw_perf_event
*hwc
;
1028 int assign
[X86_PMC_IDX_MAX
];
1033 perf_pmu_disable(event
->pmu
);
1034 n0
= cpuc
->n_events
;
1035 ret
= n
= collect_events(cpuc
, event
, false);
1039 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1040 if (!(flags
& PERF_EF_START
))
1041 hwc
->state
|= PERF_HES_ARCH
;
1044 * If group events scheduling transaction was started,
1045 * skip the schedulability test here, it will be performed
1046 * at commit time (->commit_txn) as a whole.
1048 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1051 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1055 * copy new assignment, now we know it is possible
1056 * will be used by hw_perf_enable()
1058 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1062 * Commit the collect_events() state. See x86_pmu_del() and
1066 cpuc
->n_added
+= n
- n0
;
1067 cpuc
->n_txn
+= n
- n0
;
1071 perf_pmu_enable(event
->pmu
);
1075 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1077 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1078 int idx
= event
->hw
.idx
;
1080 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1083 if (WARN_ON_ONCE(idx
== -1))
1086 if (flags
& PERF_EF_RELOAD
) {
1087 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1088 x86_perf_event_set_period(event
);
1091 event
->hw
.state
= 0;
1093 cpuc
->events
[idx
] = event
;
1094 __set_bit(idx
, cpuc
->active_mask
);
1095 __set_bit(idx
, cpuc
->running
);
1096 x86_pmu
.enable(event
);
1097 perf_event_update_userpage(event
);
1100 void perf_event_print_debug(void)
1102 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1104 struct cpu_hw_events
*cpuc
;
1105 unsigned long flags
;
1108 if (!x86_pmu
.num_counters
)
1111 local_irq_save(flags
);
1113 cpu
= smp_processor_id();
1114 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1116 if (x86_pmu
.version
>= 2) {
1117 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1118 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1119 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1120 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1121 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1124 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1125 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1126 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1127 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1128 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1130 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1132 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1133 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1134 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1136 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1138 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1139 cpu
, idx
, pmc_ctrl
);
1140 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1141 cpu
, idx
, pmc_count
);
1142 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1143 cpu
, idx
, prev_left
);
1145 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1146 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1148 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1149 cpu
, idx
, pmc_count
);
1151 local_irq_restore(flags
);
1154 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1156 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1157 struct hw_perf_event
*hwc
= &event
->hw
;
1159 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1160 x86_pmu
.disable(event
);
1161 cpuc
->events
[hwc
->idx
] = NULL
;
1162 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1163 hwc
->state
|= PERF_HES_STOPPED
;
1166 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1168 * Drain the remaining delta count out of a event
1169 * that we are disabling:
1171 x86_perf_event_update(event
);
1172 hwc
->state
|= PERF_HES_UPTODATE
;
1176 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1178 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1182 * event is descheduled
1184 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1187 * If we're called during a txn, we don't need to do anything.
1188 * The events never got scheduled and ->cancel_txn will truncate
1191 * XXX assumes any ->del() called during a TXN will only be on
1192 * an event added during that same TXN.
1194 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1198 * Not a TXN, therefore cleanup properly.
1200 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1202 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1203 if (event
== cpuc
->event_list
[i
])
1207 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1210 /* If we have a newly added event; make sure to decrease n_added. */
1211 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1214 if (x86_pmu
.put_event_constraints
)
1215 x86_pmu
.put_event_constraints(cpuc
, event
);
1217 /* Delete the array entry. */
1218 while (++i
< cpuc
->n_events
)
1219 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1222 perf_event_update_userpage(event
);
1225 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1227 struct perf_sample_data data
;
1228 struct cpu_hw_events
*cpuc
;
1229 struct perf_event
*event
;
1230 int idx
, handled
= 0;
1233 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1236 * Some chipsets need to unmask the LVTPC in a particular spot
1237 * inside the nmi handler. As a result, the unmasking was pushed
1238 * into all the nmi handlers.
1240 * This generic handler doesn't seem to have any issues where the
1241 * unmasking occurs so it was left at the top.
1243 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1245 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1246 if (!test_bit(idx
, cpuc
->active_mask
)) {
1248 * Though we deactivated the counter some cpus
1249 * might still deliver spurious interrupts still
1250 * in flight. Catch them:
1252 if (__test_and_clear_bit(idx
, cpuc
->running
))
1257 event
= cpuc
->events
[idx
];
1259 val
= x86_perf_event_update(event
);
1260 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1267 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1269 if (!x86_perf_event_set_period(event
))
1272 if (perf_event_overflow(event
, &data
, regs
))
1273 x86_pmu_stop(event
, 0);
1277 inc_irq_stat(apic_perf_irqs
);
1282 void perf_events_lapic_init(void)
1284 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1288 * Always use NMI for PMU
1290 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1294 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1300 if (!atomic_read(&active_events
))
1303 start_clock
= sched_clock();
1304 ret
= x86_pmu
.handle_irq(regs
);
1305 finish_clock
= sched_clock();
1307 perf_sample_event_took(finish_clock
- start_clock
);
1311 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1313 struct event_constraint emptyconstraint
;
1314 struct event_constraint unconstrained
;
1317 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1319 unsigned int cpu
= (long)hcpu
;
1320 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1321 int ret
= NOTIFY_OK
;
1323 switch (action
& ~CPU_TASKS_FROZEN
) {
1324 case CPU_UP_PREPARE
:
1325 cpuc
->kfree_on_online
= NULL
;
1326 if (x86_pmu
.cpu_prepare
)
1327 ret
= x86_pmu
.cpu_prepare(cpu
);
1331 if (x86_pmu
.attr_rdpmc
)
1332 cr4_set_bits(X86_CR4_PCE
);
1333 if (x86_pmu
.cpu_starting
)
1334 x86_pmu
.cpu_starting(cpu
);
1338 kfree(cpuc
->kfree_on_online
);
1342 if (x86_pmu
.cpu_dying
)
1343 x86_pmu
.cpu_dying(cpu
);
1346 case CPU_UP_CANCELED
:
1348 if (x86_pmu
.cpu_dead
)
1349 x86_pmu
.cpu_dead(cpu
);
1359 static void __init
pmu_check_apic(void)
1365 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1366 pr_info("no hardware sampling interrupt available.\n");
1369 * If we have a PMU initialized but no APIC
1370 * interrupts, we cannot sample hardware
1371 * events (user-space has to fall back and
1372 * sample via a hrtimer based software event):
1374 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1378 static struct attribute_group x86_pmu_format_group
= {
1384 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1385 * out of events_attr attributes.
1387 static void __init
filter_events(struct attribute
**attrs
)
1389 struct device_attribute
*d
;
1390 struct perf_pmu_events_attr
*pmu_attr
;
1393 for (i
= 0; attrs
[i
]; i
++) {
1394 d
= (struct device_attribute
*)attrs
[i
];
1395 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1397 if (pmu_attr
->event_str
)
1399 if (x86_pmu
.event_map(i
))
1402 for (j
= i
; attrs
[j
]; j
++)
1403 attrs
[j
] = attrs
[j
+ 1];
1405 /* Check the shifted attr. */
1410 /* Merge two pointer arrays */
1411 static __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1413 struct attribute
**new;
1416 for (j
= 0; a
[j
]; j
++)
1418 for (i
= 0; b
[i
]; i
++)
1422 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1427 for (i
= 0; a
[i
]; i
++)
1429 for (i
= 0; b
[i
]; i
++)
1436 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1439 struct perf_pmu_events_attr
*pmu_attr
= \
1440 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1441 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1443 /* string trumps id */
1444 if (pmu_attr
->event_str
)
1445 return sprintf(page
, "%s", pmu_attr
->event_str
);
1447 return x86_pmu
.events_sysfs_show(page
, config
);
1450 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1451 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1452 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1453 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1454 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1455 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1456 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1457 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1458 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1459 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1461 static struct attribute
*empty_attrs
;
1463 static struct attribute
*events_attr
[] = {
1464 EVENT_PTR(CPU_CYCLES
),
1465 EVENT_PTR(INSTRUCTIONS
),
1466 EVENT_PTR(CACHE_REFERENCES
),
1467 EVENT_PTR(CACHE_MISSES
),
1468 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1469 EVENT_PTR(BRANCH_MISSES
),
1470 EVENT_PTR(BUS_CYCLES
),
1471 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1472 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1473 EVENT_PTR(REF_CPU_CYCLES
),
1477 static struct attribute_group x86_pmu_events_group
= {
1479 .attrs
= events_attr
,
1482 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1484 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1485 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1486 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1487 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1488 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1489 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1493 * We have whole page size to spend and just little data
1494 * to write, so we can safely use sprintf.
1496 ret
= sprintf(page
, "event=0x%02llx", event
);
1499 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1502 ret
+= sprintf(page
+ ret
, ",edge");
1505 ret
+= sprintf(page
+ ret
, ",pc");
1508 ret
+= sprintf(page
+ ret
, ",any");
1511 ret
+= sprintf(page
+ ret
, ",inv");
1514 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1516 ret
+= sprintf(page
+ ret
, "\n");
1521 static int __init
init_hw_perf_events(void)
1523 struct x86_pmu_quirk
*quirk
;
1526 pr_info("Performance Events: ");
1528 switch (boot_cpu_data
.x86_vendor
) {
1529 case X86_VENDOR_INTEL
:
1530 err
= intel_pmu_init();
1532 case X86_VENDOR_AMD
:
1533 err
= amd_pmu_init();
1539 pr_cont("no PMU driver, software events only.\n");
1545 /* sanity check that the hardware exists or is emulated */
1546 if (!check_hw_exists())
1549 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1551 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1553 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1556 if (!x86_pmu
.intel_ctrl
)
1557 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1559 perf_events_lapic_init();
1560 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1562 unconstrained
= (struct event_constraint
)
1563 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1564 0, x86_pmu
.num_counters
, 0, 0);
1566 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1568 if (x86_pmu
.event_attrs
)
1569 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1571 if (!x86_pmu
.events_sysfs_show
)
1572 x86_pmu_events_group
.attrs
= &empty_attrs
;
1574 filter_events(x86_pmu_events_group
.attrs
);
1576 if (x86_pmu
.cpu_events
) {
1577 struct attribute
**tmp
;
1579 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1581 x86_pmu_events_group
.attrs
= tmp
;
1584 pr_info("... version: %d\n", x86_pmu
.version
);
1585 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1586 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1587 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1588 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1589 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1590 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1592 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1593 perf_cpu_notifier(x86_pmu_notifier
);
1597 early_initcall(init_hw_perf_events
);
1599 static inline void x86_pmu_read(struct perf_event
*event
)
1601 x86_perf_event_update(event
);
1605 * Start group events scheduling transaction
1606 * Set the flag to make pmu::enable() not perform the
1607 * schedulability test, it will be performed at commit time
1609 static void x86_pmu_start_txn(struct pmu
*pmu
)
1611 perf_pmu_disable(pmu
);
1612 __this_cpu_or(cpu_hw_events
.group_flag
, PERF_EVENT_TXN
);
1613 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1617 * Stop group events scheduling transaction
1618 * Clear the flag and pmu::enable() will perform the
1619 * schedulability test.
1621 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1623 __this_cpu_and(cpu_hw_events
.group_flag
, ~PERF_EVENT_TXN
);
1625 * Truncate collected array by the number of events added in this
1626 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1628 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1629 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1630 perf_pmu_enable(pmu
);
1634 * Commit group events scheduling transaction
1635 * Perform the group schedulability test as a whole
1636 * Return 0 if success
1638 * Does not cancel the transaction on failure; expects the caller to do this.
1640 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1642 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1643 int assign
[X86_PMC_IDX_MAX
];
1648 if (!x86_pmu_initialized())
1651 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1656 * copy new assignment, now we know it is possible
1657 * will be used by hw_perf_enable()
1659 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1661 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1662 perf_pmu_enable(pmu
);
1666 * a fake_cpuc is used to validate event groups. Due to
1667 * the extra reg logic, we need to also allocate a fake
1668 * per_core and per_cpu structure. Otherwise, group events
1669 * using extra reg may conflict without the kernel being
1670 * able to catch this when the last event gets added to
1673 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1675 kfree(cpuc
->shared_regs
);
1679 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1681 struct cpu_hw_events
*cpuc
;
1682 int cpu
= raw_smp_processor_id();
1684 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1686 return ERR_PTR(-ENOMEM
);
1688 /* only needed, if we have extra_regs */
1689 if (x86_pmu
.extra_regs
) {
1690 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1691 if (!cpuc
->shared_regs
)
1697 free_fake_cpuc(cpuc
);
1698 return ERR_PTR(-ENOMEM
);
1702 * validate that we can schedule this event
1704 static int validate_event(struct perf_event
*event
)
1706 struct cpu_hw_events
*fake_cpuc
;
1707 struct event_constraint
*c
;
1710 fake_cpuc
= allocate_fake_cpuc();
1711 if (IS_ERR(fake_cpuc
))
1712 return PTR_ERR(fake_cpuc
);
1714 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1716 if (!c
|| !c
->weight
)
1719 if (x86_pmu
.put_event_constraints
)
1720 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1722 free_fake_cpuc(fake_cpuc
);
1728 * validate a single event group
1730 * validation include:
1731 * - check events are compatible which each other
1732 * - events do not compete for the same counter
1733 * - number of events <= number of counters
1735 * validation ensures the group can be loaded onto the
1736 * PMU if it was the only group available.
1738 static int validate_group(struct perf_event
*event
)
1740 struct perf_event
*leader
= event
->group_leader
;
1741 struct cpu_hw_events
*fake_cpuc
;
1742 int ret
= -EINVAL
, n
;
1744 fake_cpuc
= allocate_fake_cpuc();
1745 if (IS_ERR(fake_cpuc
))
1746 return PTR_ERR(fake_cpuc
);
1748 * the event is not yet connected with its
1749 * siblings therefore we must first collect
1750 * existing siblings, then add the new event
1751 * before we can simulate the scheduling
1753 n
= collect_events(fake_cpuc
, leader
, true);
1757 fake_cpuc
->n_events
= n
;
1758 n
= collect_events(fake_cpuc
, event
, false);
1762 fake_cpuc
->n_events
= n
;
1764 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1767 free_fake_cpuc(fake_cpuc
);
1771 static int x86_pmu_event_init(struct perf_event
*event
)
1776 switch (event
->attr
.type
) {
1778 case PERF_TYPE_HARDWARE
:
1779 case PERF_TYPE_HW_CACHE
:
1786 err
= __x86_pmu_event_init(event
);
1789 * we temporarily connect event to its pmu
1790 * such that validate_group() can classify
1791 * it as an x86 event using is_x86_event()
1796 if (event
->group_leader
!= event
)
1797 err
= validate_group(event
);
1799 err
= validate_event(event
);
1805 event
->destroy(event
);
1811 static int x86_pmu_event_idx(struct perf_event
*event
)
1813 int idx
= event
->hw
.idx
;
1815 if (!x86_pmu
.attr_rdpmc
)
1818 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
1819 idx
-= INTEL_PMC_IDX_FIXED
;
1826 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
1827 struct device_attribute
*attr
,
1830 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
1833 static void change_rdpmc(void *info
)
1835 bool enable
= !!(unsigned long)info
;
1838 cr4_set_bits(X86_CR4_PCE
);
1840 cr4_clear_bits(X86_CR4_PCE
);
1843 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
1844 struct device_attribute
*attr
,
1845 const char *buf
, size_t count
)
1850 ret
= kstrtoul(buf
, 0, &val
);
1854 if (x86_pmu
.attr_rdpmc_broken
)
1857 if (!!val
!= !!x86_pmu
.attr_rdpmc
) {
1858 x86_pmu
.attr_rdpmc
= !!val
;
1859 on_each_cpu(change_rdpmc
, (void *)val
, 1);
1865 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
1867 static struct attribute
*x86_pmu_attrs
[] = {
1868 &dev_attr_rdpmc
.attr
,
1872 static struct attribute_group x86_pmu_attr_group
= {
1873 .attrs
= x86_pmu_attrs
,
1876 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
1877 &x86_pmu_attr_group
,
1878 &x86_pmu_format_group
,
1879 &x86_pmu_events_group
,
1883 static void x86_pmu_flush_branch_stack(void)
1885 if (x86_pmu
.flush_branch_stack
)
1886 x86_pmu
.flush_branch_stack();
1889 void perf_check_microcode(void)
1891 if (x86_pmu
.check_microcode
)
1892 x86_pmu
.check_microcode();
1894 EXPORT_SYMBOL_GPL(perf_check_microcode
);
1896 static struct pmu pmu
= {
1897 .pmu_enable
= x86_pmu_enable
,
1898 .pmu_disable
= x86_pmu_disable
,
1900 .attr_groups
= x86_pmu_attr_groups
,
1902 .event_init
= x86_pmu_event_init
,
1906 .start
= x86_pmu_start
,
1907 .stop
= x86_pmu_stop
,
1908 .read
= x86_pmu_read
,
1910 .start_txn
= x86_pmu_start_txn
,
1911 .cancel_txn
= x86_pmu_cancel_txn
,
1912 .commit_txn
= x86_pmu_commit_txn
,
1914 .event_idx
= x86_pmu_event_idx
,
1915 .flush_branch_stack
= x86_pmu_flush_branch_stack
,
1918 void arch_perf_update_userpage(struct perf_event_mmap_page
*userpg
, u64 now
)
1920 struct cyc2ns_data
*data
;
1922 userpg
->cap_user_time
= 0;
1923 userpg
->cap_user_time_zero
= 0;
1924 userpg
->cap_user_rdpmc
= x86_pmu
.attr_rdpmc
;
1925 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
1927 if (!sched_clock_stable())
1930 data
= cyc2ns_read_begin();
1932 userpg
->cap_user_time
= 1;
1933 userpg
->time_mult
= data
->cyc2ns_mul
;
1934 userpg
->time_shift
= data
->cyc2ns_shift
;
1935 userpg
->time_offset
= data
->cyc2ns_offset
- now
;
1937 userpg
->cap_user_time_zero
= 1;
1938 userpg
->time_zero
= data
->cyc2ns_offset
;
1940 cyc2ns_read_end(data
);
1947 static int backtrace_stack(void *data
, char *name
)
1952 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1954 struct perf_callchain_entry
*entry
= data
;
1956 perf_callchain_store(entry
, addr
);
1959 static const struct stacktrace_ops backtrace_ops
= {
1960 .stack
= backtrace_stack
,
1961 .address
= backtrace_address
,
1962 .walk_stack
= print_context_stack_bp
,
1966 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1968 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1969 /* TODO: We don't support guest os callchain now */
1973 perf_callchain_store(entry
, regs
->ip
);
1975 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
1979 valid_user_frame(const void __user
*fp
, unsigned long size
)
1981 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
1984 static unsigned long get_segment_base(unsigned int segment
)
1986 struct desc_struct
*desc
;
1987 int idx
= segment
>> 3;
1989 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
1990 if (idx
> LDT_ENTRIES
)
1993 if (idx
> current
->active_mm
->context
.size
)
1996 desc
= current
->active_mm
->context
.ldt
;
1998 if (idx
> GDT_ENTRIES
)
2001 desc
= raw_cpu_ptr(gdt_page
.gdt
);
2004 return get_desc_base(desc
+ idx
);
2007 #ifdef CONFIG_COMPAT
2009 #include <asm/compat.h>
2012 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2014 /* 32-bit process in 64-bit kernel. */
2015 unsigned long ss_base
, cs_base
;
2016 struct stack_frame_ia32 frame
;
2017 const void __user
*fp
;
2019 if (!test_thread_flag(TIF_IA32
))
2022 cs_base
= get_segment_base(regs
->cs
);
2023 ss_base
= get_segment_base(regs
->ss
);
2025 fp
= compat_ptr(ss_base
+ regs
->bp
);
2026 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2027 unsigned long bytes
;
2028 frame
.next_frame
= 0;
2029 frame
.return_address
= 0;
2031 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
2035 if (!valid_user_frame(fp
, sizeof(frame
)))
2038 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2039 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2045 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2052 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2054 struct stack_frame frame
;
2055 const void __user
*fp
;
2057 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2058 /* TODO: We don't support guest os callchain now */
2063 * We don't know what to do with VM86 stacks.. ignore them for now.
2065 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2068 fp
= (void __user
*)regs
->bp
;
2070 perf_callchain_store(entry
, regs
->ip
);
2075 if (perf_callchain_user32(regs
, entry
))
2078 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2079 unsigned long bytes
;
2080 frame
.next_frame
= NULL
;
2081 frame
.return_address
= 0;
2083 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
2087 if (!valid_user_frame(fp
, sizeof(frame
)))
2090 perf_callchain_store(entry
, frame
.return_address
);
2091 fp
= frame
.next_frame
;
2096 * Deal with code segment offsets for the various execution modes:
2098 * VM86 - the good olde 16 bit days, where the linear address is
2099 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2101 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2102 * to figure out what the 32bit base address is.
2104 * X32 - has TIF_X32 set, but is running in x86_64
2106 * X86_64 - CS,DS,SS,ES are all zero based.
2108 static unsigned long code_segment_base(struct pt_regs
*regs
)
2111 * If we are in VM86 mode, add the segment offset to convert to a
2114 if (regs
->flags
& X86_VM_MASK
)
2115 return 0x10 * regs
->cs
;
2118 * For IA32 we look at the GDT/LDT segment base to convert the
2119 * effective IP to a linear address.
2121 #ifdef CONFIG_X86_32
2122 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2123 return get_segment_base(regs
->cs
);
2125 if (test_thread_flag(TIF_IA32
)) {
2126 if (user_mode(regs
) && regs
->cs
!= __USER32_CS
)
2127 return get_segment_base(regs
->cs
);
2133 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2135 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2136 return perf_guest_cbs
->get_guest_ip();
2138 return regs
->ip
+ code_segment_base(regs
);
2141 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2145 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2146 if (perf_guest_cbs
->is_user_mode())
2147 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2149 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2151 if (user_mode(regs
))
2152 misc
|= PERF_RECORD_MISC_USER
;
2154 misc
|= PERF_RECORD_MISC_KERNEL
;
2157 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2158 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2163 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2165 cap
->version
= x86_pmu
.version
;
2166 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2167 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2168 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2169 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2170 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2171 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2173 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);