2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
51 unsigned long offset
, addr
= (unsigned long)from
;
52 int type
= in_nmi() ? KM_NMI
: KM_IRQ0
;
53 unsigned long size
, len
= 0;
59 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
63 offset
= addr
& (PAGE_SIZE
- 1);
64 size
= min(PAGE_SIZE
- offset
, n
- len
);
66 map
= kmap_atomic(page
, type
);
67 memcpy(to
, map
+offset
, size
);
68 kunmap_atomic(map
, type
);
80 struct event_constraint
{
82 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
91 int nb_id
; /* NorthBridge id */
92 int refcnt
; /* reference count */
93 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
94 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
97 #define MAX_LBR_ENTRIES 16
99 struct cpu_hw_events
{
101 * Generic x86 PMC bits
103 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
104 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
105 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
111 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
112 u64 tags
[X86_PMC_IDX_MAX
];
113 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
115 unsigned int group_flag
;
118 * Intel DebugStore bits
120 struct debug_store
*ds
;
128 struct perf_branch_stack lbr_stack
;
129 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
134 struct amd_nb
*amd_nb
;
137 #define __EVENT_CONSTRAINT(c, n, m, w) {\
138 { .idxmsk64 = (n) }, \
144 #define EVENT_CONSTRAINT(c, n, m) \
145 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
148 * Constraint on the Event code.
150 #define INTEL_EVENT_CONSTRAINT(c, n) \
151 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
154 * Constraint on the Event code + UMask + fixed-mask
156 * filter mask to validate fixed counter events.
157 * the following filters disqualify for fixed counters:
161 * The other filters are supported by fixed counters.
162 * The any-thread option is supported starting with v3.
164 #define FIXED_EVENT_CONSTRAINT(c, n) \
165 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
168 * Constraint on the Event code + UMask
170 #define PEBS_EVENT_CONSTRAINT(c, n) \
171 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
173 #define EVENT_CONSTRAINT_END \
174 EVENT_CONSTRAINT(0, 0, 0)
176 #define for_each_event_constraint(e, c) \
177 for ((e) = (c); (e)->weight; (e)++)
179 union perf_capabilities
{
183 u64 pebs_arch_reg
: 1;
191 * struct x86_pmu - generic x86 pmu
195 * Generic x86 PMC bits
199 int (*handle_irq
)(struct pt_regs
*);
200 void (*disable_all
)(void);
201 void (*enable_all
)(int added
);
202 void (*enable
)(struct perf_event
*);
203 void (*disable
)(struct perf_event
*);
204 int (*hw_config
)(struct perf_event
*event
);
205 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
208 u64 (*event_map
)(int);
211 int num_counters_fixed
;
216 struct event_constraint
*
217 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
218 struct perf_event
*event
);
220 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
221 struct perf_event
*event
);
222 struct event_constraint
*event_constraints
;
223 void (*quirks
)(void);
224 int perfctr_second_write
;
226 int (*cpu_prepare
)(int cpu
);
227 void (*cpu_starting
)(int cpu
);
228 void (*cpu_dying
)(int cpu
);
229 void (*cpu_dead
)(int cpu
);
232 * Intel Arch Perfmon v2+
235 union perf_capabilities intel_cap
;
238 * Intel DebugStore bits
241 int pebs_record_size
;
242 void (*drain_pebs
)(struct pt_regs
*regs
);
243 struct event_constraint
*pebs_constraints
;
248 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
249 int lbr_nr
; /* hardware stack size */
252 static struct x86_pmu x86_pmu __read_mostly
;
254 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
258 static int x86_perf_event_set_period(struct perf_event
*event
);
261 * Generalized hw caching related hw_event table, filled
262 * in on a per model basis. A value of 0 means
263 * 'not supported', -1 means 'hw_event makes no sense on
264 * this CPU', any other value means the raw hw_event
268 #define C(x) PERF_COUNT_HW_CACHE_##x
270 static u64 __read_mostly hw_cache_event_ids
271 [PERF_COUNT_HW_CACHE_MAX
]
272 [PERF_COUNT_HW_CACHE_OP_MAX
]
273 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
276 * Propagate event elapsed time into the generic event.
277 * Can only be executed on the CPU where the event is active.
278 * Returns the delta events processed.
281 x86_perf_event_update(struct perf_event
*event
)
283 struct hw_perf_event
*hwc
= &event
->hw
;
284 int shift
= 64 - x86_pmu
.cntval_bits
;
285 u64 prev_raw_count
, new_raw_count
;
289 if (idx
== X86_PMC_IDX_FIXED_BTS
)
293 * Careful: an NMI might modify the previous event value.
295 * Our tactic to handle this is to first atomically read and
296 * exchange a new raw count - then add that new-prev delta
297 * count to the generic event atomically:
300 prev_raw_count
= local64_read(&hwc
->prev_count
);
301 rdmsrl(hwc
->event_base
+ idx
, new_raw_count
);
303 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
304 new_raw_count
) != prev_raw_count
)
308 * Now we have the new raw value and have updated the prev
309 * timestamp already. We can now calculate the elapsed delta
310 * (event-)time and add that to the generic event.
312 * Careful, not all hw sign-extends above the physical width
315 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
318 local64_add(delta
, &event
->count
);
319 local64_sub(delta
, &hwc
->period_left
);
321 return new_raw_count
;
324 static atomic_t active_events
;
325 static DEFINE_MUTEX(pmc_reserve_mutex
);
327 #ifdef CONFIG_X86_LOCAL_APIC
329 static bool reserve_pmc_hardware(void)
333 if (nmi_watchdog
== NMI_LOCAL_APIC
)
334 disable_lapic_nmi_watchdog();
336 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
337 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
341 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
342 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
349 for (i
--; i
>= 0; i
--)
350 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
352 i
= x86_pmu
.num_counters
;
355 for (i
--; i
>= 0; i
--)
356 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
358 if (nmi_watchdog
== NMI_LOCAL_APIC
)
359 enable_lapic_nmi_watchdog();
364 static void release_pmc_hardware(void)
368 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
369 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
370 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
373 if (nmi_watchdog
== NMI_LOCAL_APIC
)
374 enable_lapic_nmi_watchdog();
379 static bool reserve_pmc_hardware(void) { return true; }
380 static void release_pmc_hardware(void) {}
384 static int reserve_ds_buffers(void);
385 static void release_ds_buffers(void);
387 static void hw_perf_event_destroy(struct perf_event
*event
)
389 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
390 release_pmc_hardware();
391 release_ds_buffers();
392 mutex_unlock(&pmc_reserve_mutex
);
396 static inline int x86_pmu_initialized(void)
398 return x86_pmu
.handle_irq
!= NULL
;
402 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event_attr
*attr
)
404 unsigned int cache_type
, cache_op
, cache_result
;
407 config
= attr
->config
;
409 cache_type
= (config
>> 0) & 0xff;
410 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
413 cache_op
= (config
>> 8) & 0xff;
414 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
417 cache_result
= (config
>> 16) & 0xff;
418 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
421 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
434 static int x86_setup_perfctr(struct perf_event
*event
)
436 struct perf_event_attr
*attr
= &event
->attr
;
437 struct hw_perf_event
*hwc
= &event
->hw
;
440 if (!hwc
->sample_period
) {
441 hwc
->sample_period
= x86_pmu
.max_period
;
442 hwc
->last_period
= hwc
->sample_period
;
443 local64_set(&hwc
->period_left
, hwc
->sample_period
);
446 * If we have a PMU initialized but no APIC
447 * interrupts, we cannot sample hardware
448 * events (user-space has to fall back and
449 * sample via a hrtimer based software event):
455 if (attr
->type
== PERF_TYPE_RAW
)
458 if (attr
->type
== PERF_TYPE_HW_CACHE
)
459 return set_ext_hw_attr(hwc
, attr
);
461 if (attr
->config
>= x86_pmu
.max_events
)
467 config
= x86_pmu
.event_map(attr
->config
);
478 if ((attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
) &&
479 (hwc
->sample_period
== 1)) {
480 /* BTS is not supported by this architecture. */
484 /* BTS is currently only allowed for user-mode. */
485 if (!attr
->exclude_kernel
)
489 hwc
->config
|= config
;
494 static int x86_pmu_hw_config(struct perf_event
*event
)
496 if (event
->attr
.precise_ip
) {
499 /* Support for constant skid */
503 /* Support for IP fixup */
507 if (event
->attr
.precise_ip
> precise
)
513 * (keep 'enabled' bit clear for now)
515 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
518 * Count user and OS events unless requested not to
520 if (!event
->attr
.exclude_user
)
521 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
522 if (!event
->attr
.exclude_kernel
)
523 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
525 if (event
->attr
.type
== PERF_TYPE_RAW
)
526 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
528 return x86_setup_perfctr(event
);
532 * Setup the hardware configuration for a given attr_type
534 static int __x86_pmu_event_init(struct perf_event
*event
)
538 if (!x86_pmu_initialized())
542 if (!atomic_inc_not_zero(&active_events
)) {
543 mutex_lock(&pmc_reserve_mutex
);
544 if (atomic_read(&active_events
) == 0) {
545 if (!reserve_pmc_hardware())
548 err
= reserve_ds_buffers();
550 release_pmc_hardware();
554 atomic_inc(&active_events
);
555 mutex_unlock(&pmc_reserve_mutex
);
560 event
->destroy
= hw_perf_event_destroy
;
563 event
->hw
.last_cpu
= -1;
564 event
->hw
.last_tag
= ~0ULL;
566 return x86_pmu
.hw_config(event
);
569 static void x86_pmu_disable_all(void)
571 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
574 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
577 if (!test_bit(idx
, cpuc
->active_mask
))
579 rdmsrl(x86_pmu
.eventsel
+ idx
, val
);
580 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
582 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
583 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
587 static void x86_pmu_disable(struct pmu
*pmu
)
589 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
591 if (!x86_pmu_initialized())
601 x86_pmu
.disable_all();
604 static void x86_pmu_enable_all(int added
)
606 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
609 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
610 struct perf_event
*event
= cpuc
->events
[idx
];
613 if (!test_bit(idx
, cpuc
->active_mask
))
616 val
= event
->hw
.config
;
617 val
|= ARCH_PERFMON_EVENTSEL_ENABLE
;
618 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
622 static struct pmu pmu
;
624 static inline int is_x86_event(struct perf_event
*event
)
626 return event
->pmu
== &pmu
;
629 static int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
631 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
632 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
633 int i
, j
, w
, wmax
, num
= 0;
634 struct hw_perf_event
*hwc
;
636 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
638 for (i
= 0; i
< n
; i
++) {
639 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
644 * fastpath, try to reuse previous register
646 for (i
= 0; i
< n
; i
++) {
647 hwc
= &cpuc
->event_list
[i
]->hw
;
654 /* constraint still honored */
655 if (!test_bit(hwc
->idx
, c
->idxmsk
))
658 /* not already used */
659 if (test_bit(hwc
->idx
, used_mask
))
662 __set_bit(hwc
->idx
, used_mask
);
664 assign
[i
] = hwc
->idx
;
673 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
676 * weight = number of possible counters
678 * 1 = most constrained, only works on one counter
679 * wmax = least constrained, works on any counter
681 * assign events to counters starting with most
682 * constrained events.
684 wmax
= x86_pmu
.num_counters
;
687 * when fixed event counters are present,
688 * wmax is incremented by 1 to account
689 * for one more choice
691 if (x86_pmu
.num_counters_fixed
)
694 for (w
= 1, num
= n
; num
&& w
<= wmax
; w
++) {
696 for (i
= 0; num
&& i
< n
; i
++) {
698 hwc
= &cpuc
->event_list
[i
]->hw
;
703 for_each_set_bit(j
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
704 if (!test_bit(j
, used_mask
))
708 if (j
== X86_PMC_IDX_MAX
)
711 __set_bit(j
, used_mask
);
720 * scheduling failed or is just a simulation,
721 * free resources if necessary
723 if (!assign
|| num
) {
724 for (i
= 0; i
< n
; i
++) {
725 if (x86_pmu
.put_event_constraints
)
726 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
729 return num
? -ENOSPC
: 0;
733 * dogrp: true if must collect siblings events (group)
734 * returns total number of events and error code
736 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
738 struct perf_event
*event
;
741 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
743 /* current number of events already accepted */
746 if (is_x86_event(leader
)) {
749 cpuc
->event_list
[n
] = leader
;
755 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
756 if (!is_x86_event(event
) ||
757 event
->state
<= PERF_EVENT_STATE_OFF
)
763 cpuc
->event_list
[n
] = event
;
769 static inline void x86_assign_hw_event(struct perf_event
*event
,
770 struct cpu_hw_events
*cpuc
, int i
)
772 struct hw_perf_event
*hwc
= &event
->hw
;
774 hwc
->idx
= cpuc
->assign
[i
];
775 hwc
->last_cpu
= smp_processor_id();
776 hwc
->last_tag
= ++cpuc
->tags
[i
];
778 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
779 hwc
->config_base
= 0;
781 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
782 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
784 * We set it so that event_base + idx in wrmsr/rdmsr maps to
785 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
788 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
790 hwc
->config_base
= x86_pmu
.eventsel
;
791 hwc
->event_base
= x86_pmu
.perfctr
;
795 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
796 struct cpu_hw_events
*cpuc
,
799 return hwc
->idx
== cpuc
->assign
[i
] &&
800 hwc
->last_cpu
== smp_processor_id() &&
801 hwc
->last_tag
== cpuc
->tags
[i
];
804 static void x86_pmu_start(struct perf_event
*event
, int flags
);
805 static void x86_pmu_stop(struct perf_event
*event
, int flags
);
807 static void x86_pmu_enable(struct pmu
*pmu
)
809 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
810 struct perf_event
*event
;
811 struct hw_perf_event
*hwc
;
812 int i
, added
= cpuc
->n_added
;
814 if (!x86_pmu_initialized())
821 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
823 * apply assignment obtained either from
824 * hw_perf_group_sched_in() or x86_pmu_enable()
826 * step1: save events moving to new counters
827 * step2: reprogram moved events into new counters
829 for (i
= 0; i
< n_running
; i
++) {
830 event
= cpuc
->event_list
[i
];
834 * we can avoid reprogramming counter if:
835 * - assigned same counter as last time
836 * - running on same CPU as last time
837 * - no other event has used the counter since
839 if (hwc
->idx
== -1 ||
840 match_prev_assignment(hwc
, cpuc
, i
))
844 * Ensure we don't accidentally enable a stopped
845 * counter simply because we rescheduled.
847 if (hwc
->state
& PERF_HES_STOPPED
)
848 hwc
->state
|= PERF_HES_ARCH
;
850 x86_pmu_stop(event
, PERF_EF_UPDATE
);
853 for (i
= 0; i
< cpuc
->n_events
; i
++) {
854 event
= cpuc
->event_list
[i
];
857 if (!match_prev_assignment(hwc
, cpuc
, i
))
858 x86_assign_hw_event(event
, cpuc
, i
);
859 else if (i
< n_running
)
862 if (hwc
->state
& PERF_HES_ARCH
)
865 x86_pmu_start(event
, PERF_EF_RELOAD
);
868 perf_events_lapic_init();
874 x86_pmu
.enable_all(added
);
877 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
880 wrmsrl(hwc
->config_base
+ hwc
->idx
, hwc
->config
| enable_mask
);
883 static inline void x86_pmu_disable_event(struct perf_event
*event
)
885 struct hw_perf_event
*hwc
= &event
->hw
;
887 wrmsrl(hwc
->config_base
+ hwc
->idx
, hwc
->config
);
890 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
893 * Set the next IRQ period, based on the hwc->period_left value.
894 * To be called with the event disabled in hw:
897 x86_perf_event_set_period(struct perf_event
*event
)
899 struct hw_perf_event
*hwc
= &event
->hw
;
900 s64 left
= local64_read(&hwc
->period_left
);
901 s64 period
= hwc
->sample_period
;
902 int ret
= 0, idx
= hwc
->idx
;
904 if (idx
== X86_PMC_IDX_FIXED_BTS
)
908 * If we are way outside a reasonable range then just skip forward:
910 if (unlikely(left
<= -period
)) {
912 local64_set(&hwc
->period_left
, left
);
913 hwc
->last_period
= period
;
917 if (unlikely(left
<= 0)) {
919 local64_set(&hwc
->period_left
, left
);
920 hwc
->last_period
= period
;
924 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
926 if (unlikely(left
< 2))
929 if (left
> x86_pmu
.max_period
)
930 left
= x86_pmu
.max_period
;
932 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
935 * The hw event starts counting from this event offset,
936 * mark it to be able to extra future deltas:
938 local64_set(&hwc
->prev_count
, (u64
)-left
);
940 wrmsrl(hwc
->event_base
+ idx
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
943 * Due to erratum on certan cpu we need
944 * a second write to be sure the register
945 * is updated properly
947 if (x86_pmu
.perfctr_second_write
) {
948 wrmsrl(hwc
->event_base
+ idx
,
949 (u64
)(-left
) & x86_pmu
.cntval_mask
);
952 perf_event_update_userpage(event
);
957 static void x86_pmu_enable_event(struct perf_event
*event
)
959 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
961 __x86_pmu_enable_event(&event
->hw
,
962 ARCH_PERFMON_EVENTSEL_ENABLE
);
966 * Add a single event to the PMU.
968 * The event is added to the group of enabled events
969 * but only if it can be scehduled with existing events.
971 static int x86_pmu_add(struct perf_event
*event
, int flags
)
973 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
974 struct hw_perf_event
*hwc
;
975 int assign
[X86_PMC_IDX_MAX
];
980 perf_pmu_disable(event
->pmu
);
982 ret
= n
= collect_events(cpuc
, event
, false);
986 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
987 if (!(flags
& PERF_EF_START
))
988 hwc
->state
|= PERF_HES_ARCH
;
991 * If group events scheduling transaction was started,
992 * skip the schedulability test here, it will be peformed
993 * at commit time (->commit_txn) as a whole
995 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
998 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1002 * copy new assignment, now we know it is possible
1003 * will be used by hw_perf_enable()
1005 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1009 cpuc
->n_added
+= n
- n0
;
1010 cpuc
->n_txn
+= n
- n0
;
1014 perf_pmu_enable(event
->pmu
);
1018 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1020 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1021 int idx
= event
->hw
.idx
;
1023 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1026 if (WARN_ON_ONCE(idx
== -1))
1029 if (flags
& PERF_EF_RELOAD
) {
1030 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1031 x86_perf_event_set_period(event
);
1034 event
->hw
.state
= 0;
1036 cpuc
->events
[idx
] = event
;
1037 __set_bit(idx
, cpuc
->active_mask
);
1038 __set_bit(idx
, cpuc
->running
);
1039 x86_pmu
.enable(event
);
1040 perf_event_update_userpage(event
);
1043 void perf_event_print_debug(void)
1045 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1047 struct cpu_hw_events
*cpuc
;
1048 unsigned long flags
;
1051 if (!x86_pmu
.num_counters
)
1054 local_irq_save(flags
);
1056 cpu
= smp_processor_id();
1057 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1059 if (x86_pmu
.version
>= 2) {
1060 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1061 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1062 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1063 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1064 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1067 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1068 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1069 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1070 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1071 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1073 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1075 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1076 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1077 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1079 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1081 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1082 cpu
, idx
, pmc_ctrl
);
1083 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1084 cpu
, idx
, pmc_count
);
1085 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1086 cpu
, idx
, prev_left
);
1088 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1089 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1091 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1092 cpu
, idx
, pmc_count
);
1094 local_irq_restore(flags
);
1097 static void x86_pmu_stop(struct perf_event
*event
, int flags
)
1099 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1100 struct hw_perf_event
*hwc
= &event
->hw
;
1102 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1103 x86_pmu
.disable(event
);
1104 cpuc
->events
[hwc
->idx
] = NULL
;
1105 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1106 hwc
->state
|= PERF_HES_STOPPED
;
1109 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1111 * Drain the remaining delta count out of a event
1112 * that we are disabling:
1114 x86_perf_event_update(event
);
1115 hwc
->state
|= PERF_HES_UPTODATE
;
1119 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1121 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1125 * If we're called during a txn, we don't need to do anything.
1126 * The events never got scheduled and ->cancel_txn will truncate
1129 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1132 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1134 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1135 if (event
== cpuc
->event_list
[i
]) {
1137 if (x86_pmu
.put_event_constraints
)
1138 x86_pmu
.put_event_constraints(cpuc
, event
);
1140 while (++i
< cpuc
->n_events
)
1141 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1147 perf_event_update_userpage(event
);
1150 static int x86_pmu_handle_irq(struct pt_regs
*regs
)
1152 struct perf_sample_data data
;
1153 struct cpu_hw_events
*cpuc
;
1154 struct perf_event
*event
;
1155 int idx
, handled
= 0;
1158 perf_sample_data_init(&data
, 0);
1160 cpuc
= &__get_cpu_var(cpu_hw_events
);
1162 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1163 if (!test_bit(idx
, cpuc
->active_mask
)) {
1165 * Though we deactivated the counter some cpus
1166 * might still deliver spurious interrupts still
1167 * in flight. Catch them:
1169 if (__test_and_clear_bit(idx
, cpuc
->running
))
1174 event
= cpuc
->events
[idx
];
1176 val
= x86_perf_event_update(event
);
1177 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1184 data
.period
= event
->hw
.last_period
;
1186 if (!x86_perf_event_set_period(event
))
1189 if (perf_event_overflow(event
, 1, &data
, regs
))
1190 x86_pmu_stop(event
, 0);
1194 inc_irq_stat(apic_perf_irqs
);
1199 void perf_events_lapic_init(void)
1201 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1205 * Always use NMI for PMU
1207 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1210 struct pmu_nmi_state
{
1211 unsigned int marked
;
1215 static DEFINE_PER_CPU(struct pmu_nmi_state
, pmu_nmi
);
1217 static int __kprobes
1218 perf_event_nmi_handler(struct notifier_block
*self
,
1219 unsigned long cmd
, void *__args
)
1221 struct die_args
*args
= __args
;
1222 unsigned int this_nmi
;
1225 if (!atomic_read(&active_events
))
1232 case DIE_NMIUNKNOWN
:
1233 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1234 if (this_nmi
!= __get_cpu_var(pmu_nmi
).marked
)
1235 /* let the kernel handle the unknown nmi */
1238 * This one is a PMU back-to-back nmi. Two events
1239 * trigger 'simultaneously' raising two back-to-back
1240 * NMIs. If the first NMI handles both, the latter
1241 * will be empty and daze the CPU. So, we drop it to
1242 * avoid false-positive 'unknown nmi' messages.
1249 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1251 handled
= x86_pmu
.handle_irq(args
->regs
);
1255 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1256 if ((handled
> 1) ||
1257 /* the next nmi could be a back-to-back nmi */
1258 ((__get_cpu_var(pmu_nmi
).marked
== this_nmi
) &&
1259 (__get_cpu_var(pmu_nmi
).handled
> 1))) {
1261 * We could have two subsequent back-to-back nmis: The
1262 * first handles more than one counter, the 2nd
1263 * handles only one counter and the 3rd handles no
1266 * This is the 2nd nmi because the previous was
1267 * handling more than one counter. We will mark the
1268 * next (3rd) and then drop it if unhandled.
1270 __get_cpu_var(pmu_nmi
).marked
= this_nmi
+ 1;
1271 __get_cpu_var(pmu_nmi
).handled
= handled
;
1277 static __read_mostly
struct notifier_block perf_event_nmi_notifier
= {
1278 .notifier_call
= perf_event_nmi_handler
,
1283 static struct event_constraint unconstrained
;
1284 static struct event_constraint emptyconstraint
;
1286 static struct event_constraint
*
1287 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
)
1289 struct event_constraint
*c
;
1291 if (x86_pmu
.event_constraints
) {
1292 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1293 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
1298 return &unconstrained
;
1301 #include "perf_event_amd.c"
1302 #include "perf_event_p6.c"
1303 #include "perf_event_p4.c"
1304 #include "perf_event_intel_lbr.c"
1305 #include "perf_event_intel_ds.c"
1306 #include "perf_event_intel.c"
1308 static int __cpuinit
1309 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1311 unsigned int cpu
= (long)hcpu
;
1312 int ret
= NOTIFY_OK
;
1314 switch (action
& ~CPU_TASKS_FROZEN
) {
1315 case CPU_UP_PREPARE
:
1316 if (x86_pmu
.cpu_prepare
)
1317 ret
= x86_pmu
.cpu_prepare(cpu
);
1321 if (x86_pmu
.cpu_starting
)
1322 x86_pmu
.cpu_starting(cpu
);
1326 if (x86_pmu
.cpu_dying
)
1327 x86_pmu
.cpu_dying(cpu
);
1330 case CPU_UP_CANCELED
:
1332 if (x86_pmu
.cpu_dead
)
1333 x86_pmu
.cpu_dead(cpu
);
1343 static void __init
pmu_check_apic(void)
1349 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1350 pr_info("no hardware sampling interrupt available.\n");
1353 void __init
init_hw_perf_events(void)
1355 struct event_constraint
*c
;
1358 pr_info("Performance Events: ");
1360 switch (boot_cpu_data
.x86_vendor
) {
1361 case X86_VENDOR_INTEL
:
1362 err
= intel_pmu_init();
1364 case X86_VENDOR_AMD
:
1365 err
= amd_pmu_init();
1371 pr_cont("no PMU driver, software events only.\n");
1377 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1382 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1383 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1384 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1385 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1387 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1389 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1390 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1391 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1392 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1395 x86_pmu
.intel_ctrl
|=
1396 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1398 perf_events_lapic_init();
1399 register_die_notifier(&perf_event_nmi_notifier
);
1401 unconstrained
= (struct event_constraint
)
1402 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1403 0, x86_pmu
.num_counters
);
1405 if (x86_pmu
.event_constraints
) {
1406 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1407 if (c
->cmask
!= X86_RAW_EVENT_MASK
)
1410 c
->idxmsk64
|= (1ULL << x86_pmu
.num_counters
) - 1;
1411 c
->weight
+= x86_pmu
.num_counters
;
1415 pr_info("... version: %d\n", x86_pmu
.version
);
1416 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1417 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1418 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1419 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1420 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1421 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1423 perf_pmu_register(&pmu
);
1424 perf_cpu_notifier(x86_pmu_notifier
);
1427 static inline void x86_pmu_read(struct perf_event
*event
)
1429 x86_perf_event_update(event
);
1433 * Start group events scheduling transaction
1434 * Set the flag to make pmu::enable() not perform the
1435 * schedulability test, it will be performed at commit time
1437 static void x86_pmu_start_txn(struct pmu
*pmu
)
1439 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1441 perf_pmu_disable(pmu
);
1442 cpuc
->group_flag
|= PERF_EVENT_TXN
;
1447 * Stop group events scheduling transaction
1448 * Clear the flag and pmu::enable() will perform the
1449 * schedulability test.
1451 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1453 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1455 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1457 * Truncate the collected events.
1459 cpuc
->n_added
-= cpuc
->n_txn
;
1460 cpuc
->n_events
-= cpuc
->n_txn
;
1461 perf_pmu_enable(pmu
);
1465 * Commit group events scheduling transaction
1466 * Perform the group schedulability test as a whole
1467 * Return 0 if success
1469 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1471 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1472 int assign
[X86_PMC_IDX_MAX
];
1477 if (!x86_pmu_initialized())
1480 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1485 * copy new assignment, now we know it is possible
1486 * will be used by hw_perf_enable()
1488 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1490 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1491 perf_pmu_enable(pmu
);
1496 * validate that we can schedule this event
1498 static int validate_event(struct perf_event
*event
)
1500 struct cpu_hw_events
*fake_cpuc
;
1501 struct event_constraint
*c
;
1504 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1508 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1510 if (!c
|| !c
->weight
)
1513 if (x86_pmu
.put_event_constraints
)
1514 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1522 * validate a single event group
1524 * validation include:
1525 * - check events are compatible which each other
1526 * - events do not compete for the same counter
1527 * - number of events <= number of counters
1529 * validation ensures the group can be loaded onto the
1530 * PMU if it was the only group available.
1532 static int validate_group(struct perf_event
*event
)
1534 struct perf_event
*leader
= event
->group_leader
;
1535 struct cpu_hw_events
*fake_cpuc
;
1539 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1544 * the event is not yet connected with its
1545 * siblings therefore we must first collect
1546 * existing siblings, then add the new event
1547 * before we can simulate the scheduling
1550 n
= collect_events(fake_cpuc
, leader
, true);
1554 fake_cpuc
->n_events
= n
;
1555 n
= collect_events(fake_cpuc
, event
, false);
1559 fake_cpuc
->n_events
= n
;
1561 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1569 int x86_pmu_event_init(struct perf_event
*event
)
1574 switch (event
->attr
.type
) {
1576 case PERF_TYPE_HARDWARE
:
1577 case PERF_TYPE_HW_CACHE
:
1584 err
= __x86_pmu_event_init(event
);
1587 * we temporarily connect event to its pmu
1588 * such that validate_group() can classify
1589 * it as an x86 event using is_x86_event()
1594 if (event
->group_leader
!= event
)
1595 err
= validate_group(event
);
1597 err
= validate_event(event
);
1603 event
->destroy(event
);
1609 static struct pmu pmu
= {
1610 .pmu_enable
= x86_pmu_enable
,
1611 .pmu_disable
= x86_pmu_disable
,
1613 .event_init
= x86_pmu_event_init
,
1617 .start
= x86_pmu_start
,
1618 .stop
= x86_pmu_stop
,
1619 .read
= x86_pmu_read
,
1621 .start_txn
= x86_pmu_start_txn
,
1622 .cancel_txn
= x86_pmu_cancel_txn
,
1623 .commit_txn
= x86_pmu_commit_txn
,
1631 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1633 /* Ignore warnings */
1636 static void backtrace_warning(void *data
, char *msg
)
1638 /* Ignore warnings */
1641 static int backtrace_stack(void *data
, char *name
)
1646 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1648 struct perf_callchain_entry
*entry
= data
;
1650 perf_callchain_store(entry
, addr
);
1653 static const struct stacktrace_ops backtrace_ops
= {
1654 .warning
= backtrace_warning
,
1655 .warning_symbol
= backtrace_warning_symbol
,
1656 .stack
= backtrace_stack
,
1657 .address
= backtrace_address
,
1658 .walk_stack
= print_context_stack_bp
,
1662 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1664 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1665 /* TODO: We don't support guest os callchain now */
1669 perf_callchain_store(entry
, regs
->ip
);
1671 dump_trace(NULL
, regs
, NULL
, regs
->bp
, &backtrace_ops
, entry
);
1674 #ifdef CONFIG_COMPAT
1676 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1678 /* 32-bit process in 64-bit kernel. */
1679 struct stack_frame_ia32 frame
;
1680 const void __user
*fp
;
1682 if (!test_thread_flag(TIF_IA32
))
1685 fp
= compat_ptr(regs
->bp
);
1686 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1687 unsigned long bytes
;
1688 frame
.next_frame
= 0;
1689 frame
.return_address
= 0;
1691 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1692 if (bytes
!= sizeof(frame
))
1695 if (fp
< compat_ptr(regs
->sp
))
1698 perf_callchain_store(entry
, frame
.return_address
);
1699 fp
= compat_ptr(frame
.next_frame
);
1705 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1712 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1714 struct stack_frame frame
;
1715 const void __user
*fp
;
1717 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1718 /* TODO: We don't support guest os callchain now */
1722 fp
= (void __user
*)regs
->bp
;
1724 perf_callchain_store(entry
, regs
->ip
);
1726 if (perf_callchain_user32(regs
, entry
))
1729 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1730 unsigned long bytes
;
1731 frame
.next_frame
= NULL
;
1732 frame
.return_address
= 0;
1734 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1735 if (bytes
!= sizeof(frame
))
1738 if ((unsigned long)fp
< regs
->sp
)
1741 perf_callchain_store(entry
, frame
.return_address
);
1742 fp
= frame
.next_frame
;
1746 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1750 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
1751 ip
= perf_guest_cbs
->get_guest_ip();
1753 ip
= instruction_pointer(regs
);
1758 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1762 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1763 if (perf_guest_cbs
->is_user_mode())
1764 misc
|= PERF_RECORD_MISC_GUEST_USER
;
1766 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
1768 if (user_mode(regs
))
1769 misc
|= PERF_RECORD_MISC_USER
;
1771 misc
|= PERF_RECORD_MISC_KERNEL
;
1774 if (regs
->flags
& PERF_EFLAGS_EXACT
)
1775 misc
|= PERF_RECORD_MISC_EXACT_IP
;