2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
19 * register -------------------------------
20 * | HT | no HT | HT | no HT |
21 *-----------------------------------------
22 * offcore | core | core | cpu | core |
23 * lbr_sel | core | core | cpu | core |
24 * ld_lat | cpu | core | cpu | core |
25 *-----------------------------------------
27 * Given that there is a small number of shared regs,
28 * we can pre-allocate their slot in the per-cpu
29 * per-core reg tables.
32 EXTRA_REG_NONE
= -1, /* not used */
34 EXTRA_REG_RSP_0
= 0, /* offcore_response_0 */
35 EXTRA_REG_RSP_1
= 1, /* offcore_response_1 */
36 EXTRA_REG_LBR
= 2, /* lbr_select */
38 EXTRA_REG_MAX
/* number of entries needed */
41 struct event_constraint
{
43 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
53 int nb_id
; /* NorthBridge id */
54 int refcnt
; /* reference count */
55 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
56 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
59 /* The maximal number of PEBS events: */
60 #define MAX_PEBS_EVENTS 4
63 * A debug store configuration.
65 * We only support architectures that use 64bit fields.
70 u64 bts_absolute_maximum
;
71 u64 bts_interrupt_threshold
;
74 u64 pebs_absolute_maximum
;
75 u64 pebs_interrupt_threshold
;
76 u64 pebs_event_reset
[MAX_PEBS_EVENTS
];
83 raw_spinlock_t lock
; /* per-core: protect structure */
84 u64 config
; /* extra MSR config */
85 u64 reg
; /* extra MSR number */
86 atomic_t ref
; /* reference count */
92 * Used to coordinate shared registers between HT threads or
93 * among events on a single PMU.
95 struct intel_shared_regs
{
96 struct er_account regs
[EXTRA_REG_MAX
];
97 int refcnt
; /* per-core: #HT threads */
98 unsigned core_id
; /* per-core: core id */
101 #define MAX_LBR_ENTRIES 16
103 struct cpu_hw_events
{
105 * Generic x86 PMC bits
107 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
108 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
109 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
115 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
116 u64 tags
[X86_PMC_IDX_MAX
];
117 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
119 unsigned int group_flag
;
122 * Intel DebugStore bits
124 struct debug_store
*ds
;
132 struct perf_branch_stack lbr_stack
;
133 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
134 struct er_account
*lbr_sel
;
138 * Intel host/guest exclude bits
140 u64 intel_ctrl_guest_mask
;
141 u64 intel_ctrl_host_mask
;
142 struct perf_guest_switch_msr guest_switch_msrs
[X86_PMC_IDX_MAX
];
145 * manage shared (per-core, per-cpu) registers
146 * used on Intel NHM/WSM/SNB
148 struct intel_shared_regs
*shared_regs
;
153 struct amd_nb
*amd_nb
;
154 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
155 u64 perf_ctr_virt_mask
;
157 void *kfree_on_online
;
160 #define __EVENT_CONSTRAINT(c, n, m, w, o) {\
161 { .idxmsk64 = (n) }, \
168 #define EVENT_CONSTRAINT(c, n, m) \
169 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0)
172 * The overlap flag marks event constraints with overlapping counter
173 * masks. This is the case if the counter mask of such an event is not
174 * a subset of any other counter mask of a constraint with an equal or
175 * higher weight, e.g.:
177 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
178 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
179 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
181 * The event scheduler may not select the correct counter in the first
182 * cycle because it needs to know which subsequent events will be
183 * scheduled. It may fail to schedule the events then. So we set the
184 * overlap flag for such constraints to give the scheduler a hint which
185 * events to select for counter rescheduling.
187 * Care must be taken as the rescheduling algorithm is O(n!) which
188 * will increase scheduling cycles for an over-commited system
189 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
190 * and its counter masks must be kept at a minimum.
192 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
193 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1)
196 * Constraint on the Event code.
198 #define INTEL_EVENT_CONSTRAINT(c, n) \
199 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
202 * Constraint on the Event code + UMask + fixed-mask
204 * filter mask to validate fixed counter events.
205 * the following filters disqualify for fixed counters:
209 * The other filters are supported by fixed counters.
210 * The any-thread option is supported starting with v3.
212 #define FIXED_EVENT_CONSTRAINT(c, n) \
213 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
216 * Constraint on the Event code + UMask
218 #define INTEL_UEVENT_CONSTRAINT(c, n) \
219 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
221 #define EVENT_CONSTRAINT_END \
222 EVENT_CONSTRAINT(0, 0, 0)
224 #define for_each_event_constraint(e, c) \
225 for ((e) = (c); (e)->weight; (e)++)
228 * Extra registers for specific events.
230 * Some events need large masks and require external MSRs.
231 * Those extra MSRs end up being shared for all events on
232 * a PMU and sometimes between PMU of sibling HT threads.
233 * In either case, the kernel needs to handle conflicting
234 * accesses to those extra, shared, regs. The data structure
235 * to manage those registers is stored in cpu_hw_event.
242 int idx
; /* per_xxx->regs[] reg index */
245 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
248 .config_mask = (m), \
249 .valid_mask = (vm), \
250 .idx = EXTRA_REG_##i \
253 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
254 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
256 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
258 union perf_capabilities
{
269 struct x86_pmu_quirk
{
270 struct x86_pmu_quirk
*next
;
275 * struct x86_pmu - generic x86 pmu
279 * Generic x86 PMC bits
283 int (*handle_irq
)(struct pt_regs
*);
284 void (*disable_all
)(void);
285 void (*enable_all
)(int added
);
286 void (*enable
)(struct perf_event
*);
287 void (*disable
)(struct perf_event
*);
288 int (*hw_config
)(struct perf_event
*event
);
289 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
292 u64 (*event_map
)(int);
295 int num_counters_fixed
;
299 unsigned long events_maskl
;
300 unsigned long events_mask
[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT
)];
305 struct event_constraint
*
306 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
307 struct perf_event
*event
);
309 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
310 struct perf_event
*event
);
311 struct event_constraint
*event_constraints
;
312 struct x86_pmu_quirk
*quirks
;
313 int perfctr_second_write
;
323 int (*cpu_prepare
)(int cpu
);
324 void (*cpu_starting
)(int cpu
);
325 void (*cpu_dying
)(int cpu
);
326 void (*cpu_dead
)(int cpu
);
329 * Intel Arch Perfmon v2+
332 union perf_capabilities intel_cap
;
335 * Intel DebugStore bits
338 int bts_active
, pebs_active
;
339 int pebs_record_size
;
340 void (*drain_pebs
)(struct pt_regs
*regs
);
341 struct event_constraint
*pebs_constraints
;
346 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
347 int lbr_nr
; /* hardware stack size */
348 u64 lbr_sel_mask
; /* LBR_SELECT valid bits */
349 const int *lbr_sel_map
; /* lbr_select mappings */
352 * Extra registers for events
354 struct extra_reg
*extra_regs
;
355 unsigned int er_flags
;
358 * Intel host/guest support (KVM)
360 struct perf_guest_switch_msr
*(*guest_get_msrs
)(int *nr
);
363 #define x86_add_quirk(func_) \
365 static struct x86_pmu_quirk __quirk __initdata = { \
368 __quirk.next = x86_pmu.quirks; \
369 x86_pmu.quirks = &__quirk; \
372 #define ERF_NO_HT_SHARING 1
373 #define ERF_HAS_RSP_1 2
375 extern struct x86_pmu x86_pmu __read_mostly
;
377 DECLARE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
);
379 int x86_perf_event_set_period(struct perf_event
*event
);
382 * Generalized hw caching related hw_event table, filled
383 * in on a per model basis. A value of 0 means
384 * 'not supported', -1 means 'hw_event makes no sense on
385 * this CPU', any other value means the raw hw_event
389 #define C(x) PERF_COUNT_HW_CACHE_##x
391 extern u64 __read_mostly hw_cache_event_ids
392 [PERF_COUNT_HW_CACHE_MAX
]
393 [PERF_COUNT_HW_CACHE_OP_MAX
]
394 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
395 extern u64 __read_mostly hw_cache_extra_regs
396 [PERF_COUNT_HW_CACHE_MAX
]
397 [PERF_COUNT_HW_CACHE_OP_MAX
]
398 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
400 u64
x86_perf_event_update(struct perf_event
*event
);
402 static inline int x86_pmu_addr_offset(int index
)
406 /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
407 alternative_io(ASM_NOP2
,
409 X86_FEATURE_PERFCTR_CORE
,
416 static inline unsigned int x86_pmu_config_addr(int index
)
418 return x86_pmu
.eventsel
+ x86_pmu_addr_offset(index
);
421 static inline unsigned int x86_pmu_event_addr(int index
)
423 return x86_pmu
.perfctr
+ x86_pmu_addr_offset(index
);
426 int x86_setup_perfctr(struct perf_event
*event
);
428 int x86_pmu_hw_config(struct perf_event
*event
);
430 void x86_pmu_disable_all(void);
432 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
435 u64 disable_mask
= __this_cpu_read(cpu_hw_events
.perf_ctr_virt_mask
);
437 if (hwc
->extra_reg
.reg
)
438 wrmsrl(hwc
->extra_reg
.reg
, hwc
->extra_reg
.config
);
439 wrmsrl(hwc
->config_base
, (hwc
->config
| enable_mask
) & ~disable_mask
);
442 void x86_pmu_enable_all(int added
);
444 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
446 void x86_pmu_stop(struct perf_event
*event
, int flags
);
448 static inline void x86_pmu_disable_event(struct perf_event
*event
)
450 struct hw_perf_event
*hwc
= &event
->hw
;
452 wrmsrl(hwc
->config_base
, hwc
->config
);
455 void x86_pmu_enable_event(struct perf_event
*event
);
457 int x86_pmu_handle_irq(struct pt_regs
*regs
);
459 extern struct event_constraint emptyconstraint
;
461 extern struct event_constraint unconstrained
;
463 static inline bool kernel_ip(unsigned long ip
)
466 return ip
> PAGE_OFFSET
;
472 #ifdef CONFIG_CPU_SUP_AMD
474 int amd_pmu_init(void);
476 #else /* CONFIG_CPU_SUP_AMD */
478 static inline int amd_pmu_init(void)
483 #endif /* CONFIG_CPU_SUP_AMD */
485 #ifdef CONFIG_CPU_SUP_INTEL
487 int intel_pmu_save_and_restart(struct perf_event
*event
);
489 struct event_constraint
*
490 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
);
492 struct intel_shared_regs
*allocate_shared_regs(int cpu
);
494 int intel_pmu_init(void);
496 void init_debug_store_on_cpu(int cpu
);
498 void fini_debug_store_on_cpu(int cpu
);
500 void release_ds_buffers(void);
502 void reserve_ds_buffers(void);
504 extern struct event_constraint bts_constraint
;
506 void intel_pmu_enable_bts(u64 config
);
508 void intel_pmu_disable_bts(void);
510 int intel_pmu_drain_bts_buffer(void);
512 extern struct event_constraint intel_core2_pebs_event_constraints
[];
514 extern struct event_constraint intel_atom_pebs_event_constraints
[];
516 extern struct event_constraint intel_nehalem_pebs_event_constraints
[];
518 extern struct event_constraint intel_westmere_pebs_event_constraints
[];
520 extern struct event_constraint intel_snb_pebs_event_constraints
[];
522 struct event_constraint
*intel_pebs_constraints(struct perf_event
*event
);
524 void intel_pmu_pebs_enable(struct perf_event
*event
);
526 void intel_pmu_pebs_disable(struct perf_event
*event
);
528 void intel_pmu_pebs_enable_all(void);
530 void intel_pmu_pebs_disable_all(void);
532 void intel_ds_init(void);
534 void intel_pmu_lbr_reset(void);
536 void intel_pmu_lbr_enable(struct perf_event
*event
);
538 void intel_pmu_lbr_disable(struct perf_event
*event
);
540 void intel_pmu_lbr_enable_all(void);
542 void intel_pmu_lbr_disable_all(void);
544 void intel_pmu_lbr_read(void);
546 void intel_pmu_lbr_init_core(void);
548 void intel_pmu_lbr_init_nhm(void);
550 void intel_pmu_lbr_init_atom(void);
552 void intel_pmu_lbr_init_snb(void);
554 int intel_pmu_setup_lbr_filter(struct perf_event
*event
);
556 int p4_pmu_init(void);
558 int p6_pmu_init(void);
560 #else /* CONFIG_CPU_SUP_INTEL */
562 static inline void reserve_ds_buffers(void)
566 static inline void release_ds_buffers(void)
570 static inline int intel_pmu_init(void)
575 static inline struct intel_shared_regs
*allocate_shared_regs(int cpu
)
580 #endif /* CONFIG_CPU_SUP_INTEL */