2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
19 #define wrmsrl(msr, val) \
21 unsigned int _msr = (msr); \
23 trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \
24 (unsigned long long)(_val)); \
25 native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \
31 * register -------------------------------
32 * | HT | no HT | HT | no HT |
33 *-----------------------------------------
34 * offcore | core | core | cpu | core |
35 * lbr_sel | core | core | cpu | core |
36 * ld_lat | cpu | core | cpu | core |
37 *-----------------------------------------
39 * Given that there is a small number of shared regs,
40 * we can pre-allocate their slot in the per-cpu
41 * per-core reg tables.
44 EXTRA_REG_NONE
= -1, /* not used */
46 EXTRA_REG_RSP_0
= 0, /* offcore_response_0 */
47 EXTRA_REG_RSP_1
= 1, /* offcore_response_1 */
48 EXTRA_REG_LBR
= 2, /* lbr_select */
49 EXTRA_REG_LDLAT
= 3, /* ld_lat_threshold */
51 EXTRA_REG_MAX
/* number of entries needed */
54 struct event_constraint
{
56 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
66 * struct hw_perf_event.flags flags
68 #define PERF_X86_EVENT_PEBS_LDLAT 0x1 /* ld+ldlat data address sampling */
69 #define PERF_X86_EVENT_PEBS_ST 0x2 /* st data address sampling */
70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x4 /* haswell style st data sampling */
71 #define PERF_X86_EVENT_COMMITTED 0x8 /* event passed commit_txn */
74 int nb_id
; /* NorthBridge id */
75 int refcnt
; /* reference count */
76 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
77 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
80 /* The maximal number of PEBS events: */
81 #define MAX_PEBS_EVENTS 8
84 * A debug store configuration.
86 * We only support architectures that use 64bit fields.
91 u64 bts_absolute_maximum
;
92 u64 bts_interrupt_threshold
;
95 u64 pebs_absolute_maximum
;
96 u64 pebs_interrupt_threshold
;
97 u64 pebs_event_reset
[MAX_PEBS_EVENTS
];
101 * Per register state.
104 raw_spinlock_t lock
; /* per-core: protect structure */
105 u64 config
; /* extra MSR config */
106 u64 reg
; /* extra MSR number */
107 atomic_t ref
; /* reference count */
113 * Used to coordinate shared registers between HT threads or
114 * among events on a single PMU.
116 struct intel_shared_regs
{
117 struct er_account regs
[EXTRA_REG_MAX
];
118 int refcnt
; /* per-core: #HT threads */
119 unsigned core_id
; /* per-core: core id */
122 #define MAX_LBR_ENTRIES 16
124 struct cpu_hw_events
{
126 * Generic x86 PMC bits
128 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
129 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
130 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
133 int n_events
; /* the # of events in the below arrays */
134 int n_added
; /* the # last events in the below arrays;
135 they've never been enabled yet */
136 int n_txn
; /* the # last events in the below arrays;
137 added in the current transaction */
138 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
139 u64 tags
[X86_PMC_IDX_MAX
];
140 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
142 unsigned int group_flag
;
146 * Intel DebugStore bits
148 struct debug_store
*ds
;
156 struct perf_branch_stack lbr_stack
;
157 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
158 struct er_account
*lbr_sel
;
162 * Intel host/guest exclude bits
164 u64 intel_ctrl_guest_mask
;
165 u64 intel_ctrl_host_mask
;
166 struct perf_guest_switch_msr guest_switch_msrs
[X86_PMC_IDX_MAX
];
169 * Intel checkpoint mask
174 * manage shared (per-core, per-cpu) registers
175 * used on Intel NHM/WSM/SNB
177 struct intel_shared_regs
*shared_regs
;
182 struct amd_nb
*amd_nb
;
183 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
184 u64 perf_ctr_virt_mask
;
186 void *kfree_on_online
;
189 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
190 { .idxmsk64 = (n) }, \
198 #define EVENT_CONSTRAINT(c, n, m) \
199 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
202 * The overlap flag marks event constraints with overlapping counter
203 * masks. This is the case if the counter mask of such an event is not
204 * a subset of any other counter mask of a constraint with an equal or
205 * higher weight, e.g.:
207 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
208 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
209 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
211 * The event scheduler may not select the correct counter in the first
212 * cycle because it needs to know which subsequent events will be
213 * scheduled. It may fail to schedule the events then. So we set the
214 * overlap flag for such constraints to give the scheduler a hint which
215 * events to select for counter rescheduling.
217 * Care must be taken as the rescheduling algorithm is O(n!) which
218 * will increase scheduling cycles for an over-commited system
219 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
220 * and its counter masks must be kept at a minimum.
222 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
223 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
226 * Constraint on the Event code.
228 #define INTEL_EVENT_CONSTRAINT(c, n) \
229 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
232 * Constraint on the Event code + UMask + fixed-mask
234 * filter mask to validate fixed counter events.
235 * the following filters disqualify for fixed counters:
240 * - in_tx_checkpointed
241 * The other filters are supported by fixed counters.
242 * The any-thread option is supported starting with v3.
244 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
245 #define FIXED_EVENT_CONSTRAINT(c, n) \
246 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
249 * Constraint on the Event code + UMask
251 #define INTEL_UEVENT_CONSTRAINT(c, n) \
252 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
254 #define INTEL_PLD_CONSTRAINT(c, n) \
255 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
256 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
258 #define INTEL_PST_CONSTRAINT(c, n) \
259 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
260 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
262 /* DataLA version of store sampling without extra enable bit. */
263 #define INTEL_PST_HSW_CONSTRAINT(c, n) \
264 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
265 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
268 * We define the end marker as having a weight of -1
269 * to enable blacklisting of events using a counter bitmask
270 * of zero and thus a weight of zero.
271 * The end marker has a weight that cannot possibly be
272 * obtained from counting the bits in the bitmask.
274 #define EVENT_CONSTRAINT_END { .weight = -1 }
277 * Check for end marker with weight == -1
279 #define for_each_event_constraint(e, c) \
280 for ((e) = (c); (e)->weight != -1; (e)++)
283 * Extra registers for specific events.
285 * Some events need large masks and require external MSRs.
286 * Those extra MSRs end up being shared for all events on
287 * a PMU and sometimes between PMU of sibling HT threads.
288 * In either case, the kernel needs to handle conflicting
289 * accesses to those extra, shared, regs. The data structure
290 * to manage those registers is stored in cpu_hw_event.
297 int idx
; /* per_xxx->regs[] reg index */
300 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
303 .config_mask = (m), \
304 .valid_mask = (vm), \
305 .idx = EXTRA_REG_##i, \
308 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
309 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
311 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
312 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
313 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
315 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
316 INTEL_UEVENT_EXTRA_REG(c, \
317 MSR_PEBS_LD_LAT_THRESHOLD, \
321 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
323 union perf_capabilities
{
331 * PMU supports separate counter range for writing
334 u64 full_width_write
:1;
339 struct x86_pmu_quirk
{
340 struct x86_pmu_quirk
*next
;
344 union x86_pmu_config
{
365 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
368 * struct x86_pmu - generic x86 pmu
372 * Generic x86 PMC bits
376 int (*handle_irq
)(struct pt_regs
*);
377 void (*disable_all
)(void);
378 void (*enable_all
)(int added
);
379 void (*enable
)(struct perf_event
*);
380 void (*disable
)(struct perf_event
*);
381 int (*hw_config
)(struct perf_event
*event
);
382 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
385 int (*addr_offset
)(int index
, bool eventsel
);
386 int (*rdpmc_index
)(int index
);
387 u64 (*event_map
)(int);
390 int num_counters_fixed
;
394 unsigned long events_maskl
;
395 unsigned long events_mask
[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT
)];
400 struct event_constraint
*
401 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
402 struct perf_event
*event
);
404 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
405 struct perf_event
*event
);
406 struct event_constraint
*event_constraints
;
407 struct x86_pmu_quirk
*quirks
;
408 int perfctr_second_write
;
414 int attr_rdpmc_broken
;
416 struct attribute
**format_attrs
;
417 struct attribute
**event_attrs
;
419 ssize_t (*events_sysfs_show
)(char *page
, u64 config
);
420 struct attribute
**cpu_events
;
425 int (*cpu_prepare
)(int cpu
);
426 void (*cpu_starting
)(int cpu
);
427 void (*cpu_dying
)(int cpu
);
428 void (*cpu_dead
)(int cpu
);
430 void (*check_microcode
)(void);
431 void (*flush_branch_stack
)(void);
434 * Intel Arch Perfmon v2+
437 union perf_capabilities intel_cap
;
440 * Intel DebugStore bits
447 int pebs_record_size
;
448 void (*drain_pebs
)(struct pt_regs
*regs
);
449 struct event_constraint
*pebs_constraints
;
450 void (*pebs_aliases
)(struct perf_event
*event
);
456 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
457 int lbr_nr
; /* hardware stack size */
458 u64 lbr_sel_mask
; /* LBR_SELECT valid bits */
459 const int *lbr_sel_map
; /* lbr_select mappings */
460 bool lbr_double_abort
; /* duplicated lbr aborts */
463 * Extra registers for events
465 struct extra_reg
*extra_regs
;
466 unsigned int er_flags
;
469 * Intel host/guest support (KVM)
471 struct perf_guest_switch_msr
*(*guest_get_msrs
)(int *nr
);
474 #define x86_add_quirk(func_) \
476 static struct x86_pmu_quirk __quirk __initdata = { \
479 __quirk.next = x86_pmu.quirks; \
480 x86_pmu.quirks = &__quirk; \
483 #define ERF_NO_HT_SHARING 1
484 #define ERF_HAS_RSP_1 2
486 #define EVENT_VAR(_id) event_attr_##_id
487 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
489 #define EVENT_ATTR(_name, _id) \
490 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
491 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
492 .id = PERF_COUNT_HW_##_id, \
496 #define EVENT_ATTR_STR(_name, v, str) \
497 static struct perf_pmu_events_attr event_attr_##v = { \
498 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
503 extern struct x86_pmu x86_pmu __read_mostly
;
505 DECLARE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
);
507 int x86_perf_event_set_period(struct perf_event
*event
);
510 * Generalized hw caching related hw_event table, filled
511 * in on a per model basis. A value of 0 means
512 * 'not supported', -1 means 'hw_event makes no sense on
513 * this CPU', any other value means the raw hw_event
517 #define C(x) PERF_COUNT_HW_CACHE_##x
519 extern u64 __read_mostly hw_cache_event_ids
520 [PERF_COUNT_HW_CACHE_MAX
]
521 [PERF_COUNT_HW_CACHE_OP_MAX
]
522 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
523 extern u64 __read_mostly hw_cache_extra_regs
524 [PERF_COUNT_HW_CACHE_MAX
]
525 [PERF_COUNT_HW_CACHE_OP_MAX
]
526 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
528 u64
x86_perf_event_update(struct perf_event
*event
);
530 static inline unsigned int x86_pmu_config_addr(int index
)
532 return x86_pmu
.eventsel
+ (x86_pmu
.addr_offset
?
533 x86_pmu
.addr_offset(index
, true) : index
);
536 static inline unsigned int x86_pmu_event_addr(int index
)
538 return x86_pmu
.perfctr
+ (x86_pmu
.addr_offset
?
539 x86_pmu
.addr_offset(index
, false) : index
);
542 static inline int x86_pmu_rdpmc_index(int index
)
544 return x86_pmu
.rdpmc_index
? x86_pmu
.rdpmc_index(index
) : index
;
547 int x86_setup_perfctr(struct perf_event
*event
);
549 int x86_pmu_hw_config(struct perf_event
*event
);
551 void x86_pmu_disable_all(void);
553 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
556 u64 disable_mask
= __this_cpu_read(cpu_hw_events
.perf_ctr_virt_mask
);
558 if (hwc
->extra_reg
.reg
)
559 wrmsrl(hwc
->extra_reg
.reg
, hwc
->extra_reg
.config
);
560 wrmsrl(hwc
->config_base
, (hwc
->config
| enable_mask
) & ~disable_mask
);
563 void x86_pmu_enable_all(int added
);
565 int perf_assign_events(struct perf_event
**events
, int n
,
566 int wmin
, int wmax
, int *assign
);
567 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
569 void x86_pmu_stop(struct perf_event
*event
, int flags
);
571 static inline void x86_pmu_disable_event(struct perf_event
*event
)
573 struct hw_perf_event
*hwc
= &event
->hw
;
575 wrmsrl(hwc
->config_base
, hwc
->config
);
578 void x86_pmu_enable_event(struct perf_event
*event
);
580 int x86_pmu_handle_irq(struct pt_regs
*regs
);
582 extern struct event_constraint emptyconstraint
;
584 extern struct event_constraint unconstrained
;
586 static inline bool kernel_ip(unsigned long ip
)
589 return ip
> PAGE_OFFSET
;
596 * Not all PMUs provide the right context information to place the reported IP
597 * into full context. Specifically segment registers are typically not
600 * Assuming the address is a linear address (it is for IBS), we fake the CS and
601 * vm86 mode using the known zero-based code segment and 'fix up' the registers
604 * Intel PEBS/LBR appear to typically provide the effective address, nothing
605 * much we can do about that but pray and treat it like a linear address.
607 static inline void set_linear_ip(struct pt_regs
*regs
, unsigned long ip
)
609 regs
->cs
= kernel_ip(ip
) ? __KERNEL_CS
: __USER_CS
;
610 if (regs
->flags
& X86_VM_MASK
)
611 regs
->flags
^= (PERF_EFLAGS_VM
| X86_VM_MASK
);
615 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
);
616 ssize_t
intel_event_sysfs_show(char *page
, u64 config
);
618 #ifdef CONFIG_CPU_SUP_AMD
620 int amd_pmu_init(void);
622 #else /* CONFIG_CPU_SUP_AMD */
624 static inline int amd_pmu_init(void)
629 #endif /* CONFIG_CPU_SUP_AMD */
631 #ifdef CONFIG_CPU_SUP_INTEL
633 int intel_pmu_save_and_restart(struct perf_event
*event
);
635 struct event_constraint
*
636 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
);
638 struct intel_shared_regs
*allocate_shared_regs(int cpu
);
640 int intel_pmu_init(void);
642 void init_debug_store_on_cpu(int cpu
);
644 void fini_debug_store_on_cpu(int cpu
);
646 void release_ds_buffers(void);
648 void reserve_ds_buffers(void);
650 extern struct event_constraint bts_constraint
;
652 void intel_pmu_enable_bts(u64 config
);
654 void intel_pmu_disable_bts(void);
656 int intel_pmu_drain_bts_buffer(void);
658 extern struct event_constraint intel_core2_pebs_event_constraints
[];
660 extern struct event_constraint intel_atom_pebs_event_constraints
[];
662 extern struct event_constraint intel_slm_pebs_event_constraints
[];
664 extern struct event_constraint intel_nehalem_pebs_event_constraints
[];
666 extern struct event_constraint intel_westmere_pebs_event_constraints
[];
668 extern struct event_constraint intel_snb_pebs_event_constraints
[];
670 extern struct event_constraint intel_ivb_pebs_event_constraints
[];
672 extern struct event_constraint intel_hsw_pebs_event_constraints
[];
674 struct event_constraint
*intel_pebs_constraints(struct perf_event
*event
);
676 void intel_pmu_pebs_enable(struct perf_event
*event
);
678 void intel_pmu_pebs_disable(struct perf_event
*event
);
680 void intel_pmu_pebs_enable_all(void);
682 void intel_pmu_pebs_disable_all(void);
684 void intel_ds_init(void);
686 void intel_pmu_lbr_reset(void);
688 void intel_pmu_lbr_enable(struct perf_event
*event
);
690 void intel_pmu_lbr_disable(struct perf_event
*event
);
692 void intel_pmu_lbr_enable_all(void);
694 void intel_pmu_lbr_disable_all(void);
696 void intel_pmu_lbr_read(void);
698 void intel_pmu_lbr_init_core(void);
700 void intel_pmu_lbr_init_nhm(void);
702 void intel_pmu_lbr_init_atom(void);
704 void intel_pmu_lbr_init_snb(void);
706 int intel_pmu_setup_lbr_filter(struct perf_event
*event
);
708 int p4_pmu_init(void);
710 int p6_pmu_init(void);
712 int knc_pmu_init(void);
714 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
717 #else /* CONFIG_CPU_SUP_INTEL */
719 static inline void reserve_ds_buffers(void)
723 static inline void release_ds_buffers(void)
727 static inline int intel_pmu_init(void)
732 static inline struct intel_shared_regs
*allocate_shared_regs(int cpu
)
737 #endif /* CONFIG_CPU_SUP_INTEL */