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perf/intel/x86: Enlarge the PEBS buffer
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / perf_event_intel_ds.c
1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
4
5 #include <asm/perf_event.h>
6 #include <asm/insn.h>
7
8 #include "perf_event.h"
9
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
12
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
16
17 /*
18 * pebs_record_32 for p4 and core not supported
19
20 struct pebs_record_32 {
21 u32 flags, ip;
22 u32 ax, bc, cx, dx;
23 u32 si, di, bp, sp;
24 };
25
26 */
27
28 union intel_x86_pebs_dse {
29 u64 val;
30 struct {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
35 };
36 struct {
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
42 };
43 };
44
45
46 /*
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
49 */
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
53
54 static const u64 pebs_data_source[] = {
55 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
56 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
57 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
58 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
59 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
61 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
62 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
63 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
65 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
66 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
67 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
68 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
69 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
70 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
71 };
72
73 static u64 precise_store_data(u64 status)
74 {
75 union intel_x86_pebs_dse dse;
76 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
77
78 dse.val = status;
79
80 /*
81 * bit 4: TLB access
82 * 1 = stored missed 2nd level TLB
83 *
84 * so it either hit the walker or the OS
85 * otherwise hit 2nd level TLB
86 */
87 if (dse.st_stlb_miss)
88 val |= P(TLB, MISS);
89 else
90 val |= P(TLB, HIT);
91
92 /*
93 * bit 0: hit L1 data cache
94 * if not set, then all we know is that
95 * it missed L1D
96 */
97 if (dse.st_l1d_hit)
98 val |= P(LVL, HIT);
99 else
100 val |= P(LVL, MISS);
101
102 /*
103 * bit 5: Locked prefix
104 */
105 if (dse.st_locked)
106 val |= P(LOCK, LOCKED);
107
108 return val;
109 }
110
111 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
112 {
113 union perf_mem_data_src dse;
114
115 dse.val = PERF_MEM_NA;
116
117 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
118 dse.mem_op = PERF_MEM_OP_STORE;
119 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
120 dse.mem_op = PERF_MEM_OP_LOAD;
121
122 /*
123 * L1 info only valid for following events:
124 *
125 * MEM_UOPS_RETIRED.STLB_MISS_STORES
126 * MEM_UOPS_RETIRED.LOCK_STORES
127 * MEM_UOPS_RETIRED.SPLIT_STORES
128 * MEM_UOPS_RETIRED.ALL_STORES
129 */
130 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
131 if (status & 1)
132 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
133 else
134 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
135 }
136 return dse.val;
137 }
138
139 static u64 load_latency_data(u64 status)
140 {
141 union intel_x86_pebs_dse dse;
142 u64 val;
143 int model = boot_cpu_data.x86_model;
144 int fam = boot_cpu_data.x86;
145
146 dse.val = status;
147
148 /*
149 * use the mapping table for bit 0-3
150 */
151 val = pebs_data_source[dse.ld_dse];
152
153 /*
154 * Nehalem models do not support TLB, Lock infos
155 */
156 if (fam == 0x6 && (model == 26 || model == 30
157 || model == 31 || model == 46)) {
158 val |= P(TLB, NA) | P(LOCK, NA);
159 return val;
160 }
161 /*
162 * bit 4: TLB access
163 * 0 = did not miss 2nd level TLB
164 * 1 = missed 2nd level TLB
165 */
166 if (dse.ld_stlb_miss)
167 val |= P(TLB, MISS) | P(TLB, L2);
168 else
169 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
170
171 /*
172 * bit 5: locked prefix
173 */
174 if (dse.ld_locked)
175 val |= P(LOCK, LOCKED);
176
177 return val;
178 }
179
180 struct pebs_record_core {
181 u64 flags, ip;
182 u64 ax, bx, cx, dx;
183 u64 si, di, bp, sp;
184 u64 r8, r9, r10, r11;
185 u64 r12, r13, r14, r15;
186 };
187
188 struct pebs_record_nhm {
189 u64 flags, ip;
190 u64 ax, bx, cx, dx;
191 u64 si, di, bp, sp;
192 u64 r8, r9, r10, r11;
193 u64 r12, r13, r14, r15;
194 u64 status, dla, dse, lat;
195 };
196
197 /*
198 * Same as pebs_record_nhm, with two additional fields.
199 */
200 struct pebs_record_hsw {
201 u64 flags, ip;
202 u64 ax, bx, cx, dx;
203 u64 si, di, bp, sp;
204 u64 r8, r9, r10, r11;
205 u64 r12, r13, r14, r15;
206 u64 status, dla, dse, lat;
207 u64 real_ip, tsx_tuning;
208 };
209
210 union hsw_tsx_tuning {
211 struct {
212 u32 cycles_last_block : 32,
213 hle_abort : 1,
214 rtm_abort : 1,
215 instruction_abort : 1,
216 non_instruction_abort : 1,
217 retry : 1,
218 data_conflict : 1,
219 capacity_writes : 1,
220 capacity_reads : 1;
221 };
222 u64 value;
223 };
224
225 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
226
227 void init_debug_store_on_cpu(int cpu)
228 {
229 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
230
231 if (!ds)
232 return;
233
234 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
235 (u32)((u64)(unsigned long)ds),
236 (u32)((u64)(unsigned long)ds >> 32));
237 }
238
239 void fini_debug_store_on_cpu(int cpu)
240 {
241 if (!per_cpu(cpu_hw_events, cpu).ds)
242 return;
243
244 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
245 }
246
247 static DEFINE_PER_CPU(void *, insn_buffer);
248
249 static int alloc_pebs_buffer(int cpu)
250 {
251 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
252 int node = cpu_to_node(cpu);
253 int max;
254 void *buffer, *ibuffer;
255
256 if (!x86_pmu.pebs)
257 return 0;
258
259 buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
260 if (unlikely(!buffer))
261 return -ENOMEM;
262
263 /*
264 * HSW+ already provides us the eventing ip; no need to allocate this
265 * buffer then.
266 */
267 if (x86_pmu.intel_cap.pebs_format < 2) {
268 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
269 if (!ibuffer) {
270 kfree(buffer);
271 return -ENOMEM;
272 }
273 per_cpu(insn_buffer, cpu) = ibuffer;
274 }
275
276 max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
277
278 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
279 ds->pebs_index = ds->pebs_buffer_base;
280 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
281 max * x86_pmu.pebs_record_size;
282
283 return 0;
284 }
285
286 static void release_pebs_buffer(int cpu)
287 {
288 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
289
290 if (!ds || !x86_pmu.pebs)
291 return;
292
293 kfree(per_cpu(insn_buffer, cpu));
294 per_cpu(insn_buffer, cpu) = NULL;
295
296 kfree((void *)(unsigned long)ds->pebs_buffer_base);
297 ds->pebs_buffer_base = 0;
298 }
299
300 static int alloc_bts_buffer(int cpu)
301 {
302 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
303 int node = cpu_to_node(cpu);
304 int max, thresh;
305 void *buffer;
306
307 if (!x86_pmu.bts)
308 return 0;
309
310 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
311 if (unlikely(!buffer)) {
312 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
313 return -ENOMEM;
314 }
315
316 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
317 thresh = max / 16;
318
319 ds->bts_buffer_base = (u64)(unsigned long)buffer;
320 ds->bts_index = ds->bts_buffer_base;
321 ds->bts_absolute_maximum = ds->bts_buffer_base +
322 max * BTS_RECORD_SIZE;
323 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
324 thresh * BTS_RECORD_SIZE;
325
326 return 0;
327 }
328
329 static void release_bts_buffer(int cpu)
330 {
331 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
332
333 if (!ds || !x86_pmu.bts)
334 return;
335
336 kfree((void *)(unsigned long)ds->bts_buffer_base);
337 ds->bts_buffer_base = 0;
338 }
339
340 static int alloc_ds_buffer(int cpu)
341 {
342 int node = cpu_to_node(cpu);
343 struct debug_store *ds;
344
345 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
346 if (unlikely(!ds))
347 return -ENOMEM;
348
349 per_cpu(cpu_hw_events, cpu).ds = ds;
350
351 return 0;
352 }
353
354 static void release_ds_buffer(int cpu)
355 {
356 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
357
358 if (!ds)
359 return;
360
361 per_cpu(cpu_hw_events, cpu).ds = NULL;
362 kfree(ds);
363 }
364
365 void release_ds_buffers(void)
366 {
367 int cpu;
368
369 if (!x86_pmu.bts && !x86_pmu.pebs)
370 return;
371
372 get_online_cpus();
373 for_each_online_cpu(cpu)
374 fini_debug_store_on_cpu(cpu);
375
376 for_each_possible_cpu(cpu) {
377 release_pebs_buffer(cpu);
378 release_bts_buffer(cpu);
379 release_ds_buffer(cpu);
380 }
381 put_online_cpus();
382 }
383
384 void reserve_ds_buffers(void)
385 {
386 int bts_err = 0, pebs_err = 0;
387 int cpu;
388
389 x86_pmu.bts_active = 0;
390 x86_pmu.pebs_active = 0;
391
392 if (!x86_pmu.bts && !x86_pmu.pebs)
393 return;
394
395 if (!x86_pmu.bts)
396 bts_err = 1;
397
398 if (!x86_pmu.pebs)
399 pebs_err = 1;
400
401 get_online_cpus();
402
403 for_each_possible_cpu(cpu) {
404 if (alloc_ds_buffer(cpu)) {
405 bts_err = 1;
406 pebs_err = 1;
407 }
408
409 if (!bts_err && alloc_bts_buffer(cpu))
410 bts_err = 1;
411
412 if (!pebs_err && alloc_pebs_buffer(cpu))
413 pebs_err = 1;
414
415 if (bts_err && pebs_err)
416 break;
417 }
418
419 if (bts_err) {
420 for_each_possible_cpu(cpu)
421 release_bts_buffer(cpu);
422 }
423
424 if (pebs_err) {
425 for_each_possible_cpu(cpu)
426 release_pebs_buffer(cpu);
427 }
428
429 if (bts_err && pebs_err) {
430 for_each_possible_cpu(cpu)
431 release_ds_buffer(cpu);
432 } else {
433 if (x86_pmu.bts && !bts_err)
434 x86_pmu.bts_active = 1;
435
436 if (x86_pmu.pebs && !pebs_err)
437 x86_pmu.pebs_active = 1;
438
439 for_each_online_cpu(cpu)
440 init_debug_store_on_cpu(cpu);
441 }
442
443 put_online_cpus();
444 }
445
446 /*
447 * BTS
448 */
449
450 struct event_constraint bts_constraint =
451 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
452
453 void intel_pmu_enable_bts(u64 config)
454 {
455 unsigned long debugctlmsr;
456
457 debugctlmsr = get_debugctlmsr();
458
459 debugctlmsr |= DEBUGCTLMSR_TR;
460 debugctlmsr |= DEBUGCTLMSR_BTS;
461 if (config & ARCH_PERFMON_EVENTSEL_INT)
462 debugctlmsr |= DEBUGCTLMSR_BTINT;
463
464 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
465 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
466
467 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
468 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
469
470 update_debugctlmsr(debugctlmsr);
471 }
472
473 void intel_pmu_disable_bts(void)
474 {
475 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
476 unsigned long debugctlmsr;
477
478 if (!cpuc->ds)
479 return;
480
481 debugctlmsr = get_debugctlmsr();
482
483 debugctlmsr &=
484 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
485 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
486
487 update_debugctlmsr(debugctlmsr);
488 }
489
490 int intel_pmu_drain_bts_buffer(void)
491 {
492 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
493 struct debug_store *ds = cpuc->ds;
494 struct bts_record {
495 u64 from;
496 u64 to;
497 u64 flags;
498 };
499 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
500 struct bts_record *at, *top;
501 struct perf_output_handle handle;
502 struct perf_event_header header;
503 struct perf_sample_data data;
504 struct pt_regs regs;
505
506 if (!event)
507 return 0;
508
509 if (!x86_pmu.bts_active)
510 return 0;
511
512 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
513 top = (struct bts_record *)(unsigned long)ds->bts_index;
514
515 if (top <= at)
516 return 0;
517
518 memset(&regs, 0, sizeof(regs));
519
520 ds->bts_index = ds->bts_buffer_base;
521
522 perf_sample_data_init(&data, 0, event->hw.last_period);
523
524 /*
525 * Prepare a generic sample, i.e. fill in the invariant fields.
526 * We will overwrite the from and to address before we output
527 * the sample.
528 */
529 perf_prepare_sample(&header, &data, event, &regs);
530
531 if (perf_output_begin(&handle, event, header.size * (top - at)))
532 return 1;
533
534 for (; at < top; at++) {
535 data.ip = at->from;
536 data.addr = at->to;
537
538 perf_output_sample(&handle, &header, &data, event);
539 }
540
541 perf_output_end(&handle);
542
543 /* There's new data available. */
544 event->hw.interrupts++;
545 event->pending_kill = POLL_IN;
546 return 1;
547 }
548
549 static inline void intel_pmu_drain_pebs_buffer(void)
550 {
551 struct pt_regs regs;
552
553 x86_pmu.drain_pebs(&regs);
554 }
555
556 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
557 {
558 if (!sched_in)
559 intel_pmu_drain_pebs_buffer();
560 }
561
562 /*
563 * PEBS
564 */
565 struct event_constraint intel_core2_pebs_event_constraints[] = {
566 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
567 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
568 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
569 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
570 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
571 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
572 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
573 EVENT_CONSTRAINT_END
574 };
575
576 struct event_constraint intel_atom_pebs_event_constraints[] = {
577 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
578 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
579 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
580 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
581 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
582 EVENT_CONSTRAINT_END
583 };
584
585 struct event_constraint intel_slm_pebs_event_constraints[] = {
586 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
587 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
588 /* Allow all events as PEBS with no flags */
589 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
590 EVENT_CONSTRAINT_END
591 };
592
593 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
594 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
595 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
596 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
597 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
598 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
599 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
600 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
601 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
602 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
603 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
604 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
605 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
606 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
607 EVENT_CONSTRAINT_END
608 };
609
610 struct event_constraint intel_westmere_pebs_event_constraints[] = {
611 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
612 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
613 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
614 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
615 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
616 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
617 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
618 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
619 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
620 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
621 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
622 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
623 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
624 EVENT_CONSTRAINT_END
625 };
626
627 struct event_constraint intel_snb_pebs_event_constraints[] = {
628 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
629 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
630 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
631 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
632 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
633 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
634 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
635 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
636 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
637 /* Allow all events as PEBS with no flags */
638 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
639 EVENT_CONSTRAINT_END
640 };
641
642 struct event_constraint intel_ivb_pebs_event_constraints[] = {
643 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
644 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
645 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
646 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
647 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
648 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
649 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
650 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
651 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
652 /* Allow all events as PEBS with no flags */
653 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
654 EVENT_CONSTRAINT_END
655 };
656
657 struct event_constraint intel_hsw_pebs_event_constraints[] = {
658 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
659 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
660 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
661 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
662 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
663 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
664 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
665 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
666 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
667 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
668 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
669 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
670 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
671 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
672 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
673 /* Allow all events as PEBS with no flags */
674 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
675 EVENT_CONSTRAINT_END
676 };
677
678 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
679 {
680 struct event_constraint *c;
681
682 if (!event->attr.precise_ip)
683 return NULL;
684
685 if (x86_pmu.pebs_constraints) {
686 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
687 if ((event->hw.config & c->cmask) == c->code) {
688 event->hw.flags |= c->flags;
689 return c;
690 }
691 }
692 }
693
694 return &emptyconstraint;
695 }
696
697 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
698 {
699 return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
700 }
701
702 void intel_pmu_pebs_enable(struct perf_event *event)
703 {
704 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
705 struct hw_perf_event *hwc = &event->hw;
706 struct debug_store *ds = cpuc->ds;
707 bool first_pebs;
708 u64 threshold;
709
710 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
711
712 first_pebs = !pebs_is_enabled(cpuc);
713 cpuc->pebs_enabled |= 1ULL << hwc->idx;
714
715 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
716 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
717 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
718 cpuc->pebs_enabled |= 1ULL << 63;
719
720 /*
721 * When the event is constrained enough we can use a larger
722 * threshold and run the event with less frequent PMI.
723 */
724 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
725 threshold = ds->pebs_absolute_maximum -
726 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
727
728 if (first_pebs)
729 perf_sched_cb_inc(event->ctx->pmu);
730 } else {
731 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
732
733 /*
734 * If not all events can use larger buffer,
735 * roll back to threshold = 1
736 */
737 if (!first_pebs &&
738 (ds->pebs_interrupt_threshold > threshold))
739 perf_sched_cb_dec(event->ctx->pmu);
740 }
741
742 /* Use auto-reload if possible to save a MSR write in the PMI */
743 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
744 ds->pebs_event_reset[hwc->idx] =
745 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
746 }
747
748 if (first_pebs || ds->pebs_interrupt_threshold > threshold)
749 ds->pebs_interrupt_threshold = threshold;
750 }
751
752 void intel_pmu_pebs_disable(struct perf_event *event)
753 {
754 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
755 struct hw_perf_event *hwc = &event->hw;
756 struct debug_store *ds = cpuc->ds;
757
758 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
759
760 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
761 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
762 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
763 cpuc->pebs_enabled &= ~(1ULL << 63);
764
765 if (ds->pebs_interrupt_threshold >
766 ds->pebs_buffer_base + x86_pmu.pebs_record_size) {
767 intel_pmu_drain_pebs_buffer();
768 if (!pebs_is_enabled(cpuc))
769 perf_sched_cb_dec(event->ctx->pmu);
770 }
771
772 if (cpuc->enabled)
773 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
774
775 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
776 }
777
778 void intel_pmu_pebs_enable_all(void)
779 {
780 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
781
782 if (cpuc->pebs_enabled)
783 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
784 }
785
786 void intel_pmu_pebs_disable_all(void)
787 {
788 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
789
790 if (cpuc->pebs_enabled)
791 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
792 }
793
794 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
795 {
796 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
797 unsigned long from = cpuc->lbr_entries[0].from;
798 unsigned long old_to, to = cpuc->lbr_entries[0].to;
799 unsigned long ip = regs->ip;
800 int is_64bit = 0;
801 void *kaddr;
802 int size;
803
804 /*
805 * We don't need to fixup if the PEBS assist is fault like
806 */
807 if (!x86_pmu.intel_cap.pebs_trap)
808 return 1;
809
810 /*
811 * No LBR entry, no basic block, no rewinding
812 */
813 if (!cpuc->lbr_stack.nr || !from || !to)
814 return 0;
815
816 /*
817 * Basic blocks should never cross user/kernel boundaries
818 */
819 if (kernel_ip(ip) != kernel_ip(to))
820 return 0;
821
822 /*
823 * unsigned math, either ip is before the start (impossible) or
824 * the basic block is larger than 1 page (sanity)
825 */
826 if ((ip - to) > PEBS_FIXUP_SIZE)
827 return 0;
828
829 /*
830 * We sampled a branch insn, rewind using the LBR stack
831 */
832 if (ip == to) {
833 set_linear_ip(regs, from);
834 return 1;
835 }
836
837 size = ip - to;
838 if (!kernel_ip(ip)) {
839 int bytes;
840 u8 *buf = this_cpu_read(insn_buffer);
841
842 /* 'size' must fit our buffer, see above */
843 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
844 if (bytes != 0)
845 return 0;
846
847 kaddr = buf;
848 } else {
849 kaddr = (void *)to;
850 }
851
852 do {
853 struct insn insn;
854
855 old_to = to;
856
857 #ifdef CONFIG_X86_64
858 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
859 #endif
860 insn_init(&insn, kaddr, size, is_64bit);
861 insn_get_length(&insn);
862 /*
863 * Make sure there was not a problem decoding the
864 * instruction and getting the length. This is
865 * doubly important because we have an infinite
866 * loop if insn.length=0.
867 */
868 if (!insn.length)
869 break;
870
871 to += insn.length;
872 kaddr += insn.length;
873 size -= insn.length;
874 } while (to < ip);
875
876 if (to == ip) {
877 set_linear_ip(regs, old_to);
878 return 1;
879 }
880
881 /*
882 * Even though we decoded the basic block, the instruction stream
883 * never matched the given IP, either the TO or the IP got corrupted.
884 */
885 return 0;
886 }
887
888 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
889 {
890 if (pebs->tsx_tuning) {
891 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
892 return tsx.cycles_last_block;
893 }
894 return 0;
895 }
896
897 static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
898 {
899 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
900
901 /* For RTM XABORTs also log the abort code from AX */
902 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
903 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
904 return txn;
905 }
906
907 static void setup_pebs_sample_data(struct perf_event *event,
908 struct pt_regs *iregs, void *__pebs,
909 struct perf_sample_data *data,
910 struct pt_regs *regs)
911 {
912 #define PERF_X86_EVENT_PEBS_HSW_PREC \
913 (PERF_X86_EVENT_PEBS_ST_HSW | \
914 PERF_X86_EVENT_PEBS_LD_HSW | \
915 PERF_X86_EVENT_PEBS_NA_HSW)
916 /*
917 * We cast to the biggest pebs_record but are careful not to
918 * unconditionally access the 'extra' entries.
919 */
920 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
921 struct pebs_record_hsw *pebs = __pebs;
922 u64 sample_type;
923 int fll, fst, dsrc;
924 int fl = event->hw.flags;
925
926 if (pebs == NULL)
927 return;
928
929 sample_type = event->attr.sample_type;
930 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
931
932 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
933 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
934
935 perf_sample_data_init(data, 0, event->hw.last_period);
936
937 data->period = event->hw.last_period;
938
939 /*
940 * Use latency for weight (only avail with PEBS-LL)
941 */
942 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
943 data->weight = pebs->lat;
944
945 /*
946 * data.data_src encodes the data source
947 */
948 if (dsrc) {
949 u64 val = PERF_MEM_NA;
950 if (fll)
951 val = load_latency_data(pebs->dse);
952 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
953 val = precise_datala_hsw(event, pebs->dse);
954 else if (fst)
955 val = precise_store_data(pebs->dse);
956 data->data_src.val = val;
957 }
958
959 /*
960 * We use the interrupt regs as a base because the PEBS record
961 * does not contain a full regs set, specifically it seems to
962 * lack segment descriptors, which get used by things like
963 * user_mode().
964 *
965 * In the simple case fix up only the IP and BP,SP regs, for
966 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
967 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
968 */
969 *regs = *iregs;
970 regs->flags = pebs->flags;
971 set_linear_ip(regs, pebs->ip);
972 regs->bp = pebs->bp;
973 regs->sp = pebs->sp;
974
975 if (sample_type & PERF_SAMPLE_REGS_INTR) {
976 regs->ax = pebs->ax;
977 regs->bx = pebs->bx;
978 regs->cx = pebs->cx;
979 regs->dx = pebs->dx;
980 regs->si = pebs->si;
981 regs->di = pebs->di;
982 regs->bp = pebs->bp;
983 regs->sp = pebs->sp;
984
985 regs->flags = pebs->flags;
986 #ifndef CONFIG_X86_32
987 regs->r8 = pebs->r8;
988 regs->r9 = pebs->r9;
989 regs->r10 = pebs->r10;
990 regs->r11 = pebs->r11;
991 regs->r12 = pebs->r12;
992 regs->r13 = pebs->r13;
993 regs->r14 = pebs->r14;
994 regs->r15 = pebs->r15;
995 #endif
996 }
997
998 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
999 regs->ip = pebs->real_ip;
1000 regs->flags |= PERF_EFLAGS_EXACT;
1001 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1002 regs->flags |= PERF_EFLAGS_EXACT;
1003 else
1004 regs->flags &= ~PERF_EFLAGS_EXACT;
1005
1006 if ((sample_type & PERF_SAMPLE_ADDR) &&
1007 x86_pmu.intel_cap.pebs_format >= 1)
1008 data->addr = pebs->dla;
1009
1010 if (x86_pmu.intel_cap.pebs_format >= 2) {
1011 /* Only set the TSX weight when no memory weight. */
1012 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1013 data->weight = intel_hsw_weight(pebs);
1014
1015 if (sample_type & PERF_SAMPLE_TRANSACTION)
1016 data->txn = intel_hsw_transaction(pebs);
1017 }
1018
1019 if (has_branch_stack(event))
1020 data->br_stack = &cpuc->lbr_stack;
1021 }
1022
1023 static inline void *
1024 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1025 {
1026 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1027 void *at;
1028 u64 pebs_status;
1029
1030 if (base == NULL)
1031 return NULL;
1032
1033 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1034 struct pebs_record_nhm *p = at;
1035
1036 if (test_bit(bit, (unsigned long *)&p->status)) {
1037
1038 if (p->status == (1 << bit))
1039 return at;
1040
1041 /* clear non-PEBS bit and re-check */
1042 pebs_status = p->status & cpuc->pebs_enabled;
1043 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1044 if (pebs_status == (1 << bit))
1045 return at;
1046 }
1047 }
1048 return NULL;
1049 }
1050
1051 static void __intel_pmu_pebs_event(struct perf_event *event,
1052 struct pt_regs *iregs,
1053 void *base, void *top,
1054 int bit, int count)
1055 {
1056 struct perf_sample_data data;
1057 struct pt_regs regs;
1058 int i;
1059 void *at = get_next_pebs_record_by_bit(base, top, bit);
1060
1061 if (!intel_pmu_save_and_restart(event) &&
1062 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1063 return;
1064
1065 if (count > 1) {
1066 for (i = 0; i < count - 1; i++) {
1067 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1068 perf_event_output(event, &data, &regs);
1069 at += x86_pmu.pebs_record_size;
1070 at = get_next_pebs_record_by_bit(at, top, bit);
1071 }
1072 }
1073
1074 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1075
1076 /*
1077 * All but the last records are processed.
1078 * The last one is left to be able to call the overflow handler.
1079 */
1080 if (perf_event_overflow(event, &data, &regs)) {
1081 x86_pmu_stop(event, 0);
1082 return;
1083 }
1084
1085 }
1086
1087 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1088 {
1089 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1090 struct debug_store *ds = cpuc->ds;
1091 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1092 struct pebs_record_core *at, *top;
1093 int n;
1094
1095 if (!x86_pmu.pebs_active)
1096 return;
1097
1098 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1099 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1100
1101 /*
1102 * Whatever else happens, drain the thing
1103 */
1104 ds->pebs_index = ds->pebs_buffer_base;
1105
1106 if (!test_bit(0, cpuc->active_mask))
1107 return;
1108
1109 WARN_ON_ONCE(!event);
1110
1111 if (!event->attr.precise_ip)
1112 return;
1113
1114 n = (top - at) / x86_pmu.pebs_record_size;
1115 if (n <= 0)
1116 return;
1117
1118 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1119 }
1120
1121 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1122 {
1123 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1124 struct debug_store *ds = cpuc->ds;
1125 struct perf_event *event;
1126 void *base, *at, *top;
1127 int bit;
1128 short counts[MAX_PEBS_EVENTS] = {};
1129
1130 if (!x86_pmu.pebs_active)
1131 return;
1132
1133 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1134 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1135
1136 ds->pebs_index = ds->pebs_buffer_base;
1137
1138 if (unlikely(base >= top))
1139 return;
1140
1141 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1142 struct pebs_record_nhm *p = at;
1143
1144 bit = find_first_bit((unsigned long *)&p->status,
1145 x86_pmu.max_pebs_events);
1146 if (bit >= x86_pmu.max_pebs_events)
1147 continue;
1148 if (!test_bit(bit, cpuc->active_mask))
1149 continue;
1150 /*
1151 * The PEBS hardware does not deal well with the situation
1152 * when events happen near to each other and multiple bits
1153 * are set. But it should happen rarely.
1154 *
1155 * If these events include one PEBS and multiple non-PEBS
1156 * events, it doesn't impact PEBS record. The record will
1157 * be handled normally. (slow path)
1158 *
1159 * If these events include two or more PEBS events, the
1160 * records for the events can be collapsed into a single
1161 * one, and it's not possible to reconstruct all events
1162 * that caused the PEBS record. It's called collision.
1163 * If collision happened, the record will be dropped.
1164 *
1165 */
1166 if (p->status != (1 << bit)) {
1167 u64 pebs_status;
1168
1169 /* slow path */
1170 pebs_status = p->status & cpuc->pebs_enabled;
1171 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1172 if (pebs_status != (1 << bit))
1173 continue;
1174 }
1175 counts[bit]++;
1176 }
1177
1178 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1179 if (counts[bit] == 0)
1180 continue;
1181 event = cpuc->events[bit];
1182 WARN_ON_ONCE(!event);
1183 WARN_ON_ONCE(!event->attr.precise_ip);
1184
1185 __intel_pmu_pebs_event(event, iregs, base, top, bit, counts[bit]);
1186 }
1187 }
1188
1189 /*
1190 * BTS, PEBS probe and setup
1191 */
1192
1193 void __init intel_ds_init(void)
1194 {
1195 /*
1196 * No support for 32bit formats
1197 */
1198 if (!boot_cpu_has(X86_FEATURE_DTES64))
1199 return;
1200
1201 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1202 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1203 if (x86_pmu.pebs) {
1204 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1205 int format = x86_pmu.intel_cap.pebs_format;
1206
1207 switch (format) {
1208 case 0:
1209 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1210 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1211 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1212 break;
1213
1214 case 1:
1215 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1216 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1217 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1218 break;
1219
1220 case 2:
1221 pr_cont("PEBS fmt2%c, ", pebs_type);
1222 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1223 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1224 break;
1225
1226 default:
1227 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1228 x86_pmu.pebs = 0;
1229 }
1230 }
1231 }
1232
1233 void perf_restore_debug_store(void)
1234 {
1235 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1236
1237 if (!x86_pmu.bts && !x86_pmu.pebs)
1238 return;
1239
1240 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1241 }
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