1 #include <linux/perf_event.h>
2 #include <linux/types.h>
4 #include <asm/perf_event.h>
8 #include "perf_event.h"
12 LBR_FORMAT_LIP
= 0x01,
13 LBR_FORMAT_EIP
= 0x02,
14 LBR_FORMAT_EIP_FLAGS
= 0x03,
15 LBR_FORMAT_EIP_FLAGS2
= 0x04,
16 LBR_FORMAT_INFO
= 0x05,
17 LBR_FORMAT_MAX_KNOWN
= LBR_FORMAT_INFO
,
23 } lbr_desc
[LBR_FORMAT_MAX_KNOWN
+ 1] = {
24 [LBR_FORMAT_EIP_FLAGS
] = LBR_EIP_FLAGS
,
25 [LBR_FORMAT_EIP_FLAGS2
] = LBR_EIP_FLAGS
| LBR_TSX
,
29 * Intel LBR_SELECT bits
30 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
32 * Hardware branch filter (not available on all CPUs)
34 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
35 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
36 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
37 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
38 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
39 #define LBR_RETURN_BIT 5 /* do not capture near returns */
40 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
41 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
42 #define LBR_FAR_BIT 8 /* do not capture far branches */
43 #define LBR_CALL_STACK_BIT 9 /* enable call stack */
45 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
46 #define LBR_USER (1 << LBR_USER_BIT)
47 #define LBR_JCC (1 << LBR_JCC_BIT)
48 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
49 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
50 #define LBR_RETURN (1 << LBR_RETURN_BIT)
51 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
52 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
53 #define LBR_FAR (1 << LBR_FAR_BIT)
54 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
56 #define LBR_PLM (LBR_KERNEL | LBR_USER)
58 #define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */
59 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
60 #define LBR_IGN 0 /* ignored */
71 #define LBR_FROM_FLAG_MISPRED (1ULL << 63)
72 #define LBR_FROM_FLAG_IN_TX (1ULL << 62)
73 #define LBR_FROM_FLAG_ABORT (1ULL << 61)
76 * x86control flow change classification
77 * x86control flow changes include branches, interrupts, traps, faults
80 X86_BR_NONE
= 0, /* unknown */
82 X86_BR_USER
= 1 << 0, /* branch target is user */
83 X86_BR_KERNEL
= 1 << 1, /* branch target is kernel */
85 X86_BR_CALL
= 1 << 2, /* call */
86 X86_BR_RET
= 1 << 3, /* return */
87 X86_BR_SYSCALL
= 1 << 4, /* syscall */
88 X86_BR_SYSRET
= 1 << 5, /* syscall return */
89 X86_BR_INT
= 1 << 6, /* sw interrupt */
90 X86_BR_IRET
= 1 << 7, /* return from interrupt */
91 X86_BR_JCC
= 1 << 8, /* conditional */
92 X86_BR_JMP
= 1 << 9, /* jump */
93 X86_BR_IRQ
= 1 << 10,/* hw interrupt or trap or fault */
94 X86_BR_IND_CALL
= 1 << 11,/* indirect calls */
95 X86_BR_ABORT
= 1 << 12,/* transaction abort */
96 X86_BR_IN_TX
= 1 << 13,/* in transaction */
97 X86_BR_NO_TX
= 1 << 14,/* not in transaction */
98 X86_BR_ZERO_CALL
= 1 << 15,/* zero length call */
99 X86_BR_CALL_STACK
= 1 << 16,/* call stack */
100 X86_BR_IND_JMP
= 1 << 17,/* indirect jump */
103 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
104 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
121 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
123 #define X86_BR_ANY_CALL \
131 static void intel_pmu_lbr_filter(struct cpu_hw_events
*cpuc
);
134 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
135 * otherwise it becomes near impossible to get a reliable stack.
138 static void __intel_pmu_lbr_enable(bool pmi
)
140 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
141 u64 debugctl
, lbr_select
= 0, orig_debugctl
;
144 * No need to unfreeze manually, as v4 can do that as part
145 * of the GLOBAL_STATUS ack.
147 if (pmi
&& x86_pmu
.version
>= 4)
151 * No need to reprogram LBR_SELECT in a PMI, as it
155 lbr_select
= cpuc
->lbr_sel
->config
;
157 wrmsrl(MSR_LBR_SELECT
, lbr_select
);
159 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
160 orig_debugctl
= debugctl
;
161 debugctl
|= DEBUGCTLMSR_LBR
;
163 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
164 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
165 * may cause superfluous increase/decrease of LBR_TOS.
167 if (!(lbr_select
& LBR_CALL_STACK
))
168 debugctl
|= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
;
169 if (orig_debugctl
!= debugctl
)
170 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
173 static void __intel_pmu_lbr_disable(void)
177 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
178 debugctl
&= ~(DEBUGCTLMSR_LBR
| DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
);
179 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
182 static void intel_pmu_lbr_reset_32(void)
186 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++)
187 wrmsrl(x86_pmu
.lbr_from
+ i
, 0);
190 static void intel_pmu_lbr_reset_64(void)
194 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
195 wrmsrl(x86_pmu
.lbr_from
+ i
, 0);
196 wrmsrl(x86_pmu
.lbr_to
+ i
, 0);
197 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
)
198 wrmsrl(MSR_LBR_INFO_0
+ i
, 0);
202 void intel_pmu_lbr_reset(void)
207 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_32
)
208 intel_pmu_lbr_reset_32();
210 intel_pmu_lbr_reset_64();
214 * TOS = most recently recorded branch
216 static inline u64
intel_pmu_lbr_tos(void)
220 rdmsrl(x86_pmu
.lbr_tos
, tos
);
229 static void __intel_pmu_lbr_restore(struct x86_perf_task_context
*task_ctx
)
232 unsigned lbr_idx
, mask
;
235 if (task_ctx
->lbr_callstack_users
== 0 ||
236 task_ctx
->lbr_stack_state
== LBR_NONE
) {
237 intel_pmu_lbr_reset();
241 mask
= x86_pmu
.lbr_nr
- 1;
242 tos
= intel_pmu_lbr_tos();
243 for (i
= 0; i
< tos
; i
++) {
244 lbr_idx
= (tos
- i
) & mask
;
245 wrmsrl(x86_pmu
.lbr_from
+ lbr_idx
, task_ctx
->lbr_from
[i
]);
246 wrmsrl(x86_pmu
.lbr_to
+ lbr_idx
, task_ctx
->lbr_to
[i
]);
247 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
)
248 wrmsrl(MSR_LBR_INFO_0
+ lbr_idx
, task_ctx
->lbr_info
[i
]);
250 task_ctx
->lbr_stack_state
= LBR_NONE
;
253 static void __intel_pmu_lbr_save(struct x86_perf_task_context
*task_ctx
)
256 unsigned lbr_idx
, mask
;
259 if (task_ctx
->lbr_callstack_users
== 0) {
260 task_ctx
->lbr_stack_state
= LBR_NONE
;
264 mask
= x86_pmu
.lbr_nr
- 1;
265 tos
= intel_pmu_lbr_tos();
266 for (i
= 0; i
< tos
; i
++) {
267 lbr_idx
= (tos
- i
) & mask
;
268 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, task_ctx
->lbr_from
[i
]);
269 rdmsrl(x86_pmu
.lbr_to
+ lbr_idx
, task_ctx
->lbr_to
[i
]);
270 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
)
271 rdmsrl(MSR_LBR_INFO_0
+ lbr_idx
, task_ctx
->lbr_info
[i
]);
273 task_ctx
->lbr_stack_state
= LBR_VALID
;
276 void intel_pmu_lbr_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
278 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
279 struct x86_perf_task_context
*task_ctx
;
282 * If LBR callstack feature is enabled and the stack was saved when
283 * the task was scheduled out, restore the stack. Otherwise flush
286 task_ctx
= ctx
? ctx
->task_ctx_data
: NULL
;
289 __intel_pmu_lbr_restore(task_ctx
);
290 cpuc
->lbr_context
= ctx
;
292 __intel_pmu_lbr_save(task_ctx
);
298 * When sampling the branck stack in system-wide, it may be
299 * necessary to flush the stack on context switch. This happens
300 * when the branch stack does not tag its entries with the pid
301 * of the current task. Otherwise it becomes impossible to
302 * associate a branch entry with a task. This ambiguity is more
303 * likely to appear when the branch stack supports priv level
304 * filtering and the user sets it to monitor only at the user
305 * level (which could be a useful measurement in system-wide
306 * mode). In that case, the risk is high of having a branch
307 * stack with branch from multiple tasks.
310 intel_pmu_lbr_reset();
311 cpuc
->lbr_context
= ctx
;
315 static inline bool branch_user_callstack(unsigned br_sel
)
317 return (br_sel
& X86_BR_USER
) && (br_sel
& X86_BR_CALL_STACK
);
320 void intel_pmu_lbr_enable(struct perf_event
*event
)
322 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
323 struct x86_perf_task_context
*task_ctx
;
329 * Reset the LBR stack if we changed task context to
332 if (event
->ctx
->task
&& cpuc
->lbr_context
!= event
->ctx
) {
333 intel_pmu_lbr_reset();
334 cpuc
->lbr_context
= event
->ctx
;
336 cpuc
->br_sel
= event
->hw
.branch_reg
.reg
;
338 if (branch_user_callstack(cpuc
->br_sel
) && event
->ctx
&&
339 event
->ctx
->task_ctx_data
) {
340 task_ctx
= event
->ctx
->task_ctx_data
;
341 task_ctx
->lbr_callstack_users
++;
345 perf_sched_cb_inc(event
->ctx
->pmu
);
348 void intel_pmu_lbr_disable(struct perf_event
*event
)
350 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
351 struct x86_perf_task_context
*task_ctx
;
356 if (branch_user_callstack(cpuc
->br_sel
) && event
->ctx
&&
357 event
->ctx
->task_ctx_data
) {
358 task_ctx
= event
->ctx
->task_ctx_data
;
359 task_ctx
->lbr_callstack_users
--;
363 WARN_ON_ONCE(cpuc
->lbr_users
< 0);
364 perf_sched_cb_dec(event
->ctx
->pmu
);
366 if (cpuc
->enabled
&& !cpuc
->lbr_users
) {
367 __intel_pmu_lbr_disable();
368 /* avoid stale pointer */
369 cpuc
->lbr_context
= NULL
;
373 void intel_pmu_lbr_enable_all(bool pmi
)
375 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
378 __intel_pmu_lbr_enable(pmi
);
381 void intel_pmu_lbr_disable_all(void)
383 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
386 __intel_pmu_lbr_disable();
389 static void intel_pmu_lbr_read_32(struct cpu_hw_events
*cpuc
)
391 unsigned long mask
= x86_pmu
.lbr_nr
- 1;
392 u64 tos
= intel_pmu_lbr_tos();
395 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
396 unsigned long lbr_idx
= (tos
- i
) & mask
;
405 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, msr_lastbranch
.lbr
);
407 cpuc
->lbr_entries
[i
].from
= msr_lastbranch
.from
;
408 cpuc
->lbr_entries
[i
].to
= msr_lastbranch
.to
;
409 cpuc
->lbr_entries
[i
].mispred
= 0;
410 cpuc
->lbr_entries
[i
].predicted
= 0;
411 cpuc
->lbr_entries
[i
].reserved
= 0;
413 cpuc
->lbr_stack
.nr
= i
;
417 * Due to lack of segmentation in Linux the effective address (offset)
418 * is the same as the linear address, allowing us to merge the LIP and EIP
421 static void intel_pmu_lbr_read_64(struct cpu_hw_events
*cpuc
)
423 unsigned long mask
= x86_pmu
.lbr_nr
- 1;
424 int lbr_format
= x86_pmu
.intel_cap
.lbr_format
;
425 u64 tos
= intel_pmu_lbr_tos();
428 int num
= x86_pmu
.lbr_nr
;
430 if (cpuc
->lbr_sel
->config
& LBR_CALL_STACK
)
433 for (i
= 0; i
< num
; i
++) {
434 unsigned long lbr_idx
= (tos
- i
) & mask
;
435 u64 from
, to
, mis
= 0, pred
= 0, in_tx
= 0, abort
= 0;
438 int lbr_flags
= lbr_desc
[lbr_format
];
440 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, from
);
441 rdmsrl(x86_pmu
.lbr_to
+ lbr_idx
, to
);
443 if (lbr_format
== LBR_FORMAT_INFO
) {
446 rdmsrl(MSR_LBR_INFO_0
+ lbr_idx
, info
);
447 mis
= !!(info
& LBR_INFO_MISPRED
);
449 in_tx
= !!(info
& LBR_INFO_IN_TX
);
450 abort
= !!(info
& LBR_INFO_ABORT
);
451 cycles
= (info
& LBR_INFO_CYCLES
);
453 if (lbr_flags
& LBR_EIP_FLAGS
) {
454 mis
= !!(from
& LBR_FROM_FLAG_MISPRED
);
458 if (lbr_flags
& LBR_TSX
) {
459 in_tx
= !!(from
& LBR_FROM_FLAG_IN_TX
);
460 abort
= !!(from
& LBR_FROM_FLAG_ABORT
);
463 from
= (u64
)((((s64
)from
) << skip
) >> skip
);
466 * Some CPUs report duplicated abort records,
467 * with the second entry not having an abort bit set.
468 * Skip them here. This loop runs backwards,
469 * so we need to undo the previous record.
470 * If the abort just happened outside the window
471 * the extra entry cannot be removed.
473 if (abort
&& x86_pmu
.lbr_double_abort
&& out
> 0)
476 cpuc
->lbr_entries
[out
].from
= from
;
477 cpuc
->lbr_entries
[out
].to
= to
;
478 cpuc
->lbr_entries
[out
].mispred
= mis
;
479 cpuc
->lbr_entries
[out
].predicted
= pred
;
480 cpuc
->lbr_entries
[out
].in_tx
= in_tx
;
481 cpuc
->lbr_entries
[out
].abort
= abort
;
482 cpuc
->lbr_entries
[out
].cycles
= cycles
;
483 cpuc
->lbr_entries
[out
].reserved
= 0;
486 cpuc
->lbr_stack
.nr
= out
;
489 void intel_pmu_lbr_read(void)
491 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
493 if (!cpuc
->lbr_users
)
496 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_32
)
497 intel_pmu_lbr_read_32(cpuc
);
499 intel_pmu_lbr_read_64(cpuc
);
501 intel_pmu_lbr_filter(cpuc
);
506 * - in case there is no HW filter
507 * - in case the HW filter has errata or limitations
509 static int intel_pmu_setup_sw_lbr_filter(struct perf_event
*event
)
511 u64 br_type
= event
->attr
.branch_sample_type
;
514 if (br_type
& PERF_SAMPLE_BRANCH_USER
)
517 if (br_type
& PERF_SAMPLE_BRANCH_KERNEL
)
518 mask
|= X86_BR_KERNEL
;
520 /* we ignore BRANCH_HV here */
522 if (br_type
& PERF_SAMPLE_BRANCH_ANY
)
525 if (br_type
& PERF_SAMPLE_BRANCH_ANY_CALL
)
526 mask
|= X86_BR_ANY_CALL
;
528 if (br_type
& PERF_SAMPLE_BRANCH_ANY_RETURN
)
529 mask
|= X86_BR_RET
| X86_BR_IRET
| X86_BR_SYSRET
;
531 if (br_type
& PERF_SAMPLE_BRANCH_IND_CALL
)
532 mask
|= X86_BR_IND_CALL
;
534 if (br_type
& PERF_SAMPLE_BRANCH_ABORT_TX
)
535 mask
|= X86_BR_ABORT
;
537 if (br_type
& PERF_SAMPLE_BRANCH_IN_TX
)
538 mask
|= X86_BR_IN_TX
;
540 if (br_type
& PERF_SAMPLE_BRANCH_NO_TX
)
541 mask
|= X86_BR_NO_TX
;
543 if (br_type
& PERF_SAMPLE_BRANCH_COND
)
546 if (br_type
& PERF_SAMPLE_BRANCH_CALL_STACK
) {
547 if (!x86_pmu_has_lbr_callstack())
549 if (mask
& ~(X86_BR_USER
| X86_BR_KERNEL
))
551 mask
|= X86_BR_CALL
| X86_BR_IND_CALL
| X86_BR_RET
|
555 if (br_type
& PERF_SAMPLE_BRANCH_IND_JUMP
)
556 mask
|= X86_BR_IND_JMP
;
558 if (br_type
& PERF_SAMPLE_BRANCH_CALL
)
559 mask
|= X86_BR_CALL
| X86_BR_ZERO_CALL
;
561 * stash actual user request into reg, it may
562 * be used by fixup code for some CPU
564 event
->hw
.branch_reg
.reg
= mask
;
569 * setup the HW LBR filter
570 * Used only when available, may not be enough to disambiguate
571 * all branches, may need the help of the SW filter
573 static int intel_pmu_setup_hw_lbr_filter(struct perf_event
*event
)
575 struct hw_perf_event_extra
*reg
;
576 u64 br_type
= event
->attr
.branch_sample_type
;
580 for (i
= 0; i
< PERF_SAMPLE_BRANCH_MAX_SHIFT
; i
++) {
581 if (!(br_type
& (1ULL << i
)))
584 v
= x86_pmu
.lbr_sel_map
[i
];
585 if (v
== LBR_NOT_SUPP
)
591 reg
= &event
->hw
.branch_reg
;
592 reg
->idx
= EXTRA_REG_LBR
;
595 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
596 * in suppress mode. So LBR_SELECT should be set to
597 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
599 reg
->config
= mask
^ x86_pmu
.lbr_sel_mask
;
604 int intel_pmu_setup_lbr_filter(struct perf_event
*event
)
615 * setup SW LBR filter
617 ret
= intel_pmu_setup_sw_lbr_filter(event
);
622 * setup HW LBR filter, if any
624 if (x86_pmu
.lbr_sel_map
)
625 ret
= intel_pmu_setup_hw_lbr_filter(event
);
631 * return the type of control flow change at address "from"
632 * intruction is not necessarily a branch (in case of interrupt).
634 * The branch type returned also includes the priv level of the
635 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
637 * If a branch type is unknown OR the instruction cannot be
638 * decoded (e.g., text page not present), then X86_BR_NONE is
641 static int branch_type(unsigned long from
, unsigned long to
, int abort
)
645 int bytes_read
, bytes_left
;
646 int ret
= X86_BR_NONE
;
647 int ext
, to_plm
, from_plm
;
648 u8 buf
[MAX_INSN_SIZE
];
651 to_plm
= kernel_ip(to
) ? X86_BR_KERNEL
: X86_BR_USER
;
652 from_plm
= kernel_ip(from
) ? X86_BR_KERNEL
: X86_BR_USER
;
655 * maybe zero if lbr did not fill up after a reset by the time
656 * we get a PMU interrupt
658 if (from
== 0 || to
== 0)
662 return X86_BR_ABORT
| to_plm
;
664 if (from_plm
== X86_BR_USER
) {
666 * can happen if measuring at the user level only
667 * and we interrupt in a kernel thread, e.g., idle.
672 /* may fail if text not present */
673 bytes_left
= copy_from_user_nmi(buf
, (void __user
*)from
,
675 bytes_read
= MAX_INSN_SIZE
- bytes_left
;
682 * The LBR logs any address in the IP, even if the IP just
683 * faulted. This means userspace can control the from address.
684 * Ensure we don't blindy read any address by validating it is
685 * a known text address.
687 if (kernel_text_address(from
)) {
690 * Assume we can get the maximum possible size
691 * when grabbing kernel data. This is not
692 * _strictly_ true since we could possibly be
693 * executing up next to a memory hole, but
694 * it is very unlikely to be a problem.
696 bytes_read
= MAX_INSN_SIZE
;
703 * decoder needs to know the ABI especially
704 * on 64-bit systems running 32-bit apps
707 is64
= kernel_ip((unsigned long)addr
) || !test_thread_flag(TIF_IA32
);
709 insn_init(&insn
, addr
, bytes_read
, is64
);
710 insn_get_opcode(&insn
);
711 if (!insn
.opcode
.got
)
714 switch (insn
.opcode
.bytes
[0]) {
716 switch (insn
.opcode
.bytes
[1]) {
717 case 0x05: /* syscall */
718 case 0x34: /* sysenter */
719 ret
= X86_BR_SYSCALL
;
721 case 0x07: /* sysret */
722 case 0x35: /* sysexit */
725 case 0x80 ... 0x8f: /* conditional */
732 case 0x70 ... 0x7f: /* conditional */
735 case 0xc2: /* near ret */
736 case 0xc3: /* near ret */
737 case 0xca: /* far ret */
738 case 0xcb: /* far ret */
741 case 0xcf: /* iret */
744 case 0xcc ... 0xce: /* int */
747 case 0xe8: /* call near rel */
748 insn_get_immediate(&insn
);
749 if (insn
.immediate1
.value
== 0) {
750 /* zero length call */
751 ret
= X86_BR_ZERO_CALL
;
754 case 0x9a: /* call far absolute */
757 case 0xe0 ... 0xe3: /* loop jmp */
760 case 0xe9 ... 0xeb: /* jmp */
763 case 0xff: /* call near absolute, call far absolute ind */
764 insn_get_modrm(&insn
);
765 ext
= (insn
.modrm
.bytes
[0] >> 3) & 0x7;
767 case 2: /* near ind call */
768 case 3: /* far ind call */
769 ret
= X86_BR_IND_CALL
;
773 ret
= X86_BR_IND_JMP
;
781 * interrupts, traps, faults (and thus ring transition) may
782 * occur on any instructions. Thus, to classify them correctly,
783 * we need to first look at the from and to priv levels. If they
784 * are different and to is in the kernel, then it indicates
785 * a ring transition. If the from instruction is not a ring
786 * transition instr (syscall, systenter, int), then it means
787 * it was a irq, trap or fault.
789 * we have no way of detecting kernel to kernel faults.
791 if (from_plm
== X86_BR_USER
&& to_plm
== X86_BR_KERNEL
792 && ret
!= X86_BR_SYSCALL
&& ret
!= X86_BR_INT
)
796 * branch priv level determined by target as
797 * is done by HW when LBR_SELECT is implemented
799 if (ret
!= X86_BR_NONE
)
806 * implement actual branch filter based on user demand.
807 * Hardware may not exactly satisfy that request, thus
808 * we need to inspect opcodes. Mismatched branches are
809 * discarded. Therefore, the number of branches returned
810 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
813 intel_pmu_lbr_filter(struct cpu_hw_events
*cpuc
)
816 int br_sel
= cpuc
->br_sel
;
818 bool compress
= false;
820 /* if sampling all branches, then nothing to filter */
821 if ((br_sel
& X86_BR_ALL
) == X86_BR_ALL
)
824 for (i
= 0; i
< cpuc
->lbr_stack
.nr
; i
++) {
826 from
= cpuc
->lbr_entries
[i
].from
;
827 to
= cpuc
->lbr_entries
[i
].to
;
829 type
= branch_type(from
, to
, cpuc
->lbr_entries
[i
].abort
);
830 if (type
!= X86_BR_NONE
&& (br_sel
& X86_BR_ANYTX
)) {
831 if (cpuc
->lbr_entries
[i
].in_tx
)
832 type
|= X86_BR_IN_TX
;
834 type
|= X86_BR_NO_TX
;
837 /* if type does not correspond, then discard */
838 if (type
== X86_BR_NONE
|| (br_sel
& type
) != type
) {
839 cpuc
->lbr_entries
[i
].from
= 0;
847 /* remove all entries with from=0 */
848 for (i
= 0; i
< cpuc
->lbr_stack
.nr
; ) {
849 if (!cpuc
->lbr_entries
[i
].from
) {
851 while (++j
< cpuc
->lbr_stack
.nr
)
852 cpuc
->lbr_entries
[j
-1] = cpuc
->lbr_entries
[j
];
853 cpuc
->lbr_stack
.nr
--;
854 if (!cpuc
->lbr_entries
[i
].from
)
862 * Map interface branch filters onto LBR filters
864 static const int nhm_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
865 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
866 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
867 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
868 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
869 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_REL_JMP
870 | LBR_IND_JMP
| LBR_FAR
,
872 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
874 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] =
875 LBR_REL_CALL
| LBR_IND_CALL
| LBR_REL_JMP
| LBR_IND_JMP
| LBR_FAR
,
877 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
879 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
| LBR_IND_JMP
,
880 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
881 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
] = LBR_IND_JMP
,
884 static const int snb_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
885 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
886 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
887 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
888 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
889 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_FAR
,
890 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
892 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
,
893 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
894 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
] = LBR_IND_JMP
,
895 [PERF_SAMPLE_BRANCH_CALL_SHIFT
] = LBR_REL_CALL
,
898 static const int hsw_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
899 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
900 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
901 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
902 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
903 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_FAR
,
904 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
906 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
,
907 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
908 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
909 | LBR_RETURN
| LBR_CALL_STACK
,
910 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
] = LBR_IND_JMP
,
911 [PERF_SAMPLE_BRANCH_CALL_SHIFT
] = LBR_REL_CALL
,
915 void __init
intel_pmu_lbr_init_core(void)
918 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
919 x86_pmu
.lbr_from
= MSR_LBR_CORE_FROM
;
920 x86_pmu
.lbr_to
= MSR_LBR_CORE_TO
;
923 * SW branch filter usage:
924 * - compensate for lack of HW filter
926 pr_cont("4-deep LBR, ");
929 /* nehalem/westmere */
930 void __init
intel_pmu_lbr_init_nhm(void)
933 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
934 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
935 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
937 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
938 x86_pmu
.lbr_sel_map
= nhm_lbr_sel_map
;
941 * SW branch filter usage:
942 * - workaround LBR_SEL errata (see above)
943 * - support syscall, sysret capture.
944 * That requires LBR_FAR but that means far
945 * jmp need to be filtered out
947 pr_cont("16-deep LBR, ");
951 void __init
intel_pmu_lbr_init_snb(void)
954 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
955 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
956 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
958 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
959 x86_pmu
.lbr_sel_map
= snb_lbr_sel_map
;
962 * SW branch filter usage:
963 * - support syscall, sysret capture.
964 * That requires LBR_FAR but that means far
965 * jmp need to be filtered out
967 pr_cont("16-deep LBR, ");
971 void intel_pmu_lbr_init_hsw(void)
974 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
975 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
976 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
978 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
979 x86_pmu
.lbr_sel_map
= hsw_lbr_sel_map
;
981 pr_cont("16-deep LBR, ");
985 __init
void intel_pmu_lbr_init_skl(void)
988 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
989 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
990 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
992 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
993 x86_pmu
.lbr_sel_map
= hsw_lbr_sel_map
;
996 * SW branch filter usage:
997 * - support syscall, sysret capture.
998 * That requires LBR_FAR but that means far
999 * jmp need to be filtered out
1001 pr_cont("32-deep LBR, ");
1005 void __init
intel_pmu_lbr_init_atom(void)
1008 * only models starting at stepping 10 seems
1009 * to have an operational LBR which can freeze
1012 if (boot_cpu_data
.x86_model
== 28
1013 && boot_cpu_data
.x86_mask
< 10) {
1014 pr_cont("LBR disabled due to erratum");
1019 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1020 x86_pmu
.lbr_from
= MSR_LBR_CORE_FROM
;
1021 x86_pmu
.lbr_to
= MSR_LBR_CORE_TO
;
1024 * SW branch filter usage:
1025 * - compensate for lack of HW filter
1027 pr_cont("8-deep LBR, ");