1 #include <linux/perf_event.h>
2 #include <linux/types.h>
4 #include <asm/perf_event.h>
8 #include "perf_event.h"
12 LBR_FORMAT_LIP
= 0x01,
13 LBR_FORMAT_EIP
= 0x02,
14 LBR_FORMAT_EIP_FLAGS
= 0x03,
15 LBR_FORMAT_EIP_FLAGS2
= 0x04,
16 LBR_FORMAT_INFO
= 0x05,
17 LBR_FORMAT_MAX_KNOWN
= LBR_FORMAT_INFO
,
23 } lbr_desc
[LBR_FORMAT_MAX_KNOWN
+ 1] = {
24 [LBR_FORMAT_EIP_FLAGS
] = LBR_EIP_FLAGS
,
25 [LBR_FORMAT_EIP_FLAGS2
] = LBR_EIP_FLAGS
| LBR_TSX
,
29 * Intel LBR_SELECT bits
30 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
32 * Hardware branch filter (not available on all CPUs)
34 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
35 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
36 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
37 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
38 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
39 #define LBR_RETURN_BIT 5 /* do not capture near returns */
40 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
41 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
42 #define LBR_FAR_BIT 8 /* do not capture far branches */
43 #define LBR_CALL_STACK_BIT 9 /* enable call stack */
45 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
46 #define LBR_USER (1 << LBR_USER_BIT)
47 #define LBR_JCC (1 << LBR_JCC_BIT)
48 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
49 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
50 #define LBR_RETURN (1 << LBR_RETURN_BIT)
51 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
52 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
53 #define LBR_FAR (1 << LBR_FAR_BIT)
54 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
56 #define LBR_PLM (LBR_KERNEL | LBR_USER)
58 #define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */
59 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
60 #define LBR_IGN 0 /* ignored */
71 #define LBR_FROM_FLAG_MISPRED (1ULL << 63)
72 #define LBR_FROM_FLAG_IN_TX (1ULL << 62)
73 #define LBR_FROM_FLAG_ABORT (1ULL << 61)
76 * x86control flow change classification
77 * x86control flow changes include branches, interrupts, traps, faults
80 X86_BR_NONE
= 0, /* unknown */
82 X86_BR_USER
= 1 << 0, /* branch target is user */
83 X86_BR_KERNEL
= 1 << 1, /* branch target is kernel */
85 X86_BR_CALL
= 1 << 2, /* call */
86 X86_BR_RET
= 1 << 3, /* return */
87 X86_BR_SYSCALL
= 1 << 4, /* syscall */
88 X86_BR_SYSRET
= 1 << 5, /* syscall return */
89 X86_BR_INT
= 1 << 6, /* sw interrupt */
90 X86_BR_IRET
= 1 << 7, /* return from interrupt */
91 X86_BR_JCC
= 1 << 8, /* conditional */
92 X86_BR_JMP
= 1 << 9, /* jump */
93 X86_BR_IRQ
= 1 << 10,/* hw interrupt or trap or fault */
94 X86_BR_IND_CALL
= 1 << 11,/* indirect calls */
95 X86_BR_ABORT
= 1 << 12,/* transaction abort */
96 X86_BR_IN_TX
= 1 << 13,/* in transaction */
97 X86_BR_NO_TX
= 1 << 14,/* not in transaction */
98 X86_BR_ZERO_CALL
= 1 << 15,/* zero length call */
99 X86_BR_CALL_STACK
= 1 << 16,/* call stack */
100 X86_BR_IND_JMP
= 1 << 17,/* indirect jump */
103 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
104 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
121 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
123 #define X86_BR_ANY_CALL \
131 static void intel_pmu_lbr_filter(struct cpu_hw_events
*cpuc
);
134 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
135 * otherwise it becomes near impossible to get a reliable stack.
138 static void __intel_pmu_lbr_enable(bool pmi
)
140 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
141 u64 debugctl
, lbr_select
= 0, orig_debugctl
;
144 * No need to unfreeze manually, as v4 can do that as part
145 * of the GLOBAL_STATUS ack.
147 if (pmi
&& x86_pmu
.version
>= 4)
151 * No need to reprogram LBR_SELECT in a PMI, as it
155 lbr_select
= cpuc
->lbr_sel
->config
;
157 wrmsrl(MSR_LBR_SELECT
, lbr_select
);
159 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
160 orig_debugctl
= debugctl
;
161 debugctl
|= DEBUGCTLMSR_LBR
;
163 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
164 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
165 * may cause superfluous increase/decrease of LBR_TOS.
167 if (!(lbr_select
& LBR_CALL_STACK
))
168 debugctl
|= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
;
169 if (orig_debugctl
!= debugctl
)
170 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
173 static void __intel_pmu_lbr_disable(void)
177 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
178 debugctl
&= ~(DEBUGCTLMSR_LBR
| DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
);
179 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
182 static void intel_pmu_lbr_reset_32(void)
186 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++)
187 wrmsrl(x86_pmu
.lbr_from
+ i
, 0);
190 static void intel_pmu_lbr_reset_64(void)
194 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
195 wrmsrl(x86_pmu
.lbr_from
+ i
, 0);
196 wrmsrl(x86_pmu
.lbr_to
+ i
, 0);
197 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
)
198 wrmsrl(MSR_LBR_INFO_0
+ i
, 0);
202 void intel_pmu_lbr_reset(void)
207 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_32
)
208 intel_pmu_lbr_reset_32();
210 intel_pmu_lbr_reset_64();
214 * TOS = most recently recorded branch
216 static inline u64
intel_pmu_lbr_tos(void)
220 rdmsrl(x86_pmu
.lbr_tos
, tos
);
229 static void __intel_pmu_lbr_restore(struct x86_perf_task_context
*task_ctx
)
232 unsigned lbr_idx
, mask
;
235 if (task_ctx
->lbr_callstack_users
== 0 ||
236 task_ctx
->lbr_stack_state
== LBR_NONE
) {
237 intel_pmu_lbr_reset();
241 mask
= x86_pmu
.lbr_nr
- 1;
243 for (i
= 0; i
< tos
; i
++) {
244 lbr_idx
= (tos
- i
) & mask
;
245 wrmsrl(x86_pmu
.lbr_from
+ lbr_idx
, task_ctx
->lbr_from
[i
]);
246 wrmsrl(x86_pmu
.lbr_to
+ lbr_idx
, task_ctx
->lbr_to
[i
]);
247 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
)
248 wrmsrl(MSR_LBR_INFO_0
+ lbr_idx
, task_ctx
->lbr_info
[i
]);
250 wrmsrl(x86_pmu
.lbr_tos
, tos
);
251 task_ctx
->lbr_stack_state
= LBR_NONE
;
254 static void __intel_pmu_lbr_save(struct x86_perf_task_context
*task_ctx
)
257 unsigned lbr_idx
, mask
;
260 if (task_ctx
->lbr_callstack_users
== 0) {
261 task_ctx
->lbr_stack_state
= LBR_NONE
;
265 mask
= x86_pmu
.lbr_nr
- 1;
266 tos
= intel_pmu_lbr_tos();
267 for (i
= 0; i
< tos
; i
++) {
268 lbr_idx
= (tos
- i
) & mask
;
269 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, task_ctx
->lbr_from
[i
]);
270 rdmsrl(x86_pmu
.lbr_to
+ lbr_idx
, task_ctx
->lbr_to
[i
]);
271 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
)
272 rdmsrl(MSR_LBR_INFO_0
+ lbr_idx
, task_ctx
->lbr_info
[i
]);
275 task_ctx
->lbr_stack_state
= LBR_VALID
;
278 void intel_pmu_lbr_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
280 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
281 struct x86_perf_task_context
*task_ctx
;
284 * If LBR callstack feature is enabled and the stack was saved when
285 * the task was scheduled out, restore the stack. Otherwise flush
288 task_ctx
= ctx
? ctx
->task_ctx_data
: NULL
;
291 __intel_pmu_lbr_restore(task_ctx
);
292 cpuc
->lbr_context
= ctx
;
294 __intel_pmu_lbr_save(task_ctx
);
300 * When sampling the branck stack in system-wide, it may be
301 * necessary to flush the stack on context switch. This happens
302 * when the branch stack does not tag its entries with the pid
303 * of the current task. Otherwise it becomes impossible to
304 * associate a branch entry with a task. This ambiguity is more
305 * likely to appear when the branch stack supports priv level
306 * filtering and the user sets it to monitor only at the user
307 * level (which could be a useful measurement in system-wide
308 * mode). In that case, the risk is high of having a branch
309 * stack with branch from multiple tasks.
312 intel_pmu_lbr_reset();
313 cpuc
->lbr_context
= ctx
;
317 static inline bool branch_user_callstack(unsigned br_sel
)
319 return (br_sel
& X86_BR_USER
) && (br_sel
& X86_BR_CALL_STACK
);
322 void intel_pmu_lbr_enable(struct perf_event
*event
)
324 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
325 struct x86_perf_task_context
*task_ctx
;
331 * Reset the LBR stack if we changed task context to
334 if (event
->ctx
->task
&& cpuc
->lbr_context
!= event
->ctx
) {
335 intel_pmu_lbr_reset();
336 cpuc
->lbr_context
= event
->ctx
;
338 cpuc
->br_sel
= event
->hw
.branch_reg
.reg
;
340 if (branch_user_callstack(cpuc
->br_sel
) && event
->ctx
&&
341 event
->ctx
->task_ctx_data
) {
342 task_ctx
= event
->ctx
->task_ctx_data
;
343 task_ctx
->lbr_callstack_users
++;
347 perf_sched_cb_inc(event
->ctx
->pmu
);
350 void intel_pmu_lbr_disable(struct perf_event
*event
)
352 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
353 struct x86_perf_task_context
*task_ctx
;
358 if (branch_user_callstack(cpuc
->br_sel
) && event
->ctx
&&
359 event
->ctx
->task_ctx_data
) {
360 task_ctx
= event
->ctx
->task_ctx_data
;
361 task_ctx
->lbr_callstack_users
--;
365 WARN_ON_ONCE(cpuc
->lbr_users
< 0);
366 perf_sched_cb_dec(event
->ctx
->pmu
);
368 if (cpuc
->enabled
&& !cpuc
->lbr_users
) {
369 __intel_pmu_lbr_disable();
370 /* avoid stale pointer */
371 cpuc
->lbr_context
= NULL
;
375 void intel_pmu_lbr_enable_all(bool pmi
)
377 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
380 __intel_pmu_lbr_enable(pmi
);
383 void intel_pmu_lbr_disable_all(void)
385 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
388 __intel_pmu_lbr_disable();
391 static void intel_pmu_lbr_read_32(struct cpu_hw_events
*cpuc
)
393 unsigned long mask
= x86_pmu
.lbr_nr
- 1;
394 u64 tos
= intel_pmu_lbr_tos();
397 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
398 unsigned long lbr_idx
= (tos
- i
) & mask
;
407 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, msr_lastbranch
.lbr
);
409 cpuc
->lbr_entries
[i
].from
= msr_lastbranch
.from
;
410 cpuc
->lbr_entries
[i
].to
= msr_lastbranch
.to
;
411 cpuc
->lbr_entries
[i
].mispred
= 0;
412 cpuc
->lbr_entries
[i
].predicted
= 0;
413 cpuc
->lbr_entries
[i
].reserved
= 0;
415 cpuc
->lbr_stack
.nr
= i
;
419 * Due to lack of segmentation in Linux the effective address (offset)
420 * is the same as the linear address, allowing us to merge the LIP and EIP
423 static void intel_pmu_lbr_read_64(struct cpu_hw_events
*cpuc
)
425 unsigned long mask
= x86_pmu
.lbr_nr
- 1;
426 int lbr_format
= x86_pmu
.intel_cap
.lbr_format
;
427 u64 tos
= intel_pmu_lbr_tos();
430 int num
= x86_pmu
.lbr_nr
;
432 if (cpuc
->lbr_sel
->config
& LBR_CALL_STACK
)
435 for (i
= 0; i
< num
; i
++) {
436 unsigned long lbr_idx
= (tos
- i
) & mask
;
437 u64 from
, to
, mis
= 0, pred
= 0, in_tx
= 0, abort
= 0;
440 int lbr_flags
= lbr_desc
[lbr_format
];
442 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, from
);
443 rdmsrl(x86_pmu
.lbr_to
+ lbr_idx
, to
);
445 if (lbr_format
== LBR_FORMAT_INFO
) {
448 rdmsrl(MSR_LBR_INFO_0
+ lbr_idx
, info
);
449 mis
= !!(info
& LBR_INFO_MISPRED
);
451 in_tx
= !!(info
& LBR_INFO_IN_TX
);
452 abort
= !!(info
& LBR_INFO_ABORT
);
453 cycles
= (info
& LBR_INFO_CYCLES
);
455 if (lbr_flags
& LBR_EIP_FLAGS
) {
456 mis
= !!(from
& LBR_FROM_FLAG_MISPRED
);
460 if (lbr_flags
& LBR_TSX
) {
461 in_tx
= !!(from
& LBR_FROM_FLAG_IN_TX
);
462 abort
= !!(from
& LBR_FROM_FLAG_ABORT
);
465 from
= (u64
)((((s64
)from
) << skip
) >> skip
);
468 * Some CPUs report duplicated abort records,
469 * with the second entry not having an abort bit set.
470 * Skip them here. This loop runs backwards,
471 * so we need to undo the previous record.
472 * If the abort just happened outside the window
473 * the extra entry cannot be removed.
475 if (abort
&& x86_pmu
.lbr_double_abort
&& out
> 0)
478 cpuc
->lbr_entries
[out
].from
= from
;
479 cpuc
->lbr_entries
[out
].to
= to
;
480 cpuc
->lbr_entries
[out
].mispred
= mis
;
481 cpuc
->lbr_entries
[out
].predicted
= pred
;
482 cpuc
->lbr_entries
[out
].in_tx
= in_tx
;
483 cpuc
->lbr_entries
[out
].abort
= abort
;
484 cpuc
->lbr_entries
[out
].cycles
= cycles
;
485 cpuc
->lbr_entries
[out
].reserved
= 0;
488 cpuc
->lbr_stack
.nr
= out
;
491 void intel_pmu_lbr_read(void)
493 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
495 if (!cpuc
->lbr_users
)
498 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_32
)
499 intel_pmu_lbr_read_32(cpuc
);
501 intel_pmu_lbr_read_64(cpuc
);
503 intel_pmu_lbr_filter(cpuc
);
508 * - in case there is no HW filter
509 * - in case the HW filter has errata or limitations
511 static int intel_pmu_setup_sw_lbr_filter(struct perf_event
*event
)
513 u64 br_type
= event
->attr
.branch_sample_type
;
516 if (br_type
& PERF_SAMPLE_BRANCH_USER
)
519 if (br_type
& PERF_SAMPLE_BRANCH_KERNEL
)
520 mask
|= X86_BR_KERNEL
;
522 /* we ignore BRANCH_HV here */
524 if (br_type
& PERF_SAMPLE_BRANCH_ANY
)
527 if (br_type
& PERF_SAMPLE_BRANCH_ANY_CALL
)
528 mask
|= X86_BR_ANY_CALL
;
530 if (br_type
& PERF_SAMPLE_BRANCH_ANY_RETURN
)
531 mask
|= X86_BR_RET
| X86_BR_IRET
| X86_BR_SYSRET
;
533 if (br_type
& PERF_SAMPLE_BRANCH_IND_CALL
)
534 mask
|= X86_BR_IND_CALL
;
536 if (br_type
& PERF_SAMPLE_BRANCH_ABORT_TX
)
537 mask
|= X86_BR_ABORT
;
539 if (br_type
& PERF_SAMPLE_BRANCH_IN_TX
)
540 mask
|= X86_BR_IN_TX
;
542 if (br_type
& PERF_SAMPLE_BRANCH_NO_TX
)
543 mask
|= X86_BR_NO_TX
;
545 if (br_type
& PERF_SAMPLE_BRANCH_COND
)
548 if (br_type
& PERF_SAMPLE_BRANCH_CALL_STACK
) {
549 if (!x86_pmu_has_lbr_callstack())
551 if (mask
& ~(X86_BR_USER
| X86_BR_KERNEL
))
553 mask
|= X86_BR_CALL
| X86_BR_IND_CALL
| X86_BR_RET
|
557 if (br_type
& PERF_SAMPLE_BRANCH_IND_JUMP
)
558 mask
|= X86_BR_IND_JMP
;
560 if (br_type
& PERF_SAMPLE_BRANCH_CALL
)
561 mask
|= X86_BR_CALL
| X86_BR_ZERO_CALL
;
563 * stash actual user request into reg, it may
564 * be used by fixup code for some CPU
566 event
->hw
.branch_reg
.reg
= mask
;
571 * setup the HW LBR filter
572 * Used only when available, may not be enough to disambiguate
573 * all branches, may need the help of the SW filter
575 static int intel_pmu_setup_hw_lbr_filter(struct perf_event
*event
)
577 struct hw_perf_event_extra
*reg
;
578 u64 br_type
= event
->attr
.branch_sample_type
;
582 for (i
= 0; i
< PERF_SAMPLE_BRANCH_MAX_SHIFT
; i
++) {
583 if (!(br_type
& (1ULL << i
)))
586 v
= x86_pmu
.lbr_sel_map
[i
];
587 if (v
== LBR_NOT_SUPP
)
593 reg
= &event
->hw
.branch_reg
;
594 reg
->idx
= EXTRA_REG_LBR
;
597 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
598 * in suppress mode. So LBR_SELECT should be set to
599 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
601 reg
->config
= mask
^ x86_pmu
.lbr_sel_mask
;
606 int intel_pmu_setup_lbr_filter(struct perf_event
*event
)
617 * setup SW LBR filter
619 ret
= intel_pmu_setup_sw_lbr_filter(event
);
624 * setup HW LBR filter, if any
626 if (x86_pmu
.lbr_sel_map
)
627 ret
= intel_pmu_setup_hw_lbr_filter(event
);
633 * return the type of control flow change at address "from"
634 * intruction is not necessarily a branch (in case of interrupt).
636 * The branch type returned also includes the priv level of the
637 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
639 * If a branch type is unknown OR the instruction cannot be
640 * decoded (e.g., text page not present), then X86_BR_NONE is
643 static int branch_type(unsigned long from
, unsigned long to
, int abort
)
647 int bytes_read
, bytes_left
;
648 int ret
= X86_BR_NONE
;
649 int ext
, to_plm
, from_plm
;
650 u8 buf
[MAX_INSN_SIZE
];
653 to_plm
= kernel_ip(to
) ? X86_BR_KERNEL
: X86_BR_USER
;
654 from_plm
= kernel_ip(from
) ? X86_BR_KERNEL
: X86_BR_USER
;
657 * maybe zero if lbr did not fill up after a reset by the time
658 * we get a PMU interrupt
660 if (from
== 0 || to
== 0)
664 return X86_BR_ABORT
| to_plm
;
666 if (from_plm
== X86_BR_USER
) {
668 * can happen if measuring at the user level only
669 * and we interrupt in a kernel thread, e.g., idle.
674 /* may fail if text not present */
675 bytes_left
= copy_from_user_nmi(buf
, (void __user
*)from
,
677 bytes_read
= MAX_INSN_SIZE
- bytes_left
;
684 * The LBR logs any address in the IP, even if the IP just
685 * faulted. This means userspace can control the from address.
686 * Ensure we don't blindy read any address by validating it is
687 * a known text address.
689 if (kernel_text_address(from
)) {
692 * Assume we can get the maximum possible size
693 * when grabbing kernel data. This is not
694 * _strictly_ true since we could possibly be
695 * executing up next to a memory hole, but
696 * it is very unlikely to be a problem.
698 bytes_read
= MAX_INSN_SIZE
;
705 * decoder needs to know the ABI especially
706 * on 64-bit systems running 32-bit apps
709 is64
= kernel_ip((unsigned long)addr
) || !test_thread_flag(TIF_IA32
);
711 insn_init(&insn
, addr
, bytes_read
, is64
);
712 insn_get_opcode(&insn
);
713 if (!insn
.opcode
.got
)
716 switch (insn
.opcode
.bytes
[0]) {
718 switch (insn
.opcode
.bytes
[1]) {
719 case 0x05: /* syscall */
720 case 0x34: /* sysenter */
721 ret
= X86_BR_SYSCALL
;
723 case 0x07: /* sysret */
724 case 0x35: /* sysexit */
727 case 0x80 ... 0x8f: /* conditional */
734 case 0x70 ... 0x7f: /* conditional */
737 case 0xc2: /* near ret */
738 case 0xc3: /* near ret */
739 case 0xca: /* far ret */
740 case 0xcb: /* far ret */
743 case 0xcf: /* iret */
746 case 0xcc ... 0xce: /* int */
749 case 0xe8: /* call near rel */
750 insn_get_immediate(&insn
);
751 if (insn
.immediate1
.value
== 0) {
752 /* zero length call */
753 ret
= X86_BR_ZERO_CALL
;
756 case 0x9a: /* call far absolute */
759 case 0xe0 ... 0xe3: /* loop jmp */
762 case 0xe9 ... 0xeb: /* jmp */
765 case 0xff: /* call near absolute, call far absolute ind */
766 insn_get_modrm(&insn
);
767 ext
= (insn
.modrm
.bytes
[0] >> 3) & 0x7;
769 case 2: /* near ind call */
770 case 3: /* far ind call */
771 ret
= X86_BR_IND_CALL
;
775 ret
= X86_BR_IND_JMP
;
783 * interrupts, traps, faults (and thus ring transition) may
784 * occur on any instructions. Thus, to classify them correctly,
785 * we need to first look at the from and to priv levels. If they
786 * are different and to is in the kernel, then it indicates
787 * a ring transition. If the from instruction is not a ring
788 * transition instr (syscall, systenter, int), then it means
789 * it was a irq, trap or fault.
791 * we have no way of detecting kernel to kernel faults.
793 if (from_plm
== X86_BR_USER
&& to_plm
== X86_BR_KERNEL
794 && ret
!= X86_BR_SYSCALL
&& ret
!= X86_BR_INT
)
798 * branch priv level determined by target as
799 * is done by HW when LBR_SELECT is implemented
801 if (ret
!= X86_BR_NONE
)
808 * implement actual branch filter based on user demand.
809 * Hardware may not exactly satisfy that request, thus
810 * we need to inspect opcodes. Mismatched branches are
811 * discarded. Therefore, the number of branches returned
812 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
815 intel_pmu_lbr_filter(struct cpu_hw_events
*cpuc
)
818 int br_sel
= cpuc
->br_sel
;
820 bool compress
= false;
822 /* if sampling all branches, then nothing to filter */
823 if ((br_sel
& X86_BR_ALL
) == X86_BR_ALL
)
826 for (i
= 0; i
< cpuc
->lbr_stack
.nr
; i
++) {
828 from
= cpuc
->lbr_entries
[i
].from
;
829 to
= cpuc
->lbr_entries
[i
].to
;
831 type
= branch_type(from
, to
, cpuc
->lbr_entries
[i
].abort
);
832 if (type
!= X86_BR_NONE
&& (br_sel
& X86_BR_ANYTX
)) {
833 if (cpuc
->lbr_entries
[i
].in_tx
)
834 type
|= X86_BR_IN_TX
;
836 type
|= X86_BR_NO_TX
;
839 /* if type does not correspond, then discard */
840 if (type
== X86_BR_NONE
|| (br_sel
& type
) != type
) {
841 cpuc
->lbr_entries
[i
].from
= 0;
849 /* remove all entries with from=0 */
850 for (i
= 0; i
< cpuc
->lbr_stack
.nr
; ) {
851 if (!cpuc
->lbr_entries
[i
].from
) {
853 while (++j
< cpuc
->lbr_stack
.nr
)
854 cpuc
->lbr_entries
[j
-1] = cpuc
->lbr_entries
[j
];
855 cpuc
->lbr_stack
.nr
--;
856 if (!cpuc
->lbr_entries
[i
].from
)
864 * Map interface branch filters onto LBR filters
866 static const int nhm_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
867 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
868 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
869 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
870 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
871 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_REL_JMP
872 | LBR_IND_JMP
| LBR_FAR
,
874 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
876 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] =
877 LBR_REL_CALL
| LBR_IND_CALL
| LBR_REL_JMP
| LBR_IND_JMP
| LBR_FAR
,
879 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
881 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
| LBR_IND_JMP
,
882 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
883 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
] = LBR_IND_JMP
,
886 static const int snb_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
887 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
888 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
889 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
890 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
891 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_FAR
,
892 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
894 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
,
895 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
896 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
] = LBR_IND_JMP
,
897 [PERF_SAMPLE_BRANCH_CALL_SHIFT
] = LBR_REL_CALL
,
900 static const int hsw_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
901 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
902 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
903 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
904 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
905 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_FAR
,
906 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
908 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
,
909 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
910 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
911 | LBR_RETURN
| LBR_CALL_STACK
,
912 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
] = LBR_IND_JMP
,
913 [PERF_SAMPLE_BRANCH_CALL_SHIFT
] = LBR_REL_CALL
,
917 void __init
intel_pmu_lbr_init_core(void)
920 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
921 x86_pmu
.lbr_from
= MSR_LBR_CORE_FROM
;
922 x86_pmu
.lbr_to
= MSR_LBR_CORE_TO
;
925 * SW branch filter usage:
926 * - compensate for lack of HW filter
928 pr_cont("4-deep LBR, ");
931 /* nehalem/westmere */
932 void __init
intel_pmu_lbr_init_nhm(void)
935 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
936 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
937 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
939 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
940 x86_pmu
.lbr_sel_map
= nhm_lbr_sel_map
;
943 * SW branch filter usage:
944 * - workaround LBR_SEL errata (see above)
945 * - support syscall, sysret capture.
946 * That requires LBR_FAR but that means far
947 * jmp need to be filtered out
949 pr_cont("16-deep LBR, ");
953 void __init
intel_pmu_lbr_init_snb(void)
956 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
957 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
958 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
960 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
961 x86_pmu
.lbr_sel_map
= snb_lbr_sel_map
;
964 * SW branch filter usage:
965 * - support syscall, sysret capture.
966 * That requires LBR_FAR but that means far
967 * jmp need to be filtered out
969 pr_cont("16-deep LBR, ");
973 void intel_pmu_lbr_init_hsw(void)
976 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
977 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
978 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
980 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
981 x86_pmu
.lbr_sel_map
= hsw_lbr_sel_map
;
983 pr_cont("16-deep LBR, ");
987 __init
void intel_pmu_lbr_init_skl(void)
990 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
991 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
992 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
994 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
995 x86_pmu
.lbr_sel_map
= hsw_lbr_sel_map
;
998 * SW branch filter usage:
999 * - support syscall, sysret capture.
1000 * That requires LBR_FAR but that means far
1001 * jmp need to be filtered out
1003 pr_cont("32-deep LBR, ");
1007 void __init
intel_pmu_lbr_init_atom(void)
1010 * only models starting at stepping 10 seems
1011 * to have an operational LBR which can freeze
1014 if (boot_cpu_data
.x86_model
== 28
1015 && boot_cpu_data
.x86_mask
< 10) {
1016 pr_cont("LBR disabled due to erratum");
1021 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1022 x86_pmu
.lbr_from
= MSR_LBR_CORE_FROM
;
1023 x86_pmu
.lbr_to
= MSR_LBR_CORE_TO
;
1026 * SW branch filter usage:
1027 * - compensate for lack of HW filter
1029 pr_cont("8-deep LBR, ");