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[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kernel / cpu / perf_event_intel_uncore.c
1 #include "perf_event_intel_uncore.h"
2
3 static struct intel_uncore_type *empty_uncore[] = { NULL, };
4 static struct intel_uncore_type **msr_uncores = empty_uncore;
5 static struct intel_uncore_type **pci_uncores = empty_uncore;
6 /* pci bus to socket mapping */
7 static int pcibus_to_physid[256] = { [0 ... 255] = -1, };
8
9 static struct pci_dev *extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
10
11 static DEFINE_RAW_SPINLOCK(uncore_box_lock);
12
13 /* mask of cpus that collect uncore events */
14 static cpumask_t uncore_cpu_mask;
15
16 /* constraint for the fixed counter */
17 static struct event_constraint constraint_fixed =
18 EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
19 static struct event_constraint constraint_empty =
20 EVENT_CONSTRAINT(0, 0, 0);
21
22 #define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
23 ((1ULL << (n)) - 1)))
24
25 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
26 DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
27 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
28 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
29 DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
30 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
31 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
32 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
33 DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
34 DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
35 DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
36 DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
37 DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
38 DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
39 DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8");
40 DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
41 DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47");
42 DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
43 DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22");
44 DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
45 DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60");
46 DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
47 DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
48 DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
49 DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31");
50 DEFINE_UNCORE_FORMAT_ATTR(match_rds, match_rds, "config1:48-51");
51 DEFINE_UNCORE_FORMAT_ATTR(match_rnid30, match_rnid30, "config1:32-35");
52 DEFINE_UNCORE_FORMAT_ATTR(match_rnid4, match_rnid4, "config1:31");
53 DEFINE_UNCORE_FORMAT_ATTR(match_dnid, match_dnid, "config1:13-17");
54 DEFINE_UNCORE_FORMAT_ATTR(match_mc, match_mc, "config1:9-12");
55 DEFINE_UNCORE_FORMAT_ATTR(match_opc, match_opc, "config1:5-8");
56 DEFINE_UNCORE_FORMAT_ATTR(match_vnw, match_vnw, "config1:3-4");
57 DEFINE_UNCORE_FORMAT_ATTR(match0, match0, "config1:0-31");
58 DEFINE_UNCORE_FORMAT_ATTR(match1, match1, "config1:32-63");
59 DEFINE_UNCORE_FORMAT_ATTR(mask_rds, mask_rds, "config2:48-51");
60 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid30, mask_rnid30, "config2:32-35");
61 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid4, mask_rnid4, "config2:31");
62 DEFINE_UNCORE_FORMAT_ATTR(mask_dnid, mask_dnid, "config2:13-17");
63 DEFINE_UNCORE_FORMAT_ATTR(mask_mc, mask_mc, "config2:9-12");
64 DEFINE_UNCORE_FORMAT_ATTR(mask_opc, mask_opc, "config2:5-8");
65 DEFINE_UNCORE_FORMAT_ATTR(mask_vnw, mask_vnw, "config2:3-4");
66 DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31");
67 DEFINE_UNCORE_FORMAT_ATTR(mask1, mask1, "config2:32-63");
68
69 static void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
70 static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
71 static void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
72 static void uncore_pmu_event_read(struct perf_event *event);
73
74 static struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
75 {
76 return container_of(event->pmu, struct intel_uncore_pmu, pmu);
77 }
78
79 static struct intel_uncore_box *
80 uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
81 {
82 struct intel_uncore_box *box;
83
84 box = *per_cpu_ptr(pmu->box, cpu);
85 if (box)
86 return box;
87
88 raw_spin_lock(&uncore_box_lock);
89 list_for_each_entry(box, &pmu->box_list, list) {
90 if (box->phys_id == topology_physical_package_id(cpu)) {
91 atomic_inc(&box->refcnt);
92 *per_cpu_ptr(pmu->box, cpu) = box;
93 break;
94 }
95 }
96 raw_spin_unlock(&uncore_box_lock);
97
98 return *per_cpu_ptr(pmu->box, cpu);
99 }
100
101 static struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
102 {
103 /*
104 * perf core schedules event on the basis of cpu, uncore events are
105 * collected by one of the cpus inside a physical package.
106 */
107 return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
108 }
109
110 static u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
111 {
112 u64 count;
113
114 rdmsrl(event->hw.event_base, count);
115
116 return count;
117 }
118
119 /*
120 * generic get constraint function for shared match/mask registers.
121 */
122 static struct event_constraint *
123 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
124 {
125 struct intel_uncore_extra_reg *er;
126 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
127 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
128 unsigned long flags;
129 bool ok = false;
130
131 /*
132 * reg->alloc can be set due to existing state, so for fake box we
133 * need to ignore this, otherwise we might fail to allocate proper
134 * fake state for this extra reg constraint.
135 */
136 if (reg1->idx == EXTRA_REG_NONE ||
137 (!uncore_box_is_fake(box) && reg1->alloc))
138 return NULL;
139
140 er = &box->shared_regs[reg1->idx];
141 raw_spin_lock_irqsave(&er->lock, flags);
142 if (!atomic_read(&er->ref) ||
143 (er->config1 == reg1->config && er->config2 == reg2->config)) {
144 atomic_inc(&er->ref);
145 er->config1 = reg1->config;
146 er->config2 = reg2->config;
147 ok = true;
148 }
149 raw_spin_unlock_irqrestore(&er->lock, flags);
150
151 if (ok) {
152 if (!uncore_box_is_fake(box))
153 reg1->alloc = 1;
154 return NULL;
155 }
156
157 return &constraint_empty;
158 }
159
160 static void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
161 {
162 struct intel_uncore_extra_reg *er;
163 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
164
165 /*
166 * Only put constraint if extra reg was actually allocated. Also
167 * takes care of event which do not use an extra shared reg.
168 *
169 * Also, if this is a fake box we shouldn't touch any event state
170 * (reg->alloc) and we don't care about leaving inconsistent box
171 * state either since it will be thrown out.
172 */
173 if (uncore_box_is_fake(box) || !reg1->alloc)
174 return;
175
176 er = &box->shared_regs[reg1->idx];
177 atomic_dec(&er->ref);
178 reg1->alloc = 0;
179 }
180
181 static u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
182 {
183 struct intel_uncore_extra_reg *er;
184 unsigned long flags;
185 u64 config;
186
187 er = &box->shared_regs[idx];
188
189 raw_spin_lock_irqsave(&er->lock, flags);
190 config = er->config;
191 raw_spin_unlock_irqrestore(&er->lock, flags);
192
193 return config;
194 }
195
196 /* Sandy Bridge-EP uncore support */
197 static struct intel_uncore_type snbep_uncore_cbox;
198 static struct intel_uncore_type snbep_uncore_pcu;
199
200 static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
201 {
202 struct pci_dev *pdev = box->pci_dev;
203 int box_ctl = uncore_pci_box_ctl(box);
204 u32 config = 0;
205
206 if (!pci_read_config_dword(pdev, box_ctl, &config)) {
207 config |= SNBEP_PMON_BOX_CTL_FRZ;
208 pci_write_config_dword(pdev, box_ctl, config);
209 }
210 }
211
212 static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
213 {
214 struct pci_dev *pdev = box->pci_dev;
215 int box_ctl = uncore_pci_box_ctl(box);
216 u32 config = 0;
217
218 if (!pci_read_config_dword(pdev, box_ctl, &config)) {
219 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
220 pci_write_config_dword(pdev, box_ctl, config);
221 }
222 }
223
224 static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event)
225 {
226 struct pci_dev *pdev = box->pci_dev;
227 struct hw_perf_event *hwc = &event->hw;
228
229 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
230 }
231
232 static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event)
233 {
234 struct pci_dev *pdev = box->pci_dev;
235 struct hw_perf_event *hwc = &event->hw;
236
237 pci_write_config_dword(pdev, hwc->config_base, hwc->config);
238 }
239
240 static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event)
241 {
242 struct pci_dev *pdev = box->pci_dev;
243 struct hw_perf_event *hwc = &event->hw;
244 u64 count = 0;
245
246 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
247 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
248
249 return count;
250 }
251
252 static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
253 {
254 struct pci_dev *pdev = box->pci_dev;
255
256 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, SNBEP_PMON_BOX_CTL_INT);
257 }
258
259 static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
260 {
261 u64 config;
262 unsigned msr;
263
264 msr = uncore_msr_box_ctl(box);
265 if (msr) {
266 rdmsrl(msr, config);
267 config |= SNBEP_PMON_BOX_CTL_FRZ;
268 wrmsrl(msr, config);
269 }
270 }
271
272 static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
273 {
274 u64 config;
275 unsigned msr;
276
277 msr = uncore_msr_box_ctl(box);
278 if (msr) {
279 rdmsrl(msr, config);
280 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
281 wrmsrl(msr, config);
282 }
283 }
284
285 static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
286 {
287 struct hw_perf_event *hwc = &event->hw;
288 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
289
290 if (reg1->idx != EXTRA_REG_NONE)
291 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0));
292
293 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
294 }
295
296 static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
297 struct perf_event *event)
298 {
299 struct hw_perf_event *hwc = &event->hw;
300
301 wrmsrl(hwc->config_base, hwc->config);
302 }
303
304 static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
305 {
306 unsigned msr = uncore_msr_box_ctl(box);
307
308 if (msr)
309 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
310 }
311
312 static struct attribute *snbep_uncore_formats_attr[] = {
313 &format_attr_event.attr,
314 &format_attr_umask.attr,
315 &format_attr_edge.attr,
316 &format_attr_inv.attr,
317 &format_attr_thresh8.attr,
318 NULL,
319 };
320
321 static struct attribute *snbep_uncore_ubox_formats_attr[] = {
322 &format_attr_event.attr,
323 &format_attr_umask.attr,
324 &format_attr_edge.attr,
325 &format_attr_inv.attr,
326 &format_attr_thresh5.attr,
327 NULL,
328 };
329
330 static struct attribute *snbep_uncore_cbox_formats_attr[] = {
331 &format_attr_event.attr,
332 &format_attr_umask.attr,
333 &format_attr_edge.attr,
334 &format_attr_tid_en.attr,
335 &format_attr_inv.attr,
336 &format_attr_thresh8.attr,
337 &format_attr_filter_tid.attr,
338 &format_attr_filter_nid.attr,
339 &format_attr_filter_state.attr,
340 &format_attr_filter_opc.attr,
341 NULL,
342 };
343
344 static struct attribute *snbep_uncore_pcu_formats_attr[] = {
345 &format_attr_event_ext.attr,
346 &format_attr_occ_sel.attr,
347 &format_attr_edge.attr,
348 &format_attr_inv.attr,
349 &format_attr_thresh5.attr,
350 &format_attr_occ_invert.attr,
351 &format_attr_occ_edge.attr,
352 &format_attr_filter_band0.attr,
353 &format_attr_filter_band1.attr,
354 &format_attr_filter_band2.attr,
355 &format_attr_filter_band3.attr,
356 NULL,
357 };
358
359 static struct attribute *snbep_uncore_qpi_formats_attr[] = {
360 &format_attr_event_ext.attr,
361 &format_attr_umask.attr,
362 &format_attr_edge.attr,
363 &format_attr_inv.attr,
364 &format_attr_thresh8.attr,
365 &format_attr_match_rds.attr,
366 &format_attr_match_rnid30.attr,
367 &format_attr_match_rnid4.attr,
368 &format_attr_match_dnid.attr,
369 &format_attr_match_mc.attr,
370 &format_attr_match_opc.attr,
371 &format_attr_match_vnw.attr,
372 &format_attr_match0.attr,
373 &format_attr_match1.attr,
374 &format_attr_mask_rds.attr,
375 &format_attr_mask_rnid30.attr,
376 &format_attr_mask_rnid4.attr,
377 &format_attr_mask_dnid.attr,
378 &format_attr_mask_mc.attr,
379 &format_attr_mask_opc.attr,
380 &format_attr_mask_vnw.attr,
381 &format_attr_mask0.attr,
382 &format_attr_mask1.attr,
383 NULL,
384 };
385
386 static struct uncore_event_desc snbep_uncore_imc_events[] = {
387 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
388 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
389 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
390 { /* end: all zeroes */ },
391 };
392
393 static struct uncore_event_desc snbep_uncore_qpi_events[] = {
394 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"),
395 INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"),
396 INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x102,umask=0x08"),
397 INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x103,umask=0x04"),
398 { /* end: all zeroes */ },
399 };
400
401 static struct attribute_group snbep_uncore_format_group = {
402 .name = "format",
403 .attrs = snbep_uncore_formats_attr,
404 };
405
406 static struct attribute_group snbep_uncore_ubox_format_group = {
407 .name = "format",
408 .attrs = snbep_uncore_ubox_formats_attr,
409 };
410
411 static struct attribute_group snbep_uncore_cbox_format_group = {
412 .name = "format",
413 .attrs = snbep_uncore_cbox_formats_attr,
414 };
415
416 static struct attribute_group snbep_uncore_pcu_format_group = {
417 .name = "format",
418 .attrs = snbep_uncore_pcu_formats_attr,
419 };
420
421 static struct attribute_group snbep_uncore_qpi_format_group = {
422 .name = "format",
423 .attrs = snbep_uncore_qpi_formats_attr,
424 };
425
426 #define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
427 .init_box = snbep_uncore_msr_init_box, \
428 .disable_box = snbep_uncore_msr_disable_box, \
429 .enable_box = snbep_uncore_msr_enable_box, \
430 .disable_event = snbep_uncore_msr_disable_event, \
431 .enable_event = snbep_uncore_msr_enable_event, \
432 .read_counter = uncore_msr_read_counter
433
434 static struct intel_uncore_ops snbep_uncore_msr_ops = {
435 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
436 };
437
438 #define SNBEP_UNCORE_PCI_OPS_COMMON_INIT() \
439 .init_box = snbep_uncore_pci_init_box, \
440 .disable_box = snbep_uncore_pci_disable_box, \
441 .enable_box = snbep_uncore_pci_enable_box, \
442 .disable_event = snbep_uncore_pci_disable_event, \
443 .read_counter = snbep_uncore_pci_read_counter
444
445 static struct intel_uncore_ops snbep_uncore_pci_ops = {
446 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
447 .enable_event = snbep_uncore_pci_enable_event, \
448 };
449
450 static struct event_constraint snbep_uncore_cbox_constraints[] = {
451 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
452 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
453 UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
454 UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
455 UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
456 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
457 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
458 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
459 UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
460 UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
461 UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
462 UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
463 UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
464 EVENT_CONSTRAINT_OVERLAP(0x1f, 0xe, 0xff),
465 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
466 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
467 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
468 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
469 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
470 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
471 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
472 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
473 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
474 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
475 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
476 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
477 EVENT_CONSTRAINT_END
478 };
479
480 static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
481 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
482 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
483 UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
484 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
485 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
486 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
487 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
488 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
489 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
490 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
491 EVENT_CONSTRAINT_END
492 };
493
494 static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
495 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
496 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
497 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
498 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
499 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
500 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
501 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
502 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
503 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
504 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
505 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
506 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
507 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
508 UNCORE_EVENT_CONSTRAINT(0x2a, 0x3),
509 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
510 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
511 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
512 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
513 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
514 UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
515 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
516 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
517 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
518 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
519 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
520 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
521 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
522 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
523 EVENT_CONSTRAINT_END
524 };
525
526 static struct intel_uncore_type snbep_uncore_ubox = {
527 .name = "ubox",
528 .num_counters = 2,
529 .num_boxes = 1,
530 .perf_ctr_bits = 44,
531 .fixed_ctr_bits = 48,
532 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
533 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
534 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
535 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
536 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
537 .ops = &snbep_uncore_msr_ops,
538 .format_group = &snbep_uncore_ubox_format_group,
539 };
540
541 static struct extra_reg snbep_uncore_cbox_extra_regs[] = {
542 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
543 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
544 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
545 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6),
546 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
547 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6),
548 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
549 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6),
550 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
551 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
552 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
553 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xc),
554 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xc),
555 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2),
556 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2),
557 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2),
558 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2),
559 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8),
560 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8),
561 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xc),
562 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xc),
563 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2),
564 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2),
565 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2),
566 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2),
567 EVENT_EXTRA_END
568 };
569
570 static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
571 {
572 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
573 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
574 int i;
575
576 if (uncore_box_is_fake(box))
577 return;
578
579 for (i = 0; i < 5; i++) {
580 if (reg1->alloc & (0x1 << i))
581 atomic_sub(1 << (i * 6), &er->ref);
582 }
583 reg1->alloc = 0;
584 }
585
586 static struct event_constraint *
587 __snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event,
588 u64 (*cbox_filter_mask)(int fields))
589 {
590 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
591 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
592 int i, alloc = 0;
593 unsigned long flags;
594 u64 mask;
595
596 if (reg1->idx == EXTRA_REG_NONE)
597 return NULL;
598
599 raw_spin_lock_irqsave(&er->lock, flags);
600 for (i = 0; i < 5; i++) {
601 if (!(reg1->idx & (0x1 << i)))
602 continue;
603 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
604 continue;
605
606 mask = cbox_filter_mask(0x1 << i);
607 if (!__BITS_VALUE(atomic_read(&er->ref), i, 6) ||
608 !((reg1->config ^ er->config) & mask)) {
609 atomic_add(1 << (i * 6), &er->ref);
610 er->config &= ~mask;
611 er->config |= reg1->config & mask;
612 alloc |= (0x1 << i);
613 } else {
614 break;
615 }
616 }
617 raw_spin_unlock_irqrestore(&er->lock, flags);
618 if (i < 5)
619 goto fail;
620
621 if (!uncore_box_is_fake(box))
622 reg1->alloc |= alloc;
623
624 return NULL;
625 fail:
626 for (; i >= 0; i--) {
627 if (alloc & (0x1 << i))
628 atomic_sub(1 << (i * 6), &er->ref);
629 }
630 return &constraint_empty;
631 }
632
633 static u64 snbep_cbox_filter_mask(int fields)
634 {
635 u64 mask = 0;
636
637 if (fields & 0x1)
638 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID;
639 if (fields & 0x2)
640 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID;
641 if (fields & 0x4)
642 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE;
643 if (fields & 0x8)
644 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC;
645
646 return mask;
647 }
648
649 static struct event_constraint *
650 snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
651 {
652 return __snbep_cbox_get_constraint(box, event, snbep_cbox_filter_mask);
653 }
654
655 static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
656 {
657 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
658 struct extra_reg *er;
659 int idx = 0;
660
661 for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) {
662 if (er->event != (event->hw.config & er->config_mask))
663 continue;
664 idx |= er->idx;
665 }
666
667 if (idx) {
668 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
669 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
670 reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx);
671 reg1->idx = idx;
672 }
673 return 0;
674 }
675
676 static struct intel_uncore_ops snbep_uncore_cbox_ops = {
677 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
678 .hw_config = snbep_cbox_hw_config,
679 .get_constraint = snbep_cbox_get_constraint,
680 .put_constraint = snbep_cbox_put_constraint,
681 };
682
683 static struct intel_uncore_type snbep_uncore_cbox = {
684 .name = "cbox",
685 .num_counters = 4,
686 .num_boxes = 8,
687 .perf_ctr_bits = 44,
688 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
689 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
690 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
691 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
692 .msr_offset = SNBEP_CBO_MSR_OFFSET,
693 .num_shared_regs = 1,
694 .constraints = snbep_uncore_cbox_constraints,
695 .ops = &snbep_uncore_cbox_ops,
696 .format_group = &snbep_uncore_cbox_format_group,
697 };
698
699 static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify)
700 {
701 struct hw_perf_event *hwc = &event->hw;
702 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
703 u64 config = reg1->config;
704
705 if (new_idx > reg1->idx)
706 config <<= 8 * (new_idx - reg1->idx);
707 else
708 config >>= 8 * (reg1->idx - new_idx);
709
710 if (modify) {
711 hwc->config += new_idx - reg1->idx;
712 reg1->config = config;
713 reg1->idx = new_idx;
714 }
715 return config;
716 }
717
718 static struct event_constraint *
719 snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
720 {
721 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
722 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
723 unsigned long flags;
724 int idx = reg1->idx;
725 u64 mask, config1 = reg1->config;
726 bool ok = false;
727
728 if (reg1->idx == EXTRA_REG_NONE ||
729 (!uncore_box_is_fake(box) && reg1->alloc))
730 return NULL;
731 again:
732 mask = 0xffULL << (idx * 8);
733 raw_spin_lock_irqsave(&er->lock, flags);
734 if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) ||
735 !((config1 ^ er->config) & mask)) {
736 atomic_add(1 << (idx * 8), &er->ref);
737 er->config &= ~mask;
738 er->config |= config1 & mask;
739 ok = true;
740 }
741 raw_spin_unlock_irqrestore(&er->lock, flags);
742
743 if (!ok) {
744 idx = (idx + 1) % 4;
745 if (idx != reg1->idx) {
746 config1 = snbep_pcu_alter_er(event, idx, false);
747 goto again;
748 }
749 return &constraint_empty;
750 }
751
752 if (!uncore_box_is_fake(box)) {
753 if (idx != reg1->idx)
754 snbep_pcu_alter_er(event, idx, true);
755 reg1->alloc = 1;
756 }
757 return NULL;
758 }
759
760 static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
761 {
762 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
763 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
764
765 if (uncore_box_is_fake(box) || !reg1->alloc)
766 return;
767
768 atomic_sub(1 << (reg1->idx * 8), &er->ref);
769 reg1->alloc = 0;
770 }
771
772 static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
773 {
774 struct hw_perf_event *hwc = &event->hw;
775 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
776 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
777
778 if (ev_sel >= 0xb && ev_sel <= 0xe) {
779 reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
780 reg1->idx = ev_sel - 0xb;
781 reg1->config = event->attr.config1 & (0xff << reg1->idx);
782 }
783 return 0;
784 }
785
786 static struct intel_uncore_ops snbep_uncore_pcu_ops = {
787 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
788 .hw_config = snbep_pcu_hw_config,
789 .get_constraint = snbep_pcu_get_constraint,
790 .put_constraint = snbep_pcu_put_constraint,
791 };
792
793 static struct intel_uncore_type snbep_uncore_pcu = {
794 .name = "pcu",
795 .num_counters = 4,
796 .num_boxes = 1,
797 .perf_ctr_bits = 48,
798 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
799 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
800 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
801 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
802 .num_shared_regs = 1,
803 .ops = &snbep_uncore_pcu_ops,
804 .format_group = &snbep_uncore_pcu_format_group,
805 };
806
807 static struct intel_uncore_type *snbep_msr_uncores[] = {
808 &snbep_uncore_ubox,
809 &snbep_uncore_cbox,
810 &snbep_uncore_pcu,
811 NULL,
812 };
813
814 enum {
815 SNBEP_PCI_QPI_PORT0_FILTER,
816 SNBEP_PCI_QPI_PORT1_FILTER,
817 };
818
819 static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event)
820 {
821 struct hw_perf_event *hwc = &event->hw;
822 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
823 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
824
825 if ((hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK) == 0x38) {
826 reg1->idx = 0;
827 reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0;
828 reg1->config = event->attr.config1;
829 reg2->reg = SNBEP_Q_Py_PCI_PMON_PKT_MASK0;
830 reg2->config = event->attr.config2;
831 }
832 return 0;
833 }
834
835 static void snbep_qpi_enable_event(struct intel_uncore_box *box, struct perf_event *event)
836 {
837 struct pci_dev *pdev = box->pci_dev;
838 struct hw_perf_event *hwc = &event->hw;
839 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
840 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
841
842 if (reg1->idx != EXTRA_REG_NONE) {
843 int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER;
844 struct pci_dev *filter_pdev = extra_pci_dev[box->phys_id][idx];
845 WARN_ON_ONCE(!filter_pdev);
846 if (filter_pdev) {
847 pci_write_config_dword(filter_pdev, reg1->reg,
848 (u32)reg1->config);
849 pci_write_config_dword(filter_pdev, reg1->reg + 4,
850 (u32)(reg1->config >> 32));
851 pci_write_config_dword(filter_pdev, reg2->reg,
852 (u32)reg2->config);
853 pci_write_config_dword(filter_pdev, reg2->reg + 4,
854 (u32)(reg2->config >> 32));
855 }
856 }
857
858 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
859 }
860
861 static struct intel_uncore_ops snbep_uncore_qpi_ops = {
862 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
863 .enable_event = snbep_qpi_enable_event,
864 .hw_config = snbep_qpi_hw_config,
865 .get_constraint = uncore_get_constraint,
866 .put_constraint = uncore_put_constraint,
867 };
868
869 #define SNBEP_UNCORE_PCI_COMMON_INIT() \
870 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
871 .event_ctl = SNBEP_PCI_PMON_CTL0, \
872 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
873 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
874 .ops = &snbep_uncore_pci_ops, \
875 .format_group = &snbep_uncore_format_group
876
877 static struct intel_uncore_type snbep_uncore_ha = {
878 .name = "ha",
879 .num_counters = 4,
880 .num_boxes = 1,
881 .perf_ctr_bits = 48,
882 SNBEP_UNCORE_PCI_COMMON_INIT(),
883 };
884
885 static struct intel_uncore_type snbep_uncore_imc = {
886 .name = "imc",
887 .num_counters = 4,
888 .num_boxes = 4,
889 .perf_ctr_bits = 48,
890 .fixed_ctr_bits = 48,
891 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
892 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
893 .event_descs = snbep_uncore_imc_events,
894 SNBEP_UNCORE_PCI_COMMON_INIT(),
895 };
896
897 static struct intel_uncore_type snbep_uncore_qpi = {
898 .name = "qpi",
899 .num_counters = 4,
900 .num_boxes = 2,
901 .perf_ctr_bits = 48,
902 .perf_ctr = SNBEP_PCI_PMON_CTR0,
903 .event_ctl = SNBEP_PCI_PMON_CTL0,
904 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
905 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
906 .num_shared_regs = 1,
907 .ops = &snbep_uncore_qpi_ops,
908 .event_descs = snbep_uncore_qpi_events,
909 .format_group = &snbep_uncore_qpi_format_group,
910 };
911
912
913 static struct intel_uncore_type snbep_uncore_r2pcie = {
914 .name = "r2pcie",
915 .num_counters = 4,
916 .num_boxes = 1,
917 .perf_ctr_bits = 44,
918 .constraints = snbep_uncore_r2pcie_constraints,
919 SNBEP_UNCORE_PCI_COMMON_INIT(),
920 };
921
922 static struct intel_uncore_type snbep_uncore_r3qpi = {
923 .name = "r3qpi",
924 .num_counters = 3,
925 .num_boxes = 2,
926 .perf_ctr_bits = 44,
927 .constraints = snbep_uncore_r3qpi_constraints,
928 SNBEP_UNCORE_PCI_COMMON_INIT(),
929 };
930
931 enum {
932 SNBEP_PCI_UNCORE_HA,
933 SNBEP_PCI_UNCORE_IMC,
934 SNBEP_PCI_UNCORE_QPI,
935 SNBEP_PCI_UNCORE_R2PCIE,
936 SNBEP_PCI_UNCORE_R3QPI,
937 };
938
939 static struct intel_uncore_type *snbep_pci_uncores[] = {
940 [SNBEP_PCI_UNCORE_HA] = &snbep_uncore_ha,
941 [SNBEP_PCI_UNCORE_IMC] = &snbep_uncore_imc,
942 [SNBEP_PCI_UNCORE_QPI] = &snbep_uncore_qpi,
943 [SNBEP_PCI_UNCORE_R2PCIE] = &snbep_uncore_r2pcie,
944 [SNBEP_PCI_UNCORE_R3QPI] = &snbep_uncore_r3qpi,
945 NULL,
946 };
947
948 static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = {
949 { /* Home Agent */
950 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
951 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_HA, 0),
952 },
953 { /* MC Channel 0 */
954 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
955 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 0),
956 },
957 { /* MC Channel 1 */
958 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
959 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 1),
960 },
961 { /* MC Channel 2 */
962 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
963 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 2),
964 },
965 { /* MC Channel 3 */
966 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
967 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 3),
968 },
969 { /* QPI Port 0 */
970 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
971 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 0),
972 },
973 { /* QPI Port 1 */
974 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
975 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 1),
976 },
977 { /* R2PCIe */
978 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
979 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R2PCIE, 0),
980 },
981 { /* R3QPI Link 0 */
982 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
983 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 0),
984 },
985 { /* R3QPI Link 1 */
986 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
987 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 1),
988 },
989 { /* QPI Port 0 filter */
990 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c86),
991 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
992 SNBEP_PCI_QPI_PORT0_FILTER),
993 },
994 { /* QPI Port 0 filter */
995 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c96),
996 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
997 SNBEP_PCI_QPI_PORT1_FILTER),
998 },
999 { /* end: all zeroes */ }
1000 };
1001
1002 static struct pci_driver snbep_uncore_pci_driver = {
1003 .name = "snbep_uncore",
1004 .id_table = snbep_uncore_pci_ids,
1005 };
1006
1007 /*
1008 * build pci bus to socket mapping
1009 */
1010 static int snbep_pci2phy_map_init(int devid)
1011 {
1012 struct pci_dev *ubox_dev = NULL;
1013 int i, bus, nodeid;
1014 int err = 0;
1015 u32 config = 0;
1016
1017 while (1) {
1018 /* find the UBOX device */
1019 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev);
1020 if (!ubox_dev)
1021 break;
1022 bus = ubox_dev->bus->number;
1023 /* get the Node ID of the local register */
1024 err = pci_read_config_dword(ubox_dev, 0x40, &config);
1025 if (err)
1026 break;
1027 nodeid = config;
1028 /* get the Node ID mapping */
1029 err = pci_read_config_dword(ubox_dev, 0x54, &config);
1030 if (err)
1031 break;
1032 /*
1033 * every three bits in the Node ID mapping register maps
1034 * to a particular node.
1035 */
1036 for (i = 0; i < 8; i++) {
1037 if (nodeid == ((config >> (3 * i)) & 0x7)) {
1038 pcibus_to_physid[bus] = i;
1039 break;
1040 }
1041 }
1042 }
1043
1044 if (!err) {
1045 /*
1046 * For PCI bus with no UBOX device, find the next bus
1047 * that has UBOX device and use its mapping.
1048 */
1049 i = -1;
1050 for (bus = 255; bus >= 0; bus--) {
1051 if (pcibus_to_physid[bus] >= 0)
1052 i = pcibus_to_physid[bus];
1053 else
1054 pcibus_to_physid[bus] = i;
1055 }
1056 }
1057
1058 if (ubox_dev)
1059 pci_dev_put(ubox_dev);
1060
1061 return err ? pcibios_err_to_errno(err) : 0;
1062 }
1063 /* end of Sandy Bridge-EP uncore support */
1064
1065 /* IvyTown uncore support */
1066 static void ivt_uncore_msr_init_box(struct intel_uncore_box *box)
1067 {
1068 unsigned msr = uncore_msr_box_ctl(box);
1069 if (msr)
1070 wrmsrl(msr, IVT_PMON_BOX_CTL_INT);
1071 }
1072
1073 static void ivt_uncore_pci_init_box(struct intel_uncore_box *box)
1074 {
1075 struct pci_dev *pdev = box->pci_dev;
1076
1077 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, IVT_PMON_BOX_CTL_INT);
1078 }
1079
1080 #define IVT_UNCORE_MSR_OPS_COMMON_INIT() \
1081 .init_box = ivt_uncore_msr_init_box, \
1082 .disable_box = snbep_uncore_msr_disable_box, \
1083 .enable_box = snbep_uncore_msr_enable_box, \
1084 .disable_event = snbep_uncore_msr_disable_event, \
1085 .enable_event = snbep_uncore_msr_enable_event, \
1086 .read_counter = uncore_msr_read_counter
1087
1088 static struct intel_uncore_ops ivt_uncore_msr_ops = {
1089 IVT_UNCORE_MSR_OPS_COMMON_INIT(),
1090 };
1091
1092 static struct intel_uncore_ops ivt_uncore_pci_ops = {
1093 .init_box = ivt_uncore_pci_init_box,
1094 .disable_box = snbep_uncore_pci_disable_box,
1095 .enable_box = snbep_uncore_pci_enable_box,
1096 .disable_event = snbep_uncore_pci_disable_event,
1097 .enable_event = snbep_uncore_pci_enable_event,
1098 .read_counter = snbep_uncore_pci_read_counter,
1099 };
1100
1101 #define IVT_UNCORE_PCI_COMMON_INIT() \
1102 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
1103 .event_ctl = SNBEP_PCI_PMON_CTL0, \
1104 .event_mask = IVT_PMON_RAW_EVENT_MASK, \
1105 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
1106 .ops = &ivt_uncore_pci_ops, \
1107 .format_group = &ivt_uncore_format_group
1108
1109 static struct attribute *ivt_uncore_formats_attr[] = {
1110 &format_attr_event.attr,
1111 &format_attr_umask.attr,
1112 &format_attr_edge.attr,
1113 &format_attr_inv.attr,
1114 &format_attr_thresh8.attr,
1115 NULL,
1116 };
1117
1118 static struct attribute *ivt_uncore_ubox_formats_attr[] = {
1119 &format_attr_event.attr,
1120 &format_attr_umask.attr,
1121 &format_attr_edge.attr,
1122 &format_attr_inv.attr,
1123 &format_attr_thresh5.attr,
1124 NULL,
1125 };
1126
1127 static struct attribute *ivt_uncore_cbox_formats_attr[] = {
1128 &format_attr_event.attr,
1129 &format_attr_umask.attr,
1130 &format_attr_edge.attr,
1131 &format_attr_tid_en.attr,
1132 &format_attr_thresh8.attr,
1133 &format_attr_filter_tid.attr,
1134 &format_attr_filter_link.attr,
1135 &format_attr_filter_state2.attr,
1136 &format_attr_filter_nid2.attr,
1137 &format_attr_filter_opc2.attr,
1138 NULL,
1139 };
1140
1141 static struct attribute *ivt_uncore_pcu_formats_attr[] = {
1142 &format_attr_event_ext.attr,
1143 &format_attr_occ_sel.attr,
1144 &format_attr_edge.attr,
1145 &format_attr_thresh5.attr,
1146 &format_attr_occ_invert.attr,
1147 &format_attr_occ_edge.attr,
1148 &format_attr_filter_band0.attr,
1149 &format_attr_filter_band1.attr,
1150 &format_attr_filter_band2.attr,
1151 &format_attr_filter_band3.attr,
1152 NULL,
1153 };
1154
1155 static struct attribute *ivt_uncore_qpi_formats_attr[] = {
1156 &format_attr_event_ext.attr,
1157 &format_attr_umask.attr,
1158 &format_attr_edge.attr,
1159 &format_attr_thresh8.attr,
1160 &format_attr_match_rds.attr,
1161 &format_attr_match_rnid30.attr,
1162 &format_attr_match_rnid4.attr,
1163 &format_attr_match_dnid.attr,
1164 &format_attr_match_mc.attr,
1165 &format_attr_match_opc.attr,
1166 &format_attr_match_vnw.attr,
1167 &format_attr_match0.attr,
1168 &format_attr_match1.attr,
1169 &format_attr_mask_rds.attr,
1170 &format_attr_mask_rnid30.attr,
1171 &format_attr_mask_rnid4.attr,
1172 &format_attr_mask_dnid.attr,
1173 &format_attr_mask_mc.attr,
1174 &format_attr_mask_opc.attr,
1175 &format_attr_mask_vnw.attr,
1176 &format_attr_mask0.attr,
1177 &format_attr_mask1.attr,
1178 NULL,
1179 };
1180
1181 static struct attribute_group ivt_uncore_format_group = {
1182 .name = "format",
1183 .attrs = ivt_uncore_formats_attr,
1184 };
1185
1186 static struct attribute_group ivt_uncore_ubox_format_group = {
1187 .name = "format",
1188 .attrs = ivt_uncore_ubox_formats_attr,
1189 };
1190
1191 static struct attribute_group ivt_uncore_cbox_format_group = {
1192 .name = "format",
1193 .attrs = ivt_uncore_cbox_formats_attr,
1194 };
1195
1196 static struct attribute_group ivt_uncore_pcu_format_group = {
1197 .name = "format",
1198 .attrs = ivt_uncore_pcu_formats_attr,
1199 };
1200
1201 static struct attribute_group ivt_uncore_qpi_format_group = {
1202 .name = "format",
1203 .attrs = ivt_uncore_qpi_formats_attr,
1204 };
1205
1206 static struct intel_uncore_type ivt_uncore_ubox = {
1207 .name = "ubox",
1208 .num_counters = 2,
1209 .num_boxes = 1,
1210 .perf_ctr_bits = 44,
1211 .fixed_ctr_bits = 48,
1212 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
1213 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
1214 .event_mask = IVT_U_MSR_PMON_RAW_EVENT_MASK,
1215 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
1216 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
1217 .ops = &ivt_uncore_msr_ops,
1218 .format_group = &ivt_uncore_ubox_format_group,
1219 };
1220
1221 static struct extra_reg ivt_uncore_cbox_extra_regs[] = {
1222 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
1223 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
1224 SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
1225 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
1226 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
1227 SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc),
1228 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
1229 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc),
1230 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
1231 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc),
1232 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
1233 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc),
1234 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
1235 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
1236 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
1237 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
1238 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
1239 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
1240 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
1241 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
1242 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
1243 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
1244 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
1245 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
1246 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
1247 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
1248 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1249 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1250 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
1251 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
1252 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
1253 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
1254 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
1255 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
1256 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
1257 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
1258 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
1259 EVENT_EXTRA_END
1260 };
1261
1262 static u64 ivt_cbox_filter_mask(int fields)
1263 {
1264 u64 mask = 0;
1265
1266 if (fields & 0x1)
1267 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_TID;
1268 if (fields & 0x2)
1269 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_LINK;
1270 if (fields & 0x4)
1271 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_STATE;
1272 if (fields & 0x8)
1273 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_NID;
1274 if (fields & 0x10)
1275 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_OPC;
1276
1277 return mask;
1278 }
1279
1280 static struct event_constraint *
1281 ivt_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1282 {
1283 return __snbep_cbox_get_constraint(box, event, ivt_cbox_filter_mask);
1284 }
1285
1286 static int ivt_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1287 {
1288 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1289 struct extra_reg *er;
1290 int idx = 0;
1291
1292 for (er = ivt_uncore_cbox_extra_regs; er->msr; er++) {
1293 if (er->event != (event->hw.config & er->config_mask))
1294 continue;
1295 idx |= er->idx;
1296 }
1297
1298 if (idx) {
1299 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
1300 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
1301 reg1->config = event->attr.config1 & ivt_cbox_filter_mask(idx);
1302 reg1->idx = idx;
1303 }
1304 return 0;
1305 }
1306
1307 static void ivt_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1308 {
1309 struct hw_perf_event *hwc = &event->hw;
1310 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1311
1312 if (reg1->idx != EXTRA_REG_NONE) {
1313 u64 filter = uncore_shared_reg_config(box, 0);
1314 wrmsrl(reg1->reg, filter & 0xffffffff);
1315 wrmsrl(reg1->reg + 6, filter >> 32);
1316 }
1317
1318 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
1319 }
1320
1321 static struct intel_uncore_ops ivt_uncore_cbox_ops = {
1322 .init_box = ivt_uncore_msr_init_box,
1323 .disable_box = snbep_uncore_msr_disable_box,
1324 .enable_box = snbep_uncore_msr_enable_box,
1325 .disable_event = snbep_uncore_msr_disable_event,
1326 .enable_event = ivt_cbox_enable_event,
1327 .read_counter = uncore_msr_read_counter,
1328 .hw_config = ivt_cbox_hw_config,
1329 .get_constraint = ivt_cbox_get_constraint,
1330 .put_constraint = snbep_cbox_put_constraint,
1331 };
1332
1333 static struct intel_uncore_type ivt_uncore_cbox = {
1334 .name = "cbox",
1335 .num_counters = 4,
1336 .num_boxes = 15,
1337 .perf_ctr_bits = 44,
1338 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
1339 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
1340 .event_mask = IVT_CBO_MSR_PMON_RAW_EVENT_MASK,
1341 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
1342 .msr_offset = SNBEP_CBO_MSR_OFFSET,
1343 .num_shared_regs = 1,
1344 .constraints = snbep_uncore_cbox_constraints,
1345 .ops = &ivt_uncore_cbox_ops,
1346 .format_group = &ivt_uncore_cbox_format_group,
1347 };
1348
1349 static struct intel_uncore_ops ivt_uncore_pcu_ops = {
1350 IVT_UNCORE_MSR_OPS_COMMON_INIT(),
1351 .hw_config = snbep_pcu_hw_config,
1352 .get_constraint = snbep_pcu_get_constraint,
1353 .put_constraint = snbep_pcu_put_constraint,
1354 };
1355
1356 static struct intel_uncore_type ivt_uncore_pcu = {
1357 .name = "pcu",
1358 .num_counters = 4,
1359 .num_boxes = 1,
1360 .perf_ctr_bits = 48,
1361 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
1362 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
1363 .event_mask = IVT_PCU_MSR_PMON_RAW_EVENT_MASK,
1364 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
1365 .num_shared_regs = 1,
1366 .ops = &ivt_uncore_pcu_ops,
1367 .format_group = &ivt_uncore_pcu_format_group,
1368 };
1369
1370 static struct intel_uncore_type *ivt_msr_uncores[] = {
1371 &ivt_uncore_ubox,
1372 &ivt_uncore_cbox,
1373 &ivt_uncore_pcu,
1374 NULL,
1375 };
1376
1377 static struct intel_uncore_type ivt_uncore_ha = {
1378 .name = "ha",
1379 .num_counters = 4,
1380 .num_boxes = 2,
1381 .perf_ctr_bits = 48,
1382 IVT_UNCORE_PCI_COMMON_INIT(),
1383 };
1384
1385 static struct intel_uncore_type ivt_uncore_imc = {
1386 .name = "imc",
1387 .num_counters = 4,
1388 .num_boxes = 8,
1389 .perf_ctr_bits = 48,
1390 .fixed_ctr_bits = 48,
1391 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
1392 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
1393 IVT_UNCORE_PCI_COMMON_INIT(),
1394 };
1395
1396 /* registers in IRP boxes are not properly aligned */
1397 static unsigned ivt_uncore_irp_ctls[] = {0xd8, 0xdc, 0xe0, 0xe4};
1398 static unsigned ivt_uncore_irp_ctrs[] = {0xa0, 0xb0, 0xb8, 0xc0};
1399
1400 static void ivt_uncore_irp_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1401 {
1402 struct pci_dev *pdev = box->pci_dev;
1403 struct hw_perf_event *hwc = &event->hw;
1404
1405 pci_write_config_dword(pdev, ivt_uncore_irp_ctls[hwc->idx],
1406 hwc->config | SNBEP_PMON_CTL_EN);
1407 }
1408
1409 static void ivt_uncore_irp_disable_event(struct intel_uncore_box *box, struct perf_event *event)
1410 {
1411 struct pci_dev *pdev = box->pci_dev;
1412 struct hw_perf_event *hwc = &event->hw;
1413
1414 pci_write_config_dword(pdev, ivt_uncore_irp_ctls[hwc->idx], hwc->config);
1415 }
1416
1417 static u64 ivt_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
1418 {
1419 struct pci_dev *pdev = box->pci_dev;
1420 struct hw_perf_event *hwc = &event->hw;
1421 u64 count = 0;
1422
1423 pci_read_config_dword(pdev, ivt_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
1424 pci_read_config_dword(pdev, ivt_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
1425
1426 return count;
1427 }
1428
1429 static struct intel_uncore_ops ivt_uncore_irp_ops = {
1430 .init_box = ivt_uncore_pci_init_box,
1431 .disable_box = snbep_uncore_pci_disable_box,
1432 .enable_box = snbep_uncore_pci_enable_box,
1433 .disable_event = ivt_uncore_irp_disable_event,
1434 .enable_event = ivt_uncore_irp_enable_event,
1435 .read_counter = ivt_uncore_irp_read_counter,
1436 };
1437
1438 static struct intel_uncore_type ivt_uncore_irp = {
1439 .name = "irp",
1440 .num_counters = 4,
1441 .num_boxes = 1,
1442 .perf_ctr_bits = 48,
1443 .event_mask = IVT_PMON_RAW_EVENT_MASK,
1444 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1445 .ops = &ivt_uncore_irp_ops,
1446 .format_group = &ivt_uncore_format_group,
1447 };
1448
1449 static struct intel_uncore_ops ivt_uncore_qpi_ops = {
1450 .init_box = ivt_uncore_pci_init_box,
1451 .disable_box = snbep_uncore_pci_disable_box,
1452 .enable_box = snbep_uncore_pci_enable_box,
1453 .disable_event = snbep_uncore_pci_disable_event,
1454 .enable_event = snbep_qpi_enable_event,
1455 .read_counter = snbep_uncore_pci_read_counter,
1456 .hw_config = snbep_qpi_hw_config,
1457 .get_constraint = uncore_get_constraint,
1458 .put_constraint = uncore_put_constraint,
1459 };
1460
1461 static struct intel_uncore_type ivt_uncore_qpi = {
1462 .name = "qpi",
1463 .num_counters = 4,
1464 .num_boxes = 3,
1465 .perf_ctr_bits = 48,
1466 .perf_ctr = SNBEP_PCI_PMON_CTR0,
1467 .event_ctl = SNBEP_PCI_PMON_CTL0,
1468 .event_mask = IVT_QPI_PCI_PMON_RAW_EVENT_MASK,
1469 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1470 .num_shared_regs = 1,
1471 .ops = &ivt_uncore_qpi_ops,
1472 .format_group = &ivt_uncore_qpi_format_group,
1473 };
1474
1475 static struct intel_uncore_type ivt_uncore_r2pcie = {
1476 .name = "r2pcie",
1477 .num_counters = 4,
1478 .num_boxes = 1,
1479 .perf_ctr_bits = 44,
1480 .constraints = snbep_uncore_r2pcie_constraints,
1481 IVT_UNCORE_PCI_COMMON_INIT(),
1482 };
1483
1484 static struct intel_uncore_type ivt_uncore_r3qpi = {
1485 .name = "r3qpi",
1486 .num_counters = 3,
1487 .num_boxes = 2,
1488 .perf_ctr_bits = 44,
1489 .constraints = snbep_uncore_r3qpi_constraints,
1490 IVT_UNCORE_PCI_COMMON_INIT(),
1491 };
1492
1493 enum {
1494 IVT_PCI_UNCORE_HA,
1495 IVT_PCI_UNCORE_IMC,
1496 IVT_PCI_UNCORE_IRP,
1497 IVT_PCI_UNCORE_QPI,
1498 IVT_PCI_UNCORE_R2PCIE,
1499 IVT_PCI_UNCORE_R3QPI,
1500 };
1501
1502 static struct intel_uncore_type *ivt_pci_uncores[] = {
1503 [IVT_PCI_UNCORE_HA] = &ivt_uncore_ha,
1504 [IVT_PCI_UNCORE_IMC] = &ivt_uncore_imc,
1505 [IVT_PCI_UNCORE_IRP] = &ivt_uncore_irp,
1506 [IVT_PCI_UNCORE_QPI] = &ivt_uncore_qpi,
1507 [IVT_PCI_UNCORE_R2PCIE] = &ivt_uncore_r2pcie,
1508 [IVT_PCI_UNCORE_R3QPI] = &ivt_uncore_r3qpi,
1509 NULL,
1510 };
1511
1512 static DEFINE_PCI_DEVICE_TABLE(ivt_uncore_pci_ids) = {
1513 { /* Home Agent 0 */
1514 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30),
1515 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_HA, 0),
1516 },
1517 { /* Home Agent 1 */
1518 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38),
1519 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_HA, 1),
1520 },
1521 { /* MC0 Channel 0 */
1522 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4),
1523 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 0),
1524 },
1525 { /* MC0 Channel 1 */
1526 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5),
1527 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 1),
1528 },
1529 { /* MC0 Channel 3 */
1530 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0),
1531 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 2),
1532 },
1533 { /* MC0 Channel 4 */
1534 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1),
1535 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 3),
1536 },
1537 { /* MC1 Channel 0 */
1538 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4),
1539 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 4),
1540 },
1541 { /* MC1 Channel 1 */
1542 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5),
1543 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 5),
1544 },
1545 { /* MC1 Channel 3 */
1546 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0),
1547 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 6),
1548 },
1549 { /* MC1 Channel 4 */
1550 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1),
1551 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 7),
1552 },
1553 { /* IRP */
1554 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe39),
1555 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IRP, 0),
1556 },
1557 { /* QPI0 Port 0 */
1558 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32),
1559 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI, 0),
1560 },
1561 { /* QPI0 Port 1 */
1562 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33),
1563 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI, 1),
1564 },
1565 { /* QPI1 Port 2 */
1566 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a),
1567 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI, 2),
1568 },
1569 { /* R2PCIe */
1570 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34),
1571 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R2PCIE, 0),
1572 },
1573 { /* R3QPI0 Link 0 */
1574 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36),
1575 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI, 0),
1576 },
1577 { /* R3QPI0 Link 1 */
1578 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37),
1579 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI, 1),
1580 },
1581 { /* R3QPI1 Link 2 */
1582 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e),
1583 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI, 2),
1584 },
1585 { /* QPI Port 0 filter */
1586 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe86),
1587 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1588 SNBEP_PCI_QPI_PORT0_FILTER),
1589 },
1590 { /* QPI Port 0 filter */
1591 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe96),
1592 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1593 SNBEP_PCI_QPI_PORT1_FILTER),
1594 },
1595 { /* end: all zeroes */ }
1596 };
1597
1598 static struct pci_driver ivt_uncore_pci_driver = {
1599 .name = "ivt_uncore",
1600 .id_table = ivt_uncore_pci_ids,
1601 };
1602 /* end of IvyTown uncore support */
1603
1604 /* Sandy Bridge uncore support */
1605 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1606 {
1607 struct hw_perf_event *hwc = &event->hw;
1608
1609 if (hwc->idx < UNCORE_PMC_IDX_FIXED)
1610 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
1611 else
1612 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
1613 }
1614
1615 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
1616 {
1617 wrmsrl(event->hw.config_base, 0);
1618 }
1619
1620 static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
1621 {
1622 if (box->pmu->pmu_idx == 0) {
1623 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
1624 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
1625 }
1626 }
1627
1628 static struct uncore_event_desc snb_uncore_events[] = {
1629 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
1630 { /* end: all zeroes */ },
1631 };
1632
1633 static struct attribute *snb_uncore_formats_attr[] = {
1634 &format_attr_event.attr,
1635 &format_attr_umask.attr,
1636 &format_attr_edge.attr,
1637 &format_attr_inv.attr,
1638 &format_attr_cmask5.attr,
1639 NULL,
1640 };
1641
1642 static struct attribute_group snb_uncore_format_group = {
1643 .name = "format",
1644 .attrs = snb_uncore_formats_attr,
1645 };
1646
1647 static struct intel_uncore_ops snb_uncore_msr_ops = {
1648 .init_box = snb_uncore_msr_init_box,
1649 .disable_event = snb_uncore_msr_disable_event,
1650 .enable_event = snb_uncore_msr_enable_event,
1651 .read_counter = uncore_msr_read_counter,
1652 };
1653
1654 static struct event_constraint snb_uncore_cbox_constraints[] = {
1655 UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
1656 UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
1657 EVENT_CONSTRAINT_END
1658 };
1659
1660 static struct intel_uncore_type snb_uncore_cbox = {
1661 .name = "cbox",
1662 .num_counters = 2,
1663 .num_boxes = 4,
1664 .perf_ctr_bits = 44,
1665 .fixed_ctr_bits = 48,
1666 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0,
1667 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
1668 .fixed_ctr = SNB_UNC_FIXED_CTR,
1669 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
1670 .single_fixed = 1,
1671 .event_mask = SNB_UNC_RAW_EVENT_MASK,
1672 .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
1673 .constraints = snb_uncore_cbox_constraints,
1674 .ops = &snb_uncore_msr_ops,
1675 .format_group = &snb_uncore_format_group,
1676 .event_descs = snb_uncore_events,
1677 };
1678
1679 static struct intel_uncore_type *snb_msr_uncores[] = {
1680 &snb_uncore_cbox,
1681 NULL,
1682 };
1683
1684 enum {
1685 SNB_PCI_UNCORE_IMC,
1686 };
1687
1688 static struct uncore_event_desc snb_uncore_imc_events[] = {
1689 INTEL_UNCORE_EVENT_DESC(data_reads, "event=0x01"),
1690 INTEL_UNCORE_EVENT_DESC(data_reads.scale, "6.103515625e-5"),
1691 INTEL_UNCORE_EVENT_DESC(data_reads.unit, "MiB"),
1692
1693 INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
1694 INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
1695 INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
1696
1697 { /* end: all zeroes */ },
1698 };
1699
1700 #define SNB_UNCORE_PCI_IMC_EVENT_MASK 0xff
1701 #define SNB_UNCORE_PCI_IMC_BAR_OFFSET 0x48
1702
1703 /* page size multiple covering all config regs */
1704 #define SNB_UNCORE_PCI_IMC_MAP_SIZE 0x6000
1705
1706 #define SNB_UNCORE_PCI_IMC_DATA_READS 0x1
1707 #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE 0x5050
1708 #define SNB_UNCORE_PCI_IMC_DATA_WRITES 0x2
1709 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
1710 #define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE
1711
1712 static struct attribute *snb_uncore_imc_formats_attr[] = {
1713 &format_attr_event.attr,
1714 NULL,
1715 };
1716
1717 static struct attribute_group snb_uncore_imc_format_group = {
1718 .name = "format",
1719 .attrs = snb_uncore_imc_formats_attr,
1720 };
1721
1722 static void snb_uncore_imc_init_box(struct intel_uncore_box *box)
1723 {
1724 struct pci_dev *pdev = box->pci_dev;
1725 u32 addr_lo, addr_hi;
1726 resource_size_t addr;
1727
1728 pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET, &addr_lo);
1729 addr = addr_lo;
1730
1731 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1732 pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET+4, &addr_hi);
1733 addr = ((resource_size_t)addr_hi << 32) | addr_lo;
1734 #endif
1735
1736 addr &= ~(PAGE_SIZE - 1);
1737
1738 box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
1739 box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL;
1740 }
1741
1742 static void snb_uncore_imc_enable_box(struct intel_uncore_box *box)
1743 {}
1744
1745 static void snb_uncore_imc_disable_box(struct intel_uncore_box *box)
1746 {}
1747
1748 static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1749 {}
1750
1751 static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event)
1752 {}
1753
1754 static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event)
1755 {
1756 struct hw_perf_event *hwc = &event->hw;
1757
1758 return (u64)*(unsigned int *)(box->io_addr + hwc->event_base);
1759 }
1760
1761 /*
1762 * custom event_init() function because we define our own fixed, free
1763 * running counters, so we do not want to conflict with generic uncore
1764 * logic. Also simplifies processing
1765 */
1766 static int snb_uncore_imc_event_init(struct perf_event *event)
1767 {
1768 struct intel_uncore_pmu *pmu;
1769 struct intel_uncore_box *box;
1770 struct hw_perf_event *hwc = &event->hw;
1771 u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK;
1772 int idx, base;
1773
1774 if (event->attr.type != event->pmu->type)
1775 return -ENOENT;
1776
1777 pmu = uncore_event_to_pmu(event);
1778 /* no device found for this pmu */
1779 if (pmu->func_id < 0)
1780 return -ENOENT;
1781
1782 /* Sampling not supported yet */
1783 if (hwc->sample_period)
1784 return -EINVAL;
1785
1786 /* unsupported modes and filters */
1787 if (event->attr.exclude_user ||
1788 event->attr.exclude_kernel ||
1789 event->attr.exclude_hv ||
1790 event->attr.exclude_idle ||
1791 event->attr.exclude_host ||
1792 event->attr.exclude_guest ||
1793 event->attr.sample_period) /* no sampling */
1794 return -EINVAL;
1795
1796 /*
1797 * Place all uncore events for a particular physical package
1798 * onto a single cpu
1799 */
1800 if (event->cpu < 0)
1801 return -EINVAL;
1802
1803 /* check only supported bits are set */
1804 if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK)
1805 return -EINVAL;
1806
1807 box = uncore_pmu_to_box(pmu, event->cpu);
1808 if (!box || box->cpu < 0)
1809 return -EINVAL;
1810
1811 event->cpu = box->cpu;
1812
1813 event->hw.idx = -1;
1814 event->hw.last_tag = ~0ULL;
1815 event->hw.extra_reg.idx = EXTRA_REG_NONE;
1816 event->hw.branch_reg.idx = EXTRA_REG_NONE;
1817 /*
1818 * check event is known (whitelist, determines counter)
1819 */
1820 switch (cfg) {
1821 case SNB_UNCORE_PCI_IMC_DATA_READS:
1822 base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE;
1823 idx = UNCORE_PMC_IDX_FIXED;
1824 break;
1825 case SNB_UNCORE_PCI_IMC_DATA_WRITES:
1826 base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
1827 idx = UNCORE_PMC_IDX_FIXED + 1;
1828 break;
1829 default:
1830 return -EINVAL;
1831 }
1832
1833 /* must be done before validate_group */
1834 event->hw.event_base = base;
1835 event->hw.config = cfg;
1836 event->hw.idx = idx;
1837
1838 /* no group validation needed, we have free running counters */
1839
1840 return 0;
1841 }
1842
1843 static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1844 {
1845 return 0;
1846 }
1847
1848 static void snb_uncore_imc_event_start(struct perf_event *event, int flags)
1849 {
1850 struct intel_uncore_box *box = uncore_event_to_box(event);
1851 u64 count;
1852
1853 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1854 return;
1855
1856 event->hw.state = 0;
1857 box->n_active++;
1858
1859 list_add_tail(&event->active_entry, &box->active_list);
1860
1861 count = snb_uncore_imc_read_counter(box, event);
1862 local64_set(&event->hw.prev_count, count);
1863
1864 if (box->n_active == 1)
1865 uncore_pmu_start_hrtimer(box);
1866 }
1867
1868 static void snb_uncore_imc_event_stop(struct perf_event *event, int flags)
1869 {
1870 struct intel_uncore_box *box = uncore_event_to_box(event);
1871 struct hw_perf_event *hwc = &event->hw;
1872
1873 if (!(hwc->state & PERF_HES_STOPPED)) {
1874 box->n_active--;
1875
1876 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1877 hwc->state |= PERF_HES_STOPPED;
1878
1879 list_del(&event->active_entry);
1880
1881 if (box->n_active == 0)
1882 uncore_pmu_cancel_hrtimer(box);
1883 }
1884
1885 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1886 /*
1887 * Drain the remaining delta count out of a event
1888 * that we are disabling:
1889 */
1890 uncore_perf_event_update(box, event);
1891 hwc->state |= PERF_HES_UPTODATE;
1892 }
1893 }
1894
1895 static int snb_uncore_imc_event_add(struct perf_event *event, int flags)
1896 {
1897 struct intel_uncore_box *box = uncore_event_to_box(event);
1898 struct hw_perf_event *hwc = &event->hw;
1899
1900 if (!box)
1901 return -ENODEV;
1902
1903 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1904 if (!(flags & PERF_EF_START))
1905 hwc->state |= PERF_HES_ARCH;
1906
1907 snb_uncore_imc_event_start(event, 0);
1908
1909 box->n_events++;
1910
1911 return 0;
1912 }
1913
1914 static void snb_uncore_imc_event_del(struct perf_event *event, int flags)
1915 {
1916 struct intel_uncore_box *box = uncore_event_to_box(event);
1917 int i;
1918
1919 snb_uncore_imc_event_stop(event, PERF_EF_UPDATE);
1920
1921 for (i = 0; i < box->n_events; i++) {
1922 if (event == box->event_list[i]) {
1923 --box->n_events;
1924 break;
1925 }
1926 }
1927 }
1928
1929 static int snb_pci2phy_map_init(int devid)
1930 {
1931 struct pci_dev *dev = NULL;
1932 int bus;
1933
1934 dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev);
1935 if (!dev)
1936 return -ENOTTY;
1937
1938 bus = dev->bus->number;
1939
1940 pcibus_to_physid[bus] = 0;
1941
1942 pci_dev_put(dev);
1943
1944 return 0;
1945 }
1946
1947 static struct pmu snb_uncore_imc_pmu = {
1948 .task_ctx_nr = perf_invalid_context,
1949 .event_init = snb_uncore_imc_event_init,
1950 .add = snb_uncore_imc_event_add,
1951 .del = snb_uncore_imc_event_del,
1952 .start = snb_uncore_imc_event_start,
1953 .stop = snb_uncore_imc_event_stop,
1954 .read = uncore_pmu_event_read,
1955 };
1956
1957 static struct intel_uncore_ops snb_uncore_imc_ops = {
1958 .init_box = snb_uncore_imc_init_box,
1959 .enable_box = snb_uncore_imc_enable_box,
1960 .disable_box = snb_uncore_imc_disable_box,
1961 .disable_event = snb_uncore_imc_disable_event,
1962 .enable_event = snb_uncore_imc_enable_event,
1963 .hw_config = snb_uncore_imc_hw_config,
1964 .read_counter = snb_uncore_imc_read_counter,
1965 };
1966
1967 static struct intel_uncore_type snb_uncore_imc = {
1968 .name = "imc",
1969 .num_counters = 2,
1970 .num_boxes = 1,
1971 .fixed_ctr_bits = 32,
1972 .fixed_ctr = SNB_UNCORE_PCI_IMC_CTR_BASE,
1973 .event_descs = snb_uncore_imc_events,
1974 .format_group = &snb_uncore_imc_format_group,
1975 .perf_ctr = SNB_UNCORE_PCI_IMC_DATA_READS_BASE,
1976 .event_mask = SNB_UNCORE_PCI_IMC_EVENT_MASK,
1977 .ops = &snb_uncore_imc_ops,
1978 .pmu = &snb_uncore_imc_pmu,
1979 };
1980
1981 static struct intel_uncore_type *snb_pci_uncores[] = {
1982 [SNB_PCI_UNCORE_IMC] = &snb_uncore_imc,
1983 NULL,
1984 };
1985
1986 static DEFINE_PCI_DEVICE_TABLE(snb_uncore_pci_ids) = {
1987 { /* IMC */
1988 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SNB_IMC),
1989 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1990 },
1991 };
1992
1993 static DEFINE_PCI_DEVICE_TABLE(ivb_uncore_pci_ids) = {
1994 { /* IMC */
1995 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC),
1996 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1997 },
1998 };
1999
2000 static DEFINE_PCI_DEVICE_TABLE(hsw_uncore_pci_ids) = {
2001 { /* IMC */
2002 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),
2003 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
2004 },
2005 };
2006
2007 static struct pci_driver snb_uncore_pci_driver = {
2008 .name = "snb_uncore",
2009 .id_table = snb_uncore_pci_ids,
2010 };
2011
2012 static struct pci_driver ivb_uncore_pci_driver = {
2013 .name = "ivb_uncore",
2014 .id_table = ivb_uncore_pci_ids,
2015 };
2016
2017 static struct pci_driver hsw_uncore_pci_driver = {
2018 .name = "hsw_uncore",
2019 .id_table = hsw_uncore_pci_ids,
2020 };
2021
2022 /* end of Sandy Bridge uncore support */
2023
2024 /* Nehalem uncore support */
2025 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
2026 {
2027 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
2028 }
2029
2030 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
2031 {
2032 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
2033 }
2034
2035 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2036 {
2037 struct hw_perf_event *hwc = &event->hw;
2038
2039 if (hwc->idx < UNCORE_PMC_IDX_FIXED)
2040 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
2041 else
2042 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
2043 }
2044
2045 static struct attribute *nhm_uncore_formats_attr[] = {
2046 &format_attr_event.attr,
2047 &format_attr_umask.attr,
2048 &format_attr_edge.attr,
2049 &format_attr_inv.attr,
2050 &format_attr_cmask8.attr,
2051 NULL,
2052 };
2053
2054 static struct attribute_group nhm_uncore_format_group = {
2055 .name = "format",
2056 .attrs = nhm_uncore_formats_attr,
2057 };
2058
2059 static struct uncore_event_desc nhm_uncore_events[] = {
2060 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
2061 INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any, "event=0x2f,umask=0x0f"),
2062 INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any, "event=0x2c,umask=0x0f"),
2063 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads, "event=0x20,umask=0x01"),
2064 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes, "event=0x20,umask=0x02"),
2065 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads, "event=0x20,umask=0x04"),
2066 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
2067 INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads, "event=0x20,umask=0x10"),
2068 INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes, "event=0x20,umask=0x20"),
2069 { /* end: all zeroes */ },
2070 };
2071
2072 static struct intel_uncore_ops nhm_uncore_msr_ops = {
2073 .disable_box = nhm_uncore_msr_disable_box,
2074 .enable_box = nhm_uncore_msr_enable_box,
2075 .disable_event = snb_uncore_msr_disable_event,
2076 .enable_event = nhm_uncore_msr_enable_event,
2077 .read_counter = uncore_msr_read_counter,
2078 };
2079
2080 static struct intel_uncore_type nhm_uncore = {
2081 .name = "",
2082 .num_counters = 8,
2083 .num_boxes = 1,
2084 .perf_ctr_bits = 48,
2085 .fixed_ctr_bits = 48,
2086 .event_ctl = NHM_UNC_PERFEVTSEL0,
2087 .perf_ctr = NHM_UNC_UNCORE_PMC0,
2088 .fixed_ctr = NHM_UNC_FIXED_CTR,
2089 .fixed_ctl = NHM_UNC_FIXED_CTR_CTRL,
2090 .event_mask = NHM_UNC_RAW_EVENT_MASK,
2091 .event_descs = nhm_uncore_events,
2092 .ops = &nhm_uncore_msr_ops,
2093 .format_group = &nhm_uncore_format_group,
2094 };
2095
2096 static struct intel_uncore_type *nhm_msr_uncores[] = {
2097 &nhm_uncore,
2098 NULL,
2099 };
2100 /* end of Nehalem uncore support */
2101
2102 /* Nehalem-EX uncore support */
2103 DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");
2104 DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");
2105 DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
2106 DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63");
2107
2108 static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box)
2109 {
2110 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL);
2111 }
2112
2113 static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box)
2114 {
2115 unsigned msr = uncore_msr_box_ctl(box);
2116 u64 config;
2117
2118 if (msr) {
2119 rdmsrl(msr, config);
2120 config &= ~((1ULL << uncore_num_counters(box)) - 1);
2121 /* WBox has a fixed counter */
2122 if (uncore_msr_fixed_ctl(box))
2123 config &= ~NHMEX_W_PMON_GLOBAL_FIXED_EN;
2124 wrmsrl(msr, config);
2125 }
2126 }
2127
2128 static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box)
2129 {
2130 unsigned msr = uncore_msr_box_ctl(box);
2131 u64 config;
2132
2133 if (msr) {
2134 rdmsrl(msr, config);
2135 config |= (1ULL << uncore_num_counters(box)) - 1;
2136 /* WBox has a fixed counter */
2137 if (uncore_msr_fixed_ctl(box))
2138 config |= NHMEX_W_PMON_GLOBAL_FIXED_EN;
2139 wrmsrl(msr, config);
2140 }
2141 }
2142
2143 static void nhmex_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
2144 {
2145 wrmsrl(event->hw.config_base, 0);
2146 }
2147
2148 static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2149 {
2150 struct hw_perf_event *hwc = &event->hw;
2151
2152 if (hwc->idx >= UNCORE_PMC_IDX_FIXED)
2153 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0);
2154 else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0)
2155 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
2156 else
2157 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
2158 }
2159
2160 #define NHMEX_UNCORE_OPS_COMMON_INIT() \
2161 .init_box = nhmex_uncore_msr_init_box, \
2162 .disable_box = nhmex_uncore_msr_disable_box, \
2163 .enable_box = nhmex_uncore_msr_enable_box, \
2164 .disable_event = nhmex_uncore_msr_disable_event, \
2165 .read_counter = uncore_msr_read_counter
2166
2167 static struct intel_uncore_ops nhmex_uncore_ops = {
2168 NHMEX_UNCORE_OPS_COMMON_INIT(),
2169 .enable_event = nhmex_uncore_msr_enable_event,
2170 };
2171
2172 static struct attribute *nhmex_uncore_ubox_formats_attr[] = {
2173 &format_attr_event.attr,
2174 &format_attr_edge.attr,
2175 NULL,
2176 };
2177
2178 static struct attribute_group nhmex_uncore_ubox_format_group = {
2179 .name = "format",
2180 .attrs = nhmex_uncore_ubox_formats_attr,
2181 };
2182
2183 static struct intel_uncore_type nhmex_uncore_ubox = {
2184 .name = "ubox",
2185 .num_counters = 1,
2186 .num_boxes = 1,
2187 .perf_ctr_bits = 48,
2188 .event_ctl = NHMEX_U_MSR_PMON_EV_SEL,
2189 .perf_ctr = NHMEX_U_MSR_PMON_CTR,
2190 .event_mask = NHMEX_U_PMON_RAW_EVENT_MASK,
2191 .box_ctl = NHMEX_U_MSR_PMON_GLOBAL_CTL,
2192 .ops = &nhmex_uncore_ops,
2193 .format_group = &nhmex_uncore_ubox_format_group
2194 };
2195
2196 static struct attribute *nhmex_uncore_cbox_formats_attr[] = {
2197 &format_attr_event.attr,
2198 &format_attr_umask.attr,
2199 &format_attr_edge.attr,
2200 &format_attr_inv.attr,
2201 &format_attr_thresh8.attr,
2202 NULL,
2203 };
2204
2205 static struct attribute_group nhmex_uncore_cbox_format_group = {
2206 .name = "format",
2207 .attrs = nhmex_uncore_cbox_formats_attr,
2208 };
2209
2210 /* msr offset for each instance of cbox */
2211 static unsigned nhmex_cbox_msr_offsets[] = {
2212 0x0, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x240, 0x2c0,
2213 };
2214
2215 static struct intel_uncore_type nhmex_uncore_cbox = {
2216 .name = "cbox",
2217 .num_counters = 6,
2218 .num_boxes = 10,
2219 .perf_ctr_bits = 48,
2220 .event_ctl = NHMEX_C0_MSR_PMON_EV_SEL0,
2221 .perf_ctr = NHMEX_C0_MSR_PMON_CTR0,
2222 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
2223 .box_ctl = NHMEX_C0_MSR_PMON_GLOBAL_CTL,
2224 .msr_offsets = nhmex_cbox_msr_offsets,
2225 .pair_ctr_ctl = 1,
2226 .ops = &nhmex_uncore_ops,
2227 .format_group = &nhmex_uncore_cbox_format_group
2228 };
2229
2230 static struct uncore_event_desc nhmex_uncore_wbox_events[] = {
2231 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0"),
2232 { /* end: all zeroes */ },
2233 };
2234
2235 static struct intel_uncore_type nhmex_uncore_wbox = {
2236 .name = "wbox",
2237 .num_counters = 4,
2238 .num_boxes = 1,
2239 .perf_ctr_bits = 48,
2240 .event_ctl = NHMEX_W_MSR_PMON_CNT0,
2241 .perf_ctr = NHMEX_W_MSR_PMON_EVT_SEL0,
2242 .fixed_ctr = NHMEX_W_MSR_PMON_FIXED_CTR,
2243 .fixed_ctl = NHMEX_W_MSR_PMON_FIXED_CTL,
2244 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
2245 .box_ctl = NHMEX_W_MSR_GLOBAL_CTL,
2246 .pair_ctr_ctl = 1,
2247 .event_descs = nhmex_uncore_wbox_events,
2248 .ops = &nhmex_uncore_ops,
2249 .format_group = &nhmex_uncore_cbox_format_group
2250 };
2251
2252 static int nhmex_bbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2253 {
2254 struct hw_perf_event *hwc = &event->hw;
2255 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2256 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2257 int ctr, ev_sel;
2258
2259 ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >>
2260 NHMEX_B_PMON_CTR_SHIFT;
2261 ev_sel = (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK) >>
2262 NHMEX_B_PMON_CTL_EV_SEL_SHIFT;
2263
2264 /* events that do not use the match/mask registers */
2265 if ((ctr == 0 && ev_sel > 0x3) || (ctr == 1 && ev_sel > 0x6) ||
2266 (ctr == 2 && ev_sel != 0x4) || ctr == 3)
2267 return 0;
2268
2269 if (box->pmu->pmu_idx == 0)
2270 reg1->reg = NHMEX_B0_MSR_MATCH;
2271 else
2272 reg1->reg = NHMEX_B1_MSR_MATCH;
2273 reg1->idx = 0;
2274 reg1->config = event->attr.config1;
2275 reg2->config = event->attr.config2;
2276 return 0;
2277 }
2278
2279 static void nhmex_bbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2280 {
2281 struct hw_perf_event *hwc = &event->hw;
2282 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2283 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2284
2285 if (reg1->idx != EXTRA_REG_NONE) {
2286 wrmsrl(reg1->reg, reg1->config);
2287 wrmsrl(reg1->reg + 1, reg2->config);
2288 }
2289 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
2290 (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK));
2291 }
2292
2293 /*
2294 * The Bbox has 4 counters, but each counter monitors different events.
2295 * Use bits 6-7 in the event config to select counter.
2296 */
2297 static struct event_constraint nhmex_uncore_bbox_constraints[] = {
2298 EVENT_CONSTRAINT(0 , 1, 0xc0),
2299 EVENT_CONSTRAINT(0x40, 2, 0xc0),
2300 EVENT_CONSTRAINT(0x80, 4, 0xc0),
2301 EVENT_CONSTRAINT(0xc0, 8, 0xc0),
2302 EVENT_CONSTRAINT_END,
2303 };
2304
2305 static struct attribute *nhmex_uncore_bbox_formats_attr[] = {
2306 &format_attr_event5.attr,
2307 &format_attr_counter.attr,
2308 &format_attr_match.attr,
2309 &format_attr_mask.attr,
2310 NULL,
2311 };
2312
2313 static struct attribute_group nhmex_uncore_bbox_format_group = {
2314 .name = "format",
2315 .attrs = nhmex_uncore_bbox_formats_attr,
2316 };
2317
2318 static struct intel_uncore_ops nhmex_uncore_bbox_ops = {
2319 NHMEX_UNCORE_OPS_COMMON_INIT(),
2320 .enable_event = nhmex_bbox_msr_enable_event,
2321 .hw_config = nhmex_bbox_hw_config,
2322 .get_constraint = uncore_get_constraint,
2323 .put_constraint = uncore_put_constraint,
2324 };
2325
2326 static struct intel_uncore_type nhmex_uncore_bbox = {
2327 .name = "bbox",
2328 .num_counters = 4,
2329 .num_boxes = 2,
2330 .perf_ctr_bits = 48,
2331 .event_ctl = NHMEX_B0_MSR_PMON_CTL0,
2332 .perf_ctr = NHMEX_B0_MSR_PMON_CTR0,
2333 .event_mask = NHMEX_B_PMON_RAW_EVENT_MASK,
2334 .box_ctl = NHMEX_B0_MSR_PMON_GLOBAL_CTL,
2335 .msr_offset = NHMEX_B_MSR_OFFSET,
2336 .pair_ctr_ctl = 1,
2337 .num_shared_regs = 1,
2338 .constraints = nhmex_uncore_bbox_constraints,
2339 .ops = &nhmex_uncore_bbox_ops,
2340 .format_group = &nhmex_uncore_bbox_format_group
2341 };
2342
2343 static int nhmex_sbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2344 {
2345 struct hw_perf_event *hwc = &event->hw;
2346 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2347 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2348
2349 /* only TO_R_PROG_EV event uses the match/mask register */
2350 if ((hwc->config & NHMEX_PMON_CTL_EV_SEL_MASK) !=
2351 NHMEX_S_EVENT_TO_R_PROG_EV)
2352 return 0;
2353
2354 if (box->pmu->pmu_idx == 0)
2355 reg1->reg = NHMEX_S0_MSR_MM_CFG;
2356 else
2357 reg1->reg = NHMEX_S1_MSR_MM_CFG;
2358 reg1->idx = 0;
2359 reg1->config = event->attr.config1;
2360 reg2->config = event->attr.config2;
2361 return 0;
2362 }
2363
2364 static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2365 {
2366 struct hw_perf_event *hwc = &event->hw;
2367 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2368 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2369
2370 if (reg1->idx != EXTRA_REG_NONE) {
2371 wrmsrl(reg1->reg, 0);
2372 wrmsrl(reg1->reg + 1, reg1->config);
2373 wrmsrl(reg1->reg + 2, reg2->config);
2374 wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);
2375 }
2376 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
2377 }
2378
2379 static struct attribute *nhmex_uncore_sbox_formats_attr[] = {
2380 &format_attr_event.attr,
2381 &format_attr_umask.attr,
2382 &format_attr_edge.attr,
2383 &format_attr_inv.attr,
2384 &format_attr_thresh8.attr,
2385 &format_attr_match.attr,
2386 &format_attr_mask.attr,
2387 NULL,
2388 };
2389
2390 static struct attribute_group nhmex_uncore_sbox_format_group = {
2391 .name = "format",
2392 .attrs = nhmex_uncore_sbox_formats_attr,
2393 };
2394
2395 static struct intel_uncore_ops nhmex_uncore_sbox_ops = {
2396 NHMEX_UNCORE_OPS_COMMON_INIT(),
2397 .enable_event = nhmex_sbox_msr_enable_event,
2398 .hw_config = nhmex_sbox_hw_config,
2399 .get_constraint = uncore_get_constraint,
2400 .put_constraint = uncore_put_constraint,
2401 };
2402
2403 static struct intel_uncore_type nhmex_uncore_sbox = {
2404 .name = "sbox",
2405 .num_counters = 4,
2406 .num_boxes = 2,
2407 .perf_ctr_bits = 48,
2408 .event_ctl = NHMEX_S0_MSR_PMON_CTL0,
2409 .perf_ctr = NHMEX_S0_MSR_PMON_CTR0,
2410 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
2411 .box_ctl = NHMEX_S0_MSR_PMON_GLOBAL_CTL,
2412 .msr_offset = NHMEX_S_MSR_OFFSET,
2413 .pair_ctr_ctl = 1,
2414 .num_shared_regs = 1,
2415 .ops = &nhmex_uncore_sbox_ops,
2416 .format_group = &nhmex_uncore_sbox_format_group
2417 };
2418
2419 enum {
2420 EXTRA_REG_NHMEX_M_FILTER,
2421 EXTRA_REG_NHMEX_M_DSP,
2422 EXTRA_REG_NHMEX_M_ISS,
2423 EXTRA_REG_NHMEX_M_MAP,
2424 EXTRA_REG_NHMEX_M_MSC_THR,
2425 EXTRA_REG_NHMEX_M_PGT,
2426 EXTRA_REG_NHMEX_M_PLD,
2427 EXTRA_REG_NHMEX_M_ZDP_CTL_FVC,
2428 };
2429
2430 static struct extra_reg nhmex_uncore_mbox_extra_regs[] = {
2431 MBOX_INC_SEL_EXTAR_REG(0x0, DSP),
2432 MBOX_INC_SEL_EXTAR_REG(0x4, MSC_THR),
2433 MBOX_INC_SEL_EXTAR_REG(0x5, MSC_THR),
2434 MBOX_INC_SEL_EXTAR_REG(0x9, ISS),
2435 /* event 0xa uses two extra registers */
2436 MBOX_INC_SEL_EXTAR_REG(0xa, ISS),
2437 MBOX_INC_SEL_EXTAR_REG(0xa, PLD),
2438 MBOX_INC_SEL_EXTAR_REG(0xb, PLD),
2439 /* events 0xd ~ 0x10 use the same extra register */
2440 MBOX_INC_SEL_EXTAR_REG(0xd, ZDP_CTL_FVC),
2441 MBOX_INC_SEL_EXTAR_REG(0xe, ZDP_CTL_FVC),
2442 MBOX_INC_SEL_EXTAR_REG(0xf, ZDP_CTL_FVC),
2443 MBOX_INC_SEL_EXTAR_REG(0x10, ZDP_CTL_FVC),
2444 MBOX_INC_SEL_EXTAR_REG(0x16, PGT),
2445 MBOX_SET_FLAG_SEL_EXTRA_REG(0x0, DSP),
2446 MBOX_SET_FLAG_SEL_EXTRA_REG(0x1, ISS),
2447 MBOX_SET_FLAG_SEL_EXTRA_REG(0x5, PGT),
2448 MBOX_SET_FLAG_SEL_EXTRA_REG(0x6, MAP),
2449 EVENT_EXTRA_END
2450 };
2451
2452 /* Nehalem-EX or Westmere-EX ? */
2453 static bool uncore_nhmex;
2454
2455 static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)
2456 {
2457 struct intel_uncore_extra_reg *er;
2458 unsigned long flags;
2459 bool ret = false;
2460 u64 mask;
2461
2462 if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
2463 er = &box->shared_regs[idx];
2464 raw_spin_lock_irqsave(&er->lock, flags);
2465 if (!atomic_read(&er->ref) || er->config == config) {
2466 atomic_inc(&er->ref);
2467 er->config = config;
2468 ret = true;
2469 }
2470 raw_spin_unlock_irqrestore(&er->lock, flags);
2471
2472 return ret;
2473 }
2474 /*
2475 * The ZDP_CTL_FVC MSR has 4 fields which are used to control
2476 * events 0xd ~ 0x10. Besides these 4 fields, there are additional
2477 * fields which are shared.
2478 */
2479 idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2480 if (WARN_ON_ONCE(idx >= 4))
2481 return false;
2482
2483 /* mask of the shared fields */
2484 if (uncore_nhmex)
2485 mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK;
2486 else
2487 mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK;
2488 er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
2489
2490 raw_spin_lock_irqsave(&er->lock, flags);
2491 /* add mask of the non-shared field if it's in use */
2492 if (__BITS_VALUE(atomic_read(&er->ref), idx, 8)) {
2493 if (uncore_nhmex)
2494 mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2495 else
2496 mask |= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2497 }
2498
2499 if (!atomic_read(&er->ref) || !((er->config ^ config) & mask)) {
2500 atomic_add(1 << (idx * 8), &er->ref);
2501 if (uncore_nhmex)
2502 mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK |
2503 NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2504 else
2505 mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK |
2506 WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2507 er->config &= ~mask;
2508 er->config |= (config & mask);
2509 ret = true;
2510 }
2511 raw_spin_unlock_irqrestore(&er->lock, flags);
2512
2513 return ret;
2514 }
2515
2516 static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)
2517 {
2518 struct intel_uncore_extra_reg *er;
2519
2520 if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
2521 er = &box->shared_regs[idx];
2522 atomic_dec(&er->ref);
2523 return;
2524 }
2525
2526 idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2527 er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
2528 atomic_sub(1 << (idx * 8), &er->ref);
2529 }
2530
2531 static u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
2532 {
2533 struct hw_perf_event *hwc = &event->hw;
2534 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2535 u64 idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);
2536 u64 config = reg1->config;
2537
2538 /* get the non-shared control bits and shift them */
2539 idx = orig_idx - EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2540 if (uncore_nhmex)
2541 config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2542 else
2543 config &= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2544 if (new_idx > orig_idx) {
2545 idx = new_idx - orig_idx;
2546 config <<= 3 * idx;
2547 } else {
2548 idx = orig_idx - new_idx;
2549 config >>= 3 * idx;
2550 }
2551
2552 /* add the shared control bits back */
2553 if (uncore_nhmex)
2554 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
2555 else
2556 config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
2557 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
2558 if (modify) {
2559 /* adjust the main event selector */
2560 if (new_idx > orig_idx)
2561 hwc->config += idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
2562 else
2563 hwc->config -= idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
2564 reg1->config = config;
2565 reg1->idx = ~0xff | new_idx;
2566 }
2567 return config;
2568 }
2569
2570 static struct event_constraint *
2571 nhmex_mbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
2572 {
2573 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2574 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
2575 int i, idx[2], alloc = 0;
2576 u64 config1 = reg1->config;
2577
2578 idx[0] = __BITS_VALUE(reg1->idx, 0, 8);
2579 idx[1] = __BITS_VALUE(reg1->idx, 1, 8);
2580 again:
2581 for (i = 0; i < 2; i++) {
2582 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
2583 idx[i] = 0xff;
2584
2585 if (idx[i] == 0xff)
2586 continue;
2587
2588 if (!nhmex_mbox_get_shared_reg(box, idx[i],
2589 __BITS_VALUE(config1, i, 32)))
2590 goto fail;
2591 alloc |= (0x1 << i);
2592 }
2593
2594 /* for the match/mask registers */
2595 if (reg2->idx != EXTRA_REG_NONE &&
2596 (uncore_box_is_fake(box) || !reg2->alloc) &&
2597 !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))
2598 goto fail;
2599
2600 /*
2601 * If it's a fake box -- as per validate_{group,event}() we
2602 * shouldn't touch event state and we can avoid doing so
2603 * since both will only call get_event_constraints() once
2604 * on each event, this avoids the need for reg->alloc.
2605 */
2606 if (!uncore_box_is_fake(box)) {
2607 if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))
2608 nhmex_mbox_alter_er(event, idx[0], true);
2609 reg1->alloc |= alloc;
2610 if (reg2->idx != EXTRA_REG_NONE)
2611 reg2->alloc = 1;
2612 }
2613 return NULL;
2614 fail:
2615 if (idx[0] != 0xff && !(alloc & 0x1) &&
2616 idx[0] >= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
2617 /*
2618 * events 0xd ~ 0x10 are functional identical, but are
2619 * controlled by different fields in the ZDP_CTL_FVC
2620 * register. If we failed to take one field, try the
2621 * rest 3 choices.
2622 */
2623 BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff);
2624 idx[0] -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2625 idx[0] = (idx[0] + 1) % 4;
2626 idx[0] += EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2627 if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) {
2628 config1 = nhmex_mbox_alter_er(event, idx[0], false);
2629 goto again;
2630 }
2631 }
2632
2633 if (alloc & 0x1)
2634 nhmex_mbox_put_shared_reg(box, idx[0]);
2635 if (alloc & 0x2)
2636 nhmex_mbox_put_shared_reg(box, idx[1]);
2637 return &constraint_empty;
2638 }
2639
2640 static void nhmex_mbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
2641 {
2642 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2643 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
2644
2645 if (uncore_box_is_fake(box))
2646 return;
2647
2648 if (reg1->alloc & 0x1)
2649 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8));
2650 if (reg1->alloc & 0x2)
2651 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8));
2652 reg1->alloc = 0;
2653
2654 if (reg2->alloc) {
2655 nhmex_mbox_put_shared_reg(box, reg2->idx);
2656 reg2->alloc = 0;
2657 }
2658 }
2659
2660 static int nhmex_mbox_extra_reg_idx(struct extra_reg *er)
2661 {
2662 if (er->idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
2663 return er->idx;
2664 return er->idx + (er->event >> NHMEX_M_PMON_CTL_INC_SEL_SHIFT) - 0xd;
2665 }
2666
2667 static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2668 {
2669 struct intel_uncore_type *type = box->pmu->type;
2670 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2671 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
2672 struct extra_reg *er;
2673 unsigned msr;
2674 int reg_idx = 0;
2675 /*
2676 * The mbox events may require 2 extra MSRs at the most. But only
2677 * the lower 32 bits in these MSRs are significant, so we can use
2678 * config1 to pass two MSRs' config.
2679 */
2680 for (er = nhmex_uncore_mbox_extra_regs; er->msr; er++) {
2681 if (er->event != (event->hw.config & er->config_mask))
2682 continue;
2683 if (event->attr.config1 & ~er->valid_mask)
2684 return -EINVAL;
2685
2686 msr = er->msr + type->msr_offset * box->pmu->pmu_idx;
2687 if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))
2688 return -EINVAL;
2689
2690 /* always use the 32~63 bits to pass the PLD config */
2691 if (er->idx == EXTRA_REG_NHMEX_M_PLD)
2692 reg_idx = 1;
2693 else if (WARN_ON_ONCE(reg_idx > 0))
2694 return -EINVAL;
2695
2696 reg1->idx &= ~(0xff << (reg_idx * 8));
2697 reg1->reg &= ~(0xffff << (reg_idx * 16));
2698 reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8);
2699 reg1->reg |= msr << (reg_idx * 16);
2700 reg1->config = event->attr.config1;
2701 reg_idx++;
2702 }
2703 /*
2704 * The mbox only provides ability to perform address matching
2705 * for the PLD events.
2706 */
2707 if (reg_idx == 2) {
2708 reg2->idx = EXTRA_REG_NHMEX_M_FILTER;
2709 if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN)
2710 reg2->config = event->attr.config2;
2711 else
2712 reg2->config = ~0ULL;
2713 if (box->pmu->pmu_idx == 0)
2714 reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG;
2715 else
2716 reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG;
2717 }
2718 return 0;
2719 }
2720
2721 static u64 nhmex_mbox_shared_reg_config(struct intel_uncore_box *box, int idx)
2722 {
2723 struct intel_uncore_extra_reg *er;
2724 unsigned long flags;
2725 u64 config;
2726
2727 if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
2728 return box->shared_regs[idx].config;
2729
2730 er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
2731 raw_spin_lock_irqsave(&er->lock, flags);
2732 config = er->config;
2733 raw_spin_unlock_irqrestore(&er->lock, flags);
2734 return config;
2735 }
2736
2737 static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2738 {
2739 struct hw_perf_event *hwc = &event->hw;
2740 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2741 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2742 int idx;
2743
2744 idx = __BITS_VALUE(reg1->idx, 0, 8);
2745 if (idx != 0xff)
2746 wrmsrl(__BITS_VALUE(reg1->reg, 0, 16),
2747 nhmex_mbox_shared_reg_config(box, idx));
2748 idx = __BITS_VALUE(reg1->idx, 1, 8);
2749 if (idx != 0xff)
2750 wrmsrl(__BITS_VALUE(reg1->reg, 1, 16),
2751 nhmex_mbox_shared_reg_config(box, idx));
2752
2753 if (reg2->idx != EXTRA_REG_NONE) {
2754 wrmsrl(reg2->reg, 0);
2755 if (reg2->config != ~0ULL) {
2756 wrmsrl(reg2->reg + 1,
2757 reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK);
2758 wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK &
2759 (reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT));
2760 wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);
2761 }
2762 }
2763
2764 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
2765 }
2766
2767 DEFINE_UNCORE_FORMAT_ATTR(count_mode, count_mode, "config:2-3");
2768 DEFINE_UNCORE_FORMAT_ATTR(storage_mode, storage_mode, "config:4-5");
2769 DEFINE_UNCORE_FORMAT_ATTR(wrap_mode, wrap_mode, "config:6");
2770 DEFINE_UNCORE_FORMAT_ATTR(flag_mode, flag_mode, "config:7");
2771 DEFINE_UNCORE_FORMAT_ATTR(inc_sel, inc_sel, "config:9-13");
2772 DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel, set_flag_sel, "config:19-21");
2773 DEFINE_UNCORE_FORMAT_ATTR(filter_cfg_en, filter_cfg_en, "config2:63");
2774 DEFINE_UNCORE_FORMAT_ATTR(filter_match, filter_match, "config2:0-33");
2775 DEFINE_UNCORE_FORMAT_ATTR(filter_mask, filter_mask, "config2:34-61");
2776 DEFINE_UNCORE_FORMAT_ATTR(dsp, dsp, "config1:0-31");
2777 DEFINE_UNCORE_FORMAT_ATTR(thr, thr, "config1:0-31");
2778 DEFINE_UNCORE_FORMAT_ATTR(fvc, fvc, "config1:0-31");
2779 DEFINE_UNCORE_FORMAT_ATTR(pgt, pgt, "config1:0-31");
2780 DEFINE_UNCORE_FORMAT_ATTR(map, map, "config1:0-31");
2781 DEFINE_UNCORE_FORMAT_ATTR(iss, iss, "config1:0-31");
2782 DEFINE_UNCORE_FORMAT_ATTR(pld, pld, "config1:32-63");
2783
2784 static struct attribute *nhmex_uncore_mbox_formats_attr[] = {
2785 &format_attr_count_mode.attr,
2786 &format_attr_storage_mode.attr,
2787 &format_attr_wrap_mode.attr,
2788 &format_attr_flag_mode.attr,
2789 &format_attr_inc_sel.attr,
2790 &format_attr_set_flag_sel.attr,
2791 &format_attr_filter_cfg_en.attr,
2792 &format_attr_filter_match.attr,
2793 &format_attr_filter_mask.attr,
2794 &format_attr_dsp.attr,
2795 &format_attr_thr.attr,
2796 &format_attr_fvc.attr,
2797 &format_attr_pgt.attr,
2798 &format_attr_map.attr,
2799 &format_attr_iss.attr,
2800 &format_attr_pld.attr,
2801 NULL,
2802 };
2803
2804 static struct attribute_group nhmex_uncore_mbox_format_group = {
2805 .name = "format",
2806 .attrs = nhmex_uncore_mbox_formats_attr,
2807 };
2808
2809 static struct uncore_event_desc nhmex_uncore_mbox_events[] = {
2810 INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x2800"),
2811 INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x2820"),
2812 { /* end: all zeroes */ },
2813 };
2814
2815 static struct uncore_event_desc wsmex_uncore_mbox_events[] = {
2816 INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x5000"),
2817 INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x5040"),
2818 { /* end: all zeroes */ },
2819 };
2820
2821 static struct intel_uncore_ops nhmex_uncore_mbox_ops = {
2822 NHMEX_UNCORE_OPS_COMMON_INIT(),
2823 .enable_event = nhmex_mbox_msr_enable_event,
2824 .hw_config = nhmex_mbox_hw_config,
2825 .get_constraint = nhmex_mbox_get_constraint,
2826 .put_constraint = nhmex_mbox_put_constraint,
2827 };
2828
2829 static struct intel_uncore_type nhmex_uncore_mbox = {
2830 .name = "mbox",
2831 .num_counters = 6,
2832 .num_boxes = 2,
2833 .perf_ctr_bits = 48,
2834 .event_ctl = NHMEX_M0_MSR_PMU_CTL0,
2835 .perf_ctr = NHMEX_M0_MSR_PMU_CNT0,
2836 .event_mask = NHMEX_M_PMON_RAW_EVENT_MASK,
2837 .box_ctl = NHMEX_M0_MSR_GLOBAL_CTL,
2838 .msr_offset = NHMEX_M_MSR_OFFSET,
2839 .pair_ctr_ctl = 1,
2840 .num_shared_regs = 8,
2841 .event_descs = nhmex_uncore_mbox_events,
2842 .ops = &nhmex_uncore_mbox_ops,
2843 .format_group = &nhmex_uncore_mbox_format_group,
2844 };
2845
2846 static void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
2847 {
2848 struct hw_perf_event *hwc = &event->hw;
2849 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2850
2851 /* adjust the main event selector and extra register index */
2852 if (reg1->idx % 2) {
2853 reg1->idx--;
2854 hwc->config -= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
2855 } else {
2856 reg1->idx++;
2857 hwc->config += 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
2858 }
2859
2860 /* adjust extra register config */
2861 switch (reg1->idx % 6) {
2862 case 2:
2863 /* shift the 8~15 bits to the 0~7 bits */
2864 reg1->config >>= 8;
2865 break;
2866 case 3:
2867 /* shift the 0~7 bits to the 8~15 bits */
2868 reg1->config <<= 8;
2869 break;
2870 };
2871 }
2872
2873 /*
2874 * Each rbox has 4 event set which monitor PQI port 0~3 or 4~7.
2875 * An event set consists of 6 events, the 3rd and 4th events in
2876 * an event set use the same extra register. So an event set uses
2877 * 5 extra registers.
2878 */
2879 static struct event_constraint *
2880 nhmex_rbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
2881 {
2882 struct hw_perf_event *hwc = &event->hw;
2883 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2884 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2885 struct intel_uncore_extra_reg *er;
2886 unsigned long flags;
2887 int idx, er_idx;
2888 u64 config1;
2889 bool ok = false;
2890
2891 if (!uncore_box_is_fake(box) && reg1->alloc)
2892 return NULL;
2893
2894 idx = reg1->idx % 6;
2895 config1 = reg1->config;
2896 again:
2897 er_idx = idx;
2898 /* the 3rd and 4th events use the same extra register */
2899 if (er_idx > 2)
2900 er_idx--;
2901 er_idx += (reg1->idx / 6) * 5;
2902
2903 er = &box->shared_regs[er_idx];
2904 raw_spin_lock_irqsave(&er->lock, flags);
2905 if (idx < 2) {
2906 if (!atomic_read(&er->ref) || er->config == reg1->config) {
2907 atomic_inc(&er->ref);
2908 er->config = reg1->config;
2909 ok = true;
2910 }
2911 } else if (idx == 2 || idx == 3) {
2912 /*
2913 * these two events use different fields in a extra register,
2914 * the 0~7 bits and the 8~15 bits respectively.
2915 */
2916 u64 mask = 0xff << ((idx - 2) * 8);
2917 if (!__BITS_VALUE(atomic_read(&er->ref), idx - 2, 8) ||
2918 !((er->config ^ config1) & mask)) {
2919 atomic_add(1 << ((idx - 2) * 8), &er->ref);
2920 er->config &= ~mask;
2921 er->config |= config1 & mask;
2922 ok = true;
2923 }
2924 } else {
2925 if (!atomic_read(&er->ref) ||
2926 (er->config == (hwc->config >> 32) &&
2927 er->config1 == reg1->config &&
2928 er->config2 == reg2->config)) {
2929 atomic_inc(&er->ref);
2930 er->config = (hwc->config >> 32);
2931 er->config1 = reg1->config;
2932 er->config2 = reg2->config;
2933 ok = true;
2934 }
2935 }
2936 raw_spin_unlock_irqrestore(&er->lock, flags);
2937
2938 if (!ok) {
2939 /*
2940 * The Rbox events are always in pairs. The paired
2941 * events are functional identical, but use different
2942 * extra registers. If we failed to take an extra
2943 * register, try the alternative.
2944 */
2945 if (idx % 2)
2946 idx--;
2947 else
2948 idx++;
2949 if (idx != reg1->idx % 6) {
2950 if (idx == 2)
2951 config1 >>= 8;
2952 else if (idx == 3)
2953 config1 <<= 8;
2954 goto again;
2955 }
2956 } else {
2957 if (!uncore_box_is_fake(box)) {
2958 if (idx != reg1->idx % 6)
2959 nhmex_rbox_alter_er(box, event);
2960 reg1->alloc = 1;
2961 }
2962 return NULL;
2963 }
2964 return &constraint_empty;
2965 }
2966
2967 static void nhmex_rbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
2968 {
2969 struct intel_uncore_extra_reg *er;
2970 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2971 int idx, er_idx;
2972
2973 if (uncore_box_is_fake(box) || !reg1->alloc)
2974 return;
2975
2976 idx = reg1->idx % 6;
2977 er_idx = idx;
2978 if (er_idx > 2)
2979 er_idx--;
2980 er_idx += (reg1->idx / 6) * 5;
2981
2982 er = &box->shared_regs[er_idx];
2983 if (idx == 2 || idx == 3)
2984 atomic_sub(1 << ((idx - 2) * 8), &er->ref);
2985 else
2986 atomic_dec(&er->ref);
2987
2988 reg1->alloc = 0;
2989 }
2990
2991 static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2992 {
2993 struct hw_perf_event *hwc = &event->hw;
2994 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2995 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
2996 int idx;
2997
2998 idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >>
2999 NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
3000 if (idx >= 0x18)
3001 return -EINVAL;
3002
3003 reg1->idx = idx;
3004 reg1->config = event->attr.config1;
3005
3006 switch (idx % 6) {
3007 case 4:
3008 case 5:
3009 hwc->config |= event->attr.config & (~0ULL << 32);
3010 reg2->config = event->attr.config2;
3011 break;
3012 };
3013 return 0;
3014 }
3015
3016 static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
3017 {
3018 struct hw_perf_event *hwc = &event->hw;
3019 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
3020 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
3021 int idx, port;
3022
3023 idx = reg1->idx;
3024 port = idx / 6 + box->pmu->pmu_idx * 4;
3025
3026 switch (idx % 6) {
3027 case 0:
3028 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config);
3029 break;
3030 case 1:
3031 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config);
3032 break;
3033 case 2:
3034 case 3:
3035 wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port),
3036 uncore_shared_reg_config(box, 2 + (idx / 6) * 5));
3037 break;
3038 case 4:
3039 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),
3040 hwc->config >> 32);
3041 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config);
3042 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config);
3043 break;
3044 case 5:
3045 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port),
3046 hwc->config >> 32);
3047 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);
3048 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);
3049 break;
3050 };
3051
3052 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
3053 (hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
3054 }
3055
3056 DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config:32-63");
3057 DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config1:0-63");
3058 DEFINE_UNCORE_FORMAT_ATTR(xbr_mask, xbr_mask, "config2:0-63");
3059 DEFINE_UNCORE_FORMAT_ATTR(qlx_cfg, qlx_cfg, "config1:0-15");
3060 DEFINE_UNCORE_FORMAT_ATTR(iperf_cfg, iperf_cfg, "config1:0-31");
3061
3062 static struct attribute *nhmex_uncore_rbox_formats_attr[] = {
3063 &format_attr_event5.attr,
3064 &format_attr_xbr_mm_cfg.attr,
3065 &format_attr_xbr_match.attr,
3066 &format_attr_xbr_mask.attr,
3067 &format_attr_qlx_cfg.attr,
3068 &format_attr_iperf_cfg.attr,
3069 NULL,
3070 };
3071
3072 static struct attribute_group nhmex_uncore_rbox_format_group = {
3073 .name = "format",
3074 .attrs = nhmex_uncore_rbox_formats_attr,
3075 };
3076
3077 static struct uncore_event_desc nhmex_uncore_rbox_events[] = {
3078 INTEL_UNCORE_EVENT_DESC(qpi0_flit_send, "event=0x0,iperf_cfg=0x80000000"),
3079 INTEL_UNCORE_EVENT_DESC(qpi1_filt_send, "event=0x6,iperf_cfg=0x80000000"),
3080 INTEL_UNCORE_EVENT_DESC(qpi0_idle_filt, "event=0x0,iperf_cfg=0x40000000"),
3081 INTEL_UNCORE_EVENT_DESC(qpi1_idle_filt, "event=0x6,iperf_cfg=0x40000000"),
3082 INTEL_UNCORE_EVENT_DESC(qpi0_date_response, "event=0x0,iperf_cfg=0xc4"),
3083 INTEL_UNCORE_EVENT_DESC(qpi1_date_response, "event=0x6,iperf_cfg=0xc4"),
3084 { /* end: all zeroes */ },
3085 };
3086
3087 static struct intel_uncore_ops nhmex_uncore_rbox_ops = {
3088 NHMEX_UNCORE_OPS_COMMON_INIT(),
3089 .enable_event = nhmex_rbox_msr_enable_event,
3090 .hw_config = nhmex_rbox_hw_config,
3091 .get_constraint = nhmex_rbox_get_constraint,
3092 .put_constraint = nhmex_rbox_put_constraint,
3093 };
3094
3095 static struct intel_uncore_type nhmex_uncore_rbox = {
3096 .name = "rbox",
3097 .num_counters = 8,
3098 .num_boxes = 2,
3099 .perf_ctr_bits = 48,
3100 .event_ctl = NHMEX_R_MSR_PMON_CTL0,
3101 .perf_ctr = NHMEX_R_MSR_PMON_CNT0,
3102 .event_mask = NHMEX_R_PMON_RAW_EVENT_MASK,
3103 .box_ctl = NHMEX_R_MSR_GLOBAL_CTL,
3104 .msr_offset = NHMEX_R_MSR_OFFSET,
3105 .pair_ctr_ctl = 1,
3106 .num_shared_regs = 20,
3107 .event_descs = nhmex_uncore_rbox_events,
3108 .ops = &nhmex_uncore_rbox_ops,
3109 .format_group = &nhmex_uncore_rbox_format_group
3110 };
3111
3112 static struct intel_uncore_type *nhmex_msr_uncores[] = {
3113 &nhmex_uncore_ubox,
3114 &nhmex_uncore_cbox,
3115 &nhmex_uncore_bbox,
3116 &nhmex_uncore_sbox,
3117 &nhmex_uncore_mbox,
3118 &nhmex_uncore_rbox,
3119 &nhmex_uncore_wbox,
3120 NULL,
3121 };
3122 /* end of Nehalem-EX uncore support */
3123
3124 static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx)
3125 {
3126 struct hw_perf_event *hwc = &event->hw;
3127
3128 hwc->idx = idx;
3129 hwc->last_tag = ++box->tags[idx];
3130
3131 if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
3132 hwc->event_base = uncore_fixed_ctr(box);
3133 hwc->config_base = uncore_fixed_ctl(box);
3134 return;
3135 }
3136
3137 hwc->config_base = uncore_event_ctl(box, hwc->idx);
3138 hwc->event_base = uncore_perf_ctr(box, hwc->idx);
3139 }
3140
3141 static void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
3142 {
3143 u64 prev_count, new_count, delta;
3144 int shift;
3145
3146 if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
3147 shift = 64 - uncore_fixed_ctr_bits(box);
3148 else
3149 shift = 64 - uncore_perf_ctr_bits(box);
3150
3151 /* the hrtimer might modify the previous event value */
3152 again:
3153 prev_count = local64_read(&event->hw.prev_count);
3154 new_count = uncore_read_counter(box, event);
3155 if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
3156 goto again;
3157
3158 delta = (new_count << shift) - (prev_count << shift);
3159 delta >>= shift;
3160
3161 local64_add(delta, &event->count);
3162 }
3163
3164 /*
3165 * The overflow interrupt is unavailable for SandyBridge-EP, is broken
3166 * for SandyBridge. So we use hrtimer to periodically poll the counter
3167 * to avoid overflow.
3168 */
3169 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
3170 {
3171 struct intel_uncore_box *box;
3172 struct perf_event *event;
3173 unsigned long flags;
3174 int bit;
3175
3176 box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
3177 if (!box->n_active || box->cpu != smp_processor_id())
3178 return HRTIMER_NORESTART;
3179 /*
3180 * disable local interrupt to prevent uncore_pmu_event_start/stop
3181 * to interrupt the update process
3182 */
3183 local_irq_save(flags);
3184
3185 /*
3186 * handle boxes with an active event list as opposed to active
3187 * counters
3188 */
3189 list_for_each_entry(event, &box->active_list, active_entry) {
3190 uncore_perf_event_update(box, event);
3191 }
3192
3193 for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
3194 uncore_perf_event_update(box, box->events[bit]);
3195
3196 local_irq_restore(flags);
3197
3198 hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration));
3199 return HRTIMER_RESTART;
3200 }
3201
3202 static void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
3203 {
3204 __hrtimer_start_range_ns(&box->hrtimer,
3205 ns_to_ktime(box->hrtimer_duration), 0,
3206 HRTIMER_MODE_REL_PINNED, 0);
3207 }
3208
3209 static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
3210 {
3211 hrtimer_cancel(&box->hrtimer);
3212 }
3213
3214 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
3215 {
3216 hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3217 box->hrtimer.function = uncore_pmu_hrtimer;
3218 }
3219
3220 static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int node)
3221 {
3222 struct intel_uncore_box *box;
3223 int i, size;
3224
3225 size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg);
3226
3227 box = kzalloc_node(size, GFP_KERNEL, node);
3228 if (!box)
3229 return NULL;
3230
3231 for (i = 0; i < type->num_shared_regs; i++)
3232 raw_spin_lock_init(&box->shared_regs[i].lock);
3233
3234 uncore_pmu_init_hrtimer(box);
3235 atomic_set(&box->refcnt, 1);
3236 box->cpu = -1;
3237 box->phys_id = -1;
3238
3239 /* set default hrtimer timeout */
3240 box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
3241
3242 INIT_LIST_HEAD(&box->active_list);
3243
3244 return box;
3245 }
3246
3247 static int
3248 uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
3249 {
3250 struct perf_event *event;
3251 int n, max_count;
3252
3253 max_count = box->pmu->type->num_counters;
3254 if (box->pmu->type->fixed_ctl)
3255 max_count++;
3256
3257 if (box->n_events >= max_count)
3258 return -EINVAL;
3259
3260 n = box->n_events;
3261 box->event_list[n] = leader;
3262 n++;
3263 if (!dogrp)
3264 return n;
3265
3266 list_for_each_entry(event, &leader->sibling_list, group_entry) {
3267 if (event->state <= PERF_EVENT_STATE_OFF)
3268 continue;
3269
3270 if (n >= max_count)
3271 return -EINVAL;
3272
3273 box->event_list[n] = event;
3274 n++;
3275 }
3276 return n;
3277 }
3278
3279 static struct event_constraint *
3280 uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
3281 {
3282 struct intel_uncore_type *type = box->pmu->type;
3283 struct event_constraint *c;
3284
3285 if (type->ops->get_constraint) {
3286 c = type->ops->get_constraint(box, event);
3287 if (c)
3288 return c;
3289 }
3290
3291 if (event->attr.config == UNCORE_FIXED_EVENT)
3292 return &constraint_fixed;
3293
3294 if (type->constraints) {
3295 for_each_event_constraint(c, type->constraints) {
3296 if ((event->hw.config & c->cmask) == c->code)
3297 return c;
3298 }
3299 }
3300
3301 return &type->unconstrainted;
3302 }
3303
3304 static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
3305 {
3306 if (box->pmu->type->ops->put_constraint)
3307 box->pmu->type->ops->put_constraint(box, event);
3308 }
3309
3310 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
3311 {
3312 unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
3313 struct event_constraint *c;
3314 int i, wmin, wmax, ret = 0;
3315 struct hw_perf_event *hwc;
3316
3317 bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
3318
3319 for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
3320 hwc = &box->event_list[i]->hw;
3321 c = uncore_get_event_constraint(box, box->event_list[i]);
3322 hwc->constraint = c;
3323 wmin = min(wmin, c->weight);
3324 wmax = max(wmax, c->weight);
3325 }
3326
3327 /* fastpath, try to reuse previous register */
3328 for (i = 0; i < n; i++) {
3329 hwc = &box->event_list[i]->hw;
3330 c = hwc->constraint;
3331
3332 /* never assigned */
3333 if (hwc->idx == -1)
3334 break;
3335
3336 /* constraint still honored */
3337 if (!test_bit(hwc->idx, c->idxmsk))
3338 break;
3339
3340 /* not already used */
3341 if (test_bit(hwc->idx, used_mask))
3342 break;
3343
3344 __set_bit(hwc->idx, used_mask);
3345 if (assign)
3346 assign[i] = hwc->idx;
3347 }
3348 /* slow path */
3349 if (i != n)
3350 ret = perf_assign_events(box->event_list, n,
3351 wmin, wmax, assign);
3352
3353 if (!assign || ret) {
3354 for (i = 0; i < n; i++)
3355 uncore_put_event_constraint(box, box->event_list[i]);
3356 }
3357 return ret ? -EINVAL : 0;
3358 }
3359
3360 static void uncore_pmu_event_start(struct perf_event *event, int flags)
3361 {
3362 struct intel_uncore_box *box = uncore_event_to_box(event);
3363 int idx = event->hw.idx;
3364
3365 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
3366 return;
3367
3368 if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
3369 return;
3370
3371 event->hw.state = 0;
3372 box->events[idx] = event;
3373 box->n_active++;
3374 __set_bit(idx, box->active_mask);
3375
3376 local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
3377 uncore_enable_event(box, event);
3378
3379 if (box->n_active == 1) {
3380 uncore_enable_box(box);
3381 uncore_pmu_start_hrtimer(box);
3382 }
3383 }
3384
3385 static void uncore_pmu_event_stop(struct perf_event *event, int flags)
3386 {
3387 struct intel_uncore_box *box = uncore_event_to_box(event);
3388 struct hw_perf_event *hwc = &event->hw;
3389
3390 if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
3391 uncore_disable_event(box, event);
3392 box->n_active--;
3393 box->events[hwc->idx] = NULL;
3394 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
3395 hwc->state |= PERF_HES_STOPPED;
3396
3397 if (box->n_active == 0) {
3398 uncore_disable_box(box);
3399 uncore_pmu_cancel_hrtimer(box);
3400 }
3401 }
3402
3403 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
3404 /*
3405 * Drain the remaining delta count out of a event
3406 * that we are disabling:
3407 */
3408 uncore_perf_event_update(box, event);
3409 hwc->state |= PERF_HES_UPTODATE;
3410 }
3411 }
3412
3413 static int uncore_pmu_event_add(struct perf_event *event, int flags)
3414 {
3415 struct intel_uncore_box *box = uncore_event_to_box(event);
3416 struct hw_perf_event *hwc = &event->hw;
3417 int assign[UNCORE_PMC_IDX_MAX];
3418 int i, n, ret;
3419
3420 if (!box)
3421 return -ENODEV;
3422
3423 ret = n = uncore_collect_events(box, event, false);
3424 if (ret < 0)
3425 return ret;
3426
3427 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
3428 if (!(flags & PERF_EF_START))
3429 hwc->state |= PERF_HES_ARCH;
3430
3431 ret = uncore_assign_events(box, assign, n);
3432 if (ret)
3433 return ret;
3434
3435 /* save events moving to new counters */
3436 for (i = 0; i < box->n_events; i++) {
3437 event = box->event_list[i];
3438 hwc = &event->hw;
3439
3440 if (hwc->idx == assign[i] &&
3441 hwc->last_tag == box->tags[assign[i]])
3442 continue;
3443 /*
3444 * Ensure we don't accidentally enable a stopped
3445 * counter simply because we rescheduled.
3446 */
3447 if (hwc->state & PERF_HES_STOPPED)
3448 hwc->state |= PERF_HES_ARCH;
3449
3450 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
3451 }
3452
3453 /* reprogram moved events into new counters */
3454 for (i = 0; i < n; i++) {
3455 event = box->event_list[i];
3456 hwc = &event->hw;
3457
3458 if (hwc->idx != assign[i] ||
3459 hwc->last_tag != box->tags[assign[i]])
3460 uncore_assign_hw_event(box, event, assign[i]);
3461 else if (i < box->n_events)
3462 continue;
3463
3464 if (hwc->state & PERF_HES_ARCH)
3465 continue;
3466
3467 uncore_pmu_event_start(event, 0);
3468 }
3469 box->n_events = n;
3470
3471 return 0;
3472 }
3473
3474 static void uncore_pmu_event_del(struct perf_event *event, int flags)
3475 {
3476 struct intel_uncore_box *box = uncore_event_to_box(event);
3477 int i;
3478
3479 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
3480
3481 for (i = 0; i < box->n_events; i++) {
3482 if (event == box->event_list[i]) {
3483 uncore_put_event_constraint(box, event);
3484
3485 while (++i < box->n_events)
3486 box->event_list[i - 1] = box->event_list[i];
3487
3488 --box->n_events;
3489 break;
3490 }
3491 }
3492
3493 event->hw.idx = -1;
3494 event->hw.last_tag = ~0ULL;
3495 }
3496
3497 static void uncore_pmu_event_read(struct perf_event *event)
3498 {
3499 struct intel_uncore_box *box = uncore_event_to_box(event);
3500 uncore_perf_event_update(box, event);
3501 }
3502
3503 /*
3504 * validation ensures the group can be loaded onto the
3505 * PMU if it was the only group available.
3506 */
3507 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
3508 struct perf_event *event)
3509 {
3510 struct perf_event *leader = event->group_leader;
3511 struct intel_uncore_box *fake_box;
3512 int ret = -EINVAL, n;
3513
3514 fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
3515 if (!fake_box)
3516 return -ENOMEM;
3517
3518 fake_box->pmu = pmu;
3519 /*
3520 * the event is not yet connected with its
3521 * siblings therefore we must first collect
3522 * existing siblings, then add the new event
3523 * before we can simulate the scheduling
3524 */
3525 n = uncore_collect_events(fake_box, leader, true);
3526 if (n < 0)
3527 goto out;
3528
3529 fake_box->n_events = n;
3530 n = uncore_collect_events(fake_box, event, false);
3531 if (n < 0)
3532 goto out;
3533
3534 fake_box->n_events = n;
3535
3536 ret = uncore_assign_events(fake_box, NULL, n);
3537 out:
3538 kfree(fake_box);
3539 return ret;
3540 }
3541
3542 static int uncore_pmu_event_init(struct perf_event *event)
3543 {
3544 struct intel_uncore_pmu *pmu;
3545 struct intel_uncore_box *box;
3546 struct hw_perf_event *hwc = &event->hw;
3547 int ret;
3548
3549 if (event->attr.type != event->pmu->type)
3550 return -ENOENT;
3551
3552 pmu = uncore_event_to_pmu(event);
3553 /* no device found for this pmu */
3554 if (pmu->func_id < 0)
3555 return -ENOENT;
3556
3557 /*
3558 * Uncore PMU does measure at all privilege level all the time.
3559 * So it doesn't make sense to specify any exclude bits.
3560 */
3561 if (event->attr.exclude_user || event->attr.exclude_kernel ||
3562 event->attr.exclude_hv || event->attr.exclude_idle)
3563 return -EINVAL;
3564
3565 /* Sampling not supported yet */
3566 if (hwc->sample_period)
3567 return -EINVAL;
3568
3569 /*
3570 * Place all uncore events for a particular physical package
3571 * onto a single cpu
3572 */
3573 if (event->cpu < 0)
3574 return -EINVAL;
3575 box = uncore_pmu_to_box(pmu, event->cpu);
3576 if (!box || box->cpu < 0)
3577 return -EINVAL;
3578 event->cpu = box->cpu;
3579
3580 event->hw.idx = -1;
3581 event->hw.last_tag = ~0ULL;
3582 event->hw.extra_reg.idx = EXTRA_REG_NONE;
3583 event->hw.branch_reg.idx = EXTRA_REG_NONE;
3584
3585 if (event->attr.config == UNCORE_FIXED_EVENT) {
3586 /* no fixed counter */
3587 if (!pmu->type->fixed_ctl)
3588 return -EINVAL;
3589 /*
3590 * if there is only one fixed counter, only the first pmu
3591 * can access the fixed counter
3592 */
3593 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
3594 return -EINVAL;
3595
3596 /* fixed counters have event field hardcoded to zero */
3597 hwc->config = 0ULL;
3598 } else {
3599 hwc->config = event->attr.config & pmu->type->event_mask;
3600 if (pmu->type->ops->hw_config) {
3601 ret = pmu->type->ops->hw_config(box, event);
3602 if (ret)
3603 return ret;
3604 }
3605 }
3606
3607 if (event->group_leader != event)
3608 ret = uncore_validate_group(pmu, event);
3609 else
3610 ret = 0;
3611
3612 return ret;
3613 }
3614
3615 static ssize_t uncore_get_attr_cpumask(struct device *dev,
3616 struct device_attribute *attr, char *buf)
3617 {
3618 int n = cpulist_scnprintf(buf, PAGE_SIZE - 2, &uncore_cpu_mask);
3619
3620 buf[n++] = '\n';
3621 buf[n] = '\0';
3622 return n;
3623 }
3624
3625 static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL);
3626
3627 static struct attribute *uncore_pmu_attrs[] = {
3628 &dev_attr_cpumask.attr,
3629 NULL,
3630 };
3631
3632 static struct attribute_group uncore_pmu_attr_group = {
3633 .attrs = uncore_pmu_attrs,
3634 };
3635
3636 static int __init uncore_pmu_register(struct intel_uncore_pmu *pmu)
3637 {
3638 int ret;
3639
3640 if (!pmu->type->pmu) {
3641 pmu->pmu = (struct pmu) {
3642 .attr_groups = pmu->type->attr_groups,
3643 .task_ctx_nr = perf_invalid_context,
3644 .event_init = uncore_pmu_event_init,
3645 .add = uncore_pmu_event_add,
3646 .del = uncore_pmu_event_del,
3647 .start = uncore_pmu_event_start,
3648 .stop = uncore_pmu_event_stop,
3649 .read = uncore_pmu_event_read,
3650 };
3651 } else {
3652 pmu->pmu = *pmu->type->pmu;
3653 pmu->pmu.attr_groups = pmu->type->attr_groups;
3654 }
3655
3656 if (pmu->type->num_boxes == 1) {
3657 if (strlen(pmu->type->name) > 0)
3658 sprintf(pmu->name, "uncore_%s", pmu->type->name);
3659 else
3660 sprintf(pmu->name, "uncore");
3661 } else {
3662 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
3663 pmu->pmu_idx);
3664 }
3665
3666 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
3667 return ret;
3668 }
3669
3670 static void __init uncore_type_exit(struct intel_uncore_type *type)
3671 {
3672 int i;
3673
3674 for (i = 0; i < type->num_boxes; i++)
3675 free_percpu(type->pmus[i].box);
3676 kfree(type->pmus);
3677 type->pmus = NULL;
3678 kfree(type->events_group);
3679 type->events_group = NULL;
3680 }
3681
3682 static void __init uncore_types_exit(struct intel_uncore_type **types)
3683 {
3684 int i;
3685 for (i = 0; types[i]; i++)
3686 uncore_type_exit(types[i]);
3687 }
3688
3689 static int __init uncore_type_init(struct intel_uncore_type *type)
3690 {
3691 struct intel_uncore_pmu *pmus;
3692 struct attribute_group *attr_group;
3693 struct attribute **attrs;
3694 int i, j;
3695
3696 pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
3697 if (!pmus)
3698 return -ENOMEM;
3699
3700 type->unconstrainted = (struct event_constraint)
3701 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
3702 0, type->num_counters, 0, 0);
3703
3704 for (i = 0; i < type->num_boxes; i++) {
3705 pmus[i].func_id = -1;
3706 pmus[i].pmu_idx = i;
3707 pmus[i].type = type;
3708 INIT_LIST_HEAD(&pmus[i].box_list);
3709 pmus[i].box = alloc_percpu(struct intel_uncore_box *);
3710 if (!pmus[i].box)
3711 goto fail;
3712 }
3713
3714 if (type->event_descs) {
3715 i = 0;
3716 while (type->event_descs[i].attr.attr.name)
3717 i++;
3718
3719 attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
3720 sizeof(*attr_group), GFP_KERNEL);
3721 if (!attr_group)
3722 goto fail;
3723
3724 attrs = (struct attribute **)(attr_group + 1);
3725 attr_group->name = "events";
3726 attr_group->attrs = attrs;
3727
3728 for (j = 0; j < i; j++)
3729 attrs[j] = &type->event_descs[j].attr.attr;
3730
3731 type->events_group = attr_group;
3732 }
3733
3734 type->pmu_group = &uncore_pmu_attr_group;
3735 type->pmus = pmus;
3736 return 0;
3737 fail:
3738 uncore_type_exit(type);
3739 return -ENOMEM;
3740 }
3741
3742 static int __init uncore_types_init(struct intel_uncore_type **types)
3743 {
3744 int i, ret;
3745
3746 for (i = 0; types[i]; i++) {
3747 ret = uncore_type_init(types[i]);
3748 if (ret)
3749 goto fail;
3750 }
3751 return 0;
3752 fail:
3753 while (--i >= 0)
3754 uncore_type_exit(types[i]);
3755 return ret;
3756 }
3757
3758 static struct pci_driver *uncore_pci_driver;
3759 static bool pcidrv_registered;
3760
3761 /*
3762 * add a pci uncore device
3763 */
3764 static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3765 {
3766 struct intel_uncore_pmu *pmu;
3767 struct intel_uncore_box *box;
3768 struct intel_uncore_type *type;
3769 int phys_id;
3770
3771 phys_id = pcibus_to_physid[pdev->bus->number];
3772 if (phys_id < 0)
3773 return -ENODEV;
3774
3775 if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
3776 extra_pci_dev[phys_id][UNCORE_PCI_DEV_IDX(id->driver_data)] = pdev;
3777 pci_set_drvdata(pdev, NULL);
3778 return 0;
3779 }
3780
3781 type = pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
3782 box = uncore_alloc_box(type, NUMA_NO_NODE);
3783 if (!box)
3784 return -ENOMEM;
3785
3786 /*
3787 * for performance monitoring unit with multiple boxes,
3788 * each box has a different function id.
3789 */
3790 pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
3791 if (pmu->func_id < 0)
3792 pmu->func_id = pdev->devfn;
3793 else
3794 WARN_ON_ONCE(pmu->func_id != pdev->devfn);
3795
3796 box->phys_id = phys_id;
3797 box->pci_dev = pdev;
3798 box->pmu = pmu;
3799 uncore_box_init(box);
3800 pci_set_drvdata(pdev, box);
3801
3802 raw_spin_lock(&uncore_box_lock);
3803 list_add_tail(&box->list, &pmu->box_list);
3804 raw_spin_unlock(&uncore_box_lock);
3805
3806 return 0;
3807 }
3808
3809 static void uncore_pci_remove(struct pci_dev *pdev)
3810 {
3811 struct intel_uncore_box *box = pci_get_drvdata(pdev);
3812 struct intel_uncore_pmu *pmu;
3813 int i, cpu, phys_id = pcibus_to_physid[pdev->bus->number];
3814
3815 box = pci_get_drvdata(pdev);
3816 if (!box) {
3817 for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
3818 if (extra_pci_dev[phys_id][i] == pdev) {
3819 extra_pci_dev[phys_id][i] = NULL;
3820 break;
3821 }
3822 }
3823 WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX);
3824 return;
3825 }
3826
3827 pmu = box->pmu;
3828 if (WARN_ON_ONCE(phys_id != box->phys_id))
3829 return;
3830
3831 pci_set_drvdata(pdev, NULL);
3832
3833 raw_spin_lock(&uncore_box_lock);
3834 list_del(&box->list);
3835 raw_spin_unlock(&uncore_box_lock);
3836
3837 for_each_possible_cpu(cpu) {
3838 if (*per_cpu_ptr(pmu->box, cpu) == box) {
3839 *per_cpu_ptr(pmu->box, cpu) = NULL;
3840 atomic_dec(&box->refcnt);
3841 }
3842 }
3843
3844 WARN_ON_ONCE(atomic_read(&box->refcnt) != 1);
3845 kfree(box);
3846 }
3847
3848 static int __init uncore_pci_init(void)
3849 {
3850 int ret;
3851
3852 switch (boot_cpu_data.x86_model) {
3853 case 45: /* Sandy Bridge-EP */
3854 ret = snbep_pci2phy_map_init(0x3ce0);
3855 if (ret)
3856 return ret;
3857 pci_uncores = snbep_pci_uncores;
3858 uncore_pci_driver = &snbep_uncore_pci_driver;
3859 break;
3860 case 62: /* IvyTown */
3861 ret = snbep_pci2phy_map_init(0x0e1e);
3862 if (ret)
3863 return ret;
3864 pci_uncores = ivt_pci_uncores;
3865 uncore_pci_driver = &ivt_uncore_pci_driver;
3866 break;
3867 case 42: /* Sandy Bridge */
3868 ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_SNB_IMC);
3869 if (ret)
3870 return ret;
3871 pci_uncores = snb_pci_uncores;
3872 uncore_pci_driver = &snb_uncore_pci_driver;
3873 break;
3874 case 58: /* Ivy Bridge */
3875 ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_IVB_IMC);
3876 if (ret)
3877 return ret;
3878 pci_uncores = snb_pci_uncores;
3879 uncore_pci_driver = &ivb_uncore_pci_driver;
3880 break;
3881 case 60: /* Haswell */
3882 case 69: /* Haswell Celeron */
3883 ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_HSW_IMC);
3884 if (ret)
3885 return ret;
3886 pci_uncores = snb_pci_uncores;
3887 uncore_pci_driver = &hsw_uncore_pci_driver;
3888 break;
3889 default:
3890 return 0;
3891 }
3892
3893 ret = uncore_types_init(pci_uncores);
3894 if (ret)
3895 return ret;
3896
3897 uncore_pci_driver->probe = uncore_pci_probe;
3898 uncore_pci_driver->remove = uncore_pci_remove;
3899
3900 ret = pci_register_driver(uncore_pci_driver);
3901 if (ret == 0)
3902 pcidrv_registered = true;
3903 else
3904 uncore_types_exit(pci_uncores);
3905
3906 return ret;
3907 }
3908
3909 static void __init uncore_pci_exit(void)
3910 {
3911 if (pcidrv_registered) {
3912 pcidrv_registered = false;
3913 pci_unregister_driver(uncore_pci_driver);
3914 uncore_types_exit(pci_uncores);
3915 }
3916 }
3917
3918 /* CPU hot plug/unplug are serialized by cpu_add_remove_lock mutex */
3919 static LIST_HEAD(boxes_to_free);
3920
3921 static void uncore_kfree_boxes(void)
3922 {
3923 struct intel_uncore_box *box;
3924
3925 while (!list_empty(&boxes_to_free)) {
3926 box = list_entry(boxes_to_free.next,
3927 struct intel_uncore_box, list);
3928 list_del(&box->list);
3929 kfree(box);
3930 }
3931 }
3932
3933 static void uncore_cpu_dying(int cpu)
3934 {
3935 struct intel_uncore_type *type;
3936 struct intel_uncore_pmu *pmu;
3937 struct intel_uncore_box *box;
3938 int i, j;
3939
3940 for (i = 0; msr_uncores[i]; i++) {
3941 type = msr_uncores[i];
3942 for (j = 0; j < type->num_boxes; j++) {
3943 pmu = &type->pmus[j];
3944 box = *per_cpu_ptr(pmu->box, cpu);
3945 *per_cpu_ptr(pmu->box, cpu) = NULL;
3946 if (box && atomic_dec_and_test(&box->refcnt))
3947 list_add(&box->list, &boxes_to_free);
3948 }
3949 }
3950 }
3951
3952 static int uncore_cpu_starting(int cpu)
3953 {
3954 struct intel_uncore_type *type;
3955 struct intel_uncore_pmu *pmu;
3956 struct intel_uncore_box *box, *exist;
3957 int i, j, k, phys_id;
3958
3959 phys_id = topology_physical_package_id(cpu);
3960
3961 for (i = 0; msr_uncores[i]; i++) {
3962 type = msr_uncores[i];
3963 for (j = 0; j < type->num_boxes; j++) {
3964 pmu = &type->pmus[j];
3965 box = *per_cpu_ptr(pmu->box, cpu);
3966 /* called by uncore_cpu_init? */
3967 if (box && box->phys_id >= 0) {
3968 uncore_box_init(box);
3969 continue;
3970 }
3971
3972 for_each_online_cpu(k) {
3973 exist = *per_cpu_ptr(pmu->box, k);
3974 if (exist && exist->phys_id == phys_id) {
3975 atomic_inc(&exist->refcnt);
3976 *per_cpu_ptr(pmu->box, cpu) = exist;
3977 if (box) {
3978 list_add(&box->list,
3979 &boxes_to_free);
3980 box = NULL;
3981 }
3982 break;
3983 }
3984 }
3985
3986 if (box) {
3987 box->phys_id = phys_id;
3988 uncore_box_init(box);
3989 }
3990 }
3991 }
3992 return 0;
3993 }
3994
3995 static int uncore_cpu_prepare(int cpu, int phys_id)
3996 {
3997 struct intel_uncore_type *type;
3998 struct intel_uncore_pmu *pmu;
3999 struct intel_uncore_box *box;
4000 int i, j;
4001
4002 for (i = 0; msr_uncores[i]; i++) {
4003 type = msr_uncores[i];
4004 for (j = 0; j < type->num_boxes; j++) {
4005 pmu = &type->pmus[j];
4006 if (pmu->func_id < 0)
4007 pmu->func_id = j;
4008
4009 box = uncore_alloc_box(type, cpu_to_node(cpu));
4010 if (!box)
4011 return -ENOMEM;
4012
4013 box->pmu = pmu;
4014 box->phys_id = phys_id;
4015 *per_cpu_ptr(pmu->box, cpu) = box;
4016 }
4017 }
4018 return 0;
4019 }
4020
4021 static void
4022 uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu)
4023 {
4024 struct intel_uncore_type *type;
4025 struct intel_uncore_pmu *pmu;
4026 struct intel_uncore_box *box;
4027 int i, j;
4028
4029 for (i = 0; uncores[i]; i++) {
4030 type = uncores[i];
4031 for (j = 0; j < type->num_boxes; j++) {
4032 pmu = &type->pmus[j];
4033 if (old_cpu < 0)
4034 box = uncore_pmu_to_box(pmu, new_cpu);
4035 else
4036 box = uncore_pmu_to_box(pmu, old_cpu);
4037 if (!box)
4038 continue;
4039
4040 if (old_cpu < 0) {
4041 WARN_ON_ONCE(box->cpu != -1);
4042 box->cpu = new_cpu;
4043 continue;
4044 }
4045
4046 WARN_ON_ONCE(box->cpu != old_cpu);
4047 if (new_cpu >= 0) {
4048 uncore_pmu_cancel_hrtimer(box);
4049 perf_pmu_migrate_context(&pmu->pmu,
4050 old_cpu, new_cpu);
4051 box->cpu = new_cpu;
4052 } else {
4053 box->cpu = -1;
4054 }
4055 }
4056 }
4057 }
4058
4059 static void uncore_event_exit_cpu(int cpu)
4060 {
4061 int i, phys_id, target;
4062
4063 /* if exiting cpu is used for collecting uncore events */
4064 if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
4065 return;
4066
4067 /* find a new cpu to collect uncore events */
4068 phys_id = topology_physical_package_id(cpu);
4069 target = -1;
4070 for_each_online_cpu(i) {
4071 if (i == cpu)
4072 continue;
4073 if (phys_id == topology_physical_package_id(i)) {
4074 target = i;
4075 break;
4076 }
4077 }
4078
4079 /* migrate uncore events to the new cpu */
4080 if (target >= 0)
4081 cpumask_set_cpu(target, &uncore_cpu_mask);
4082
4083 uncore_change_context(msr_uncores, cpu, target);
4084 uncore_change_context(pci_uncores, cpu, target);
4085 }
4086
4087 static void uncore_event_init_cpu(int cpu)
4088 {
4089 int i, phys_id;
4090
4091 phys_id = topology_physical_package_id(cpu);
4092 for_each_cpu(i, &uncore_cpu_mask) {
4093 if (phys_id == topology_physical_package_id(i))
4094 return;
4095 }
4096
4097 cpumask_set_cpu(cpu, &uncore_cpu_mask);
4098
4099 uncore_change_context(msr_uncores, -1, cpu);
4100 uncore_change_context(pci_uncores, -1, cpu);
4101 }
4102
4103 static int uncore_cpu_notifier(struct notifier_block *self,
4104 unsigned long action, void *hcpu)
4105 {
4106 unsigned int cpu = (long)hcpu;
4107
4108 /* allocate/free data structure for uncore box */
4109 switch (action & ~CPU_TASKS_FROZEN) {
4110 case CPU_UP_PREPARE:
4111 uncore_cpu_prepare(cpu, -1);
4112 break;
4113 case CPU_STARTING:
4114 uncore_cpu_starting(cpu);
4115 break;
4116 case CPU_UP_CANCELED:
4117 case CPU_DYING:
4118 uncore_cpu_dying(cpu);
4119 break;
4120 case CPU_ONLINE:
4121 case CPU_DEAD:
4122 uncore_kfree_boxes();
4123 break;
4124 default:
4125 break;
4126 }
4127
4128 /* select the cpu that collects uncore events */
4129 switch (action & ~CPU_TASKS_FROZEN) {
4130 case CPU_DOWN_FAILED:
4131 case CPU_STARTING:
4132 uncore_event_init_cpu(cpu);
4133 break;
4134 case CPU_DOWN_PREPARE:
4135 uncore_event_exit_cpu(cpu);
4136 break;
4137 default:
4138 break;
4139 }
4140
4141 return NOTIFY_OK;
4142 }
4143
4144 static struct notifier_block uncore_cpu_nb = {
4145 .notifier_call = uncore_cpu_notifier,
4146 /*
4147 * to migrate uncore events, our notifier should be executed
4148 * before perf core's notifier.
4149 */
4150 .priority = CPU_PRI_PERF + 1,
4151 };
4152
4153 static void __init uncore_cpu_setup(void *dummy)
4154 {
4155 uncore_cpu_starting(smp_processor_id());
4156 }
4157
4158 static int __init uncore_cpu_init(void)
4159 {
4160 int ret, max_cores;
4161
4162 max_cores = boot_cpu_data.x86_max_cores;
4163 switch (boot_cpu_data.x86_model) {
4164 case 26: /* Nehalem */
4165 case 30:
4166 case 37: /* Westmere */
4167 case 44:
4168 msr_uncores = nhm_msr_uncores;
4169 break;
4170 case 42: /* Sandy Bridge */
4171 case 58: /* Ivy Bridge */
4172 if (snb_uncore_cbox.num_boxes > max_cores)
4173 snb_uncore_cbox.num_boxes = max_cores;
4174 msr_uncores = snb_msr_uncores;
4175 break;
4176 case 45: /* Sandy Bridge-EP */
4177 if (snbep_uncore_cbox.num_boxes > max_cores)
4178 snbep_uncore_cbox.num_boxes = max_cores;
4179 msr_uncores = snbep_msr_uncores;
4180 break;
4181 case 46: /* Nehalem-EX */
4182 uncore_nhmex = true;
4183 case 47: /* Westmere-EX aka. Xeon E7 */
4184 if (!uncore_nhmex)
4185 nhmex_uncore_mbox.event_descs = wsmex_uncore_mbox_events;
4186 if (nhmex_uncore_cbox.num_boxes > max_cores)
4187 nhmex_uncore_cbox.num_boxes = max_cores;
4188 msr_uncores = nhmex_msr_uncores;
4189 break;
4190 case 62: /* IvyTown */
4191 if (ivt_uncore_cbox.num_boxes > max_cores)
4192 ivt_uncore_cbox.num_boxes = max_cores;
4193 msr_uncores = ivt_msr_uncores;
4194 break;
4195
4196 default:
4197 return 0;
4198 }
4199
4200 ret = uncore_types_init(msr_uncores);
4201 if (ret)
4202 return ret;
4203
4204 return 0;
4205 }
4206
4207 static int __init uncore_pmus_register(void)
4208 {
4209 struct intel_uncore_pmu *pmu;
4210 struct intel_uncore_type *type;
4211 int i, j;
4212
4213 for (i = 0; msr_uncores[i]; i++) {
4214 type = msr_uncores[i];
4215 for (j = 0; j < type->num_boxes; j++) {
4216 pmu = &type->pmus[j];
4217 uncore_pmu_register(pmu);
4218 }
4219 }
4220
4221 for (i = 0; pci_uncores[i]; i++) {
4222 type = pci_uncores[i];
4223 for (j = 0; j < type->num_boxes; j++) {
4224 pmu = &type->pmus[j];
4225 uncore_pmu_register(pmu);
4226 }
4227 }
4228
4229 return 0;
4230 }
4231
4232 static void __init uncore_cpumask_init(void)
4233 {
4234 int cpu;
4235
4236 /*
4237 * ony invoke once from msr or pci init code
4238 */
4239 if (!cpumask_empty(&uncore_cpu_mask))
4240 return;
4241
4242 get_online_cpus();
4243
4244 for_each_online_cpu(cpu) {
4245 int i, phys_id = topology_physical_package_id(cpu);
4246
4247 for_each_cpu(i, &uncore_cpu_mask) {
4248 if (phys_id == topology_physical_package_id(i)) {
4249 phys_id = -1;
4250 break;
4251 }
4252 }
4253 if (phys_id < 0)
4254 continue;
4255
4256 uncore_cpu_prepare(cpu, phys_id);
4257 uncore_event_init_cpu(cpu);
4258 }
4259 on_each_cpu(uncore_cpu_setup, NULL, 1);
4260
4261 register_cpu_notifier(&uncore_cpu_nb);
4262
4263 put_online_cpus();
4264 }
4265
4266
4267 static int __init intel_uncore_init(void)
4268 {
4269 int ret;
4270
4271 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
4272 return -ENODEV;
4273
4274 if (cpu_has_hypervisor)
4275 return -ENODEV;
4276
4277 ret = uncore_pci_init();
4278 if (ret)
4279 goto fail;
4280 ret = uncore_cpu_init();
4281 if (ret) {
4282 uncore_pci_exit();
4283 goto fail;
4284 }
4285 uncore_cpumask_init();
4286
4287 uncore_pmus_register();
4288 return 0;
4289 fail:
4290 return ret;
4291 }
4292 device_initcall(intel_uncore_init);
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