1 /* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/pci_ids.h>
15 #include <drm/i915_drm.h>
16 #include <asm/pci-direct.h>
18 #include <asm/io_apic.h>
20 #include <asm/iommu.h>
22 #include <asm/irq_remapping.h>
24 static void __init
fix_hypertransport_config(int num
, int slot
, int func
)
28 * we found a hypertransport bus
29 * make sure that we are broadcasting
30 * interrupts to all cpus on the ht bus
31 * if we're using extended apic ids
33 htcfg
= read_pci_config(num
, slot
, func
, 0x68);
34 if (htcfg
& (1 << 18)) {
35 printk(KERN_INFO
"Detected use of extended apic ids "
36 "on hypertransport bus\n");
37 if ((htcfg
& (1 << 17)) == 0) {
38 printk(KERN_INFO
"Enabling hypertransport extended "
39 "apic interrupt broadcast\n");
40 printk(KERN_INFO
"Note this is a bios bug, "
41 "please contact your hw vendor\n");
43 write_pci_config(num
, slot
, func
, 0x68, htcfg
);
50 static void __init
via_bugs(int num
, int slot
, int func
)
52 #ifdef CONFIG_GART_IOMMU
53 if ((max_pfn
> MAX_DMA32_PFN
|| force_iommu
) &&
54 !gart_iommu_aperture_allowed
) {
56 "Looks like a VIA chipset. Disabling IOMMU."
57 " Override with iommu=allowed\n");
58 gart_iommu_aperture_disabled
= 1;
64 #ifdef CONFIG_X86_IO_APIC
66 static int __init
nvidia_hpet_check(struct acpi_table_header
*header
)
70 #endif /* CONFIG_X86_IO_APIC */
71 #endif /* CONFIG_ACPI */
73 static void __init
nvidia_bugs(int num
, int slot
, int func
)
76 #ifdef CONFIG_X86_IO_APIC
78 * All timer overrides on Nvidia are
79 * wrong unless HPET is enabled.
80 * Unfortunately that's not true on many Asus boards.
81 * We don't know yet how to detect this automatically, but
82 * at least allow a command line override.
84 if (acpi_use_timer_override
)
87 if (acpi_table_parse(ACPI_SIG_HPET
, nvidia_hpet_check
)) {
88 acpi_skip_timer_override
= 1;
89 printk(KERN_INFO
"Nvidia board "
90 "detected. Ignoring ACPI "
92 printk(KERN_INFO
"If you got timer trouble "
93 "try acpi_use_timer_override\n");
97 /* RED-PEN skip them on mptables too? */
101 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
102 static u32 __init
ati_ixp4x0_rev(int num
, int slot
, int func
)
107 b
= read_pci_config_byte(num
, slot
, func
, 0xac);
109 write_pci_config_byte(num
, slot
, func
, 0xac, b
);
111 d
= read_pci_config(num
, slot
, func
, 0x70);
113 write_pci_config(num
, slot
, func
, 0x70, d
);
115 d
= read_pci_config(num
, slot
, func
, 0x8);
120 static void __init
ati_bugs(int num
, int slot
, int func
)
125 if (acpi_use_timer_override
)
128 d
= ati_ixp4x0_rev(num
, slot
, func
);
130 acpi_skip_timer_override
= 1;
132 /* check for IRQ0 interrupt swap */
133 outb(0x72, 0xcd6); b
= inb(0xcd7);
135 acpi_skip_timer_override
= 1;
138 if (acpi_skip_timer_override
) {
139 printk(KERN_INFO
"SB4X0 revision 0x%x\n", d
);
140 printk(KERN_INFO
"Ignoring ACPI timer override.\n");
141 printk(KERN_INFO
"If you got timer trouble "
142 "try acpi_use_timer_override\n");
146 static u32 __init
ati_sbx00_rev(int num
, int slot
, int func
)
150 d
= read_pci_config(num
, slot
, func
, 0x8);
156 static void __init
ati_bugs_contd(int num
, int slot
, int func
)
160 rev
= ati_sbx00_rev(num
, slot
, func
);
162 acpi_fix_pin2_polarity
= 1;
165 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
166 * SB700: revisions 0x39, 0x3a, ...
167 * SB800: revisions 0x40, 0x41, ...
172 if (acpi_use_timer_override
)
175 /* check for IRQ0 interrupt swap */
176 d
= read_pci_config(num
, slot
, func
, 0x64);
178 acpi_skip_timer_override
= 1;
180 if (acpi_skip_timer_override
) {
181 printk(KERN_INFO
"SB600 revision 0x%x\n", rev
);
182 printk(KERN_INFO
"Ignoring ACPI timer override.\n");
183 printk(KERN_INFO
"If you got timer trouble "
184 "try acpi_use_timer_override\n");
188 static void __init
ati_bugs(int num
, int slot
, int func
)
192 static void __init
ati_bugs_contd(int num
, int slot
, int func
)
197 static void __init
intel_remapping_check(int num
, int slot
, int func
)
202 device
= read_pci_config_16(num
, slot
, func
, PCI_DEVICE_ID
);
203 revision
= read_pci_config_byte(num
, slot
, func
, PCI_REVISION_ID
);
206 * Revision <= 13 of all triggering devices id in this quirk
207 * have a problem draining interrupts when irq remapping is
208 * enabled, and should be flagged as broken. Additionally
209 * revision 0x22 of device id 0x3405 has this problem.
211 if (revision
<= 0x13)
212 set_irq_remapping_broken();
213 else if (device
== 0x3405 && revision
== 0x22)
214 set_irq_remapping_broken();
218 * Systems with Intel graphics controllers set aside memory exclusively
219 * for gfx driver use. This memory is not marked in the E820 as reserved
220 * or as RAM, and so is subject to overlap from E820 manipulation later
221 * in the boot process. On some systems, MMIO space is allocated on top,
222 * despite the efforts of the "RAM buffer" approach, which simply rounds
223 * memory boundaries up to 64M to try to catch space that may decode
224 * as RAM and so is not suitable for MMIO.
226 * And yes, so far on current devices the base addr is always under 4G.
228 static u32 __init
intel_stolen_base(int num
, int slot
, int func
, size_t stolen_size
)
233 * For the PCI IDs in this quirk, the stolen base is always
234 * in 0x5c, aka the BDSM register (yes that's really what
237 base
= read_pci_config(num
, slot
, func
, 0x5c);
238 base
&= ~((1<<20) - 1);
243 #define KB(x) ((x) * 1024)
244 #define MB(x) (KB (KB (x)))
245 #define GB(x) (MB (KB (x)))
247 static size_t __init
i830_tseg_size(void)
249 u8 tmp
= read_pci_config_byte(0, 0, 0, I830_ESMRAMC
);
251 if (!(tmp
& TSEG_ENABLE
))
254 if (tmp
& I830_TSEG_SIZE_1M
)
260 static size_t __init
i845_tseg_size(void)
262 u8 tmp
= read_pci_config_byte(0, 0, 0, I845_ESMRAMC
);
264 if (!(tmp
& TSEG_ENABLE
))
267 switch (tmp
& I845_TSEG_SIZE_MASK
) {
268 case I845_TSEG_SIZE_512K
:
270 case I845_TSEG_SIZE_1M
:
278 static size_t __init
i85x_tseg_size(void)
280 u8 tmp
= read_pci_config_byte(0, 0, 0, I85X_ESMRAMC
);
282 if (!(tmp
& TSEG_ENABLE
))
288 static size_t __init
i830_mem_size(void)
290 return read_pci_config_byte(0, 0, 0, I830_DRB3
) * MB(32);
293 static size_t __init
i85x_mem_size(void)
295 return read_pci_config_byte(0, 0, 1, I85X_DRB3
) * MB(32);
299 * On 830/845/85x the stolen memory base isn't available in any
300 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
302 static u32 __init
i830_stolen_base(int num
, int slot
, int func
, size_t stolen_size
)
304 return i830_mem_size() - i830_tseg_size() - stolen_size
;
307 static u32 __init
i845_stolen_base(int num
, int slot
, int func
, size_t stolen_size
)
309 return i830_mem_size() - i845_tseg_size() - stolen_size
;
312 static u32 __init
i85x_stolen_base(int num
, int slot
, int func
, size_t stolen_size
)
314 return i85x_mem_size() - i85x_tseg_size() - stolen_size
;
317 static u32 __init
i865_stolen_base(int num
, int slot
, int func
, size_t stolen_size
)
320 * FIXME is the graphics stolen memory region
321 * always at TOUD? Ie. is it always the last
322 * one to be allocated by the BIOS?
324 return read_pci_config_16(0, 0, 0, I865_TOUD
) << 16;
327 static size_t __init
i830_stolen_size(int num
, int slot
, int func
)
332 gmch_ctrl
= read_pci_config_16(0, 0, 0, I830_GMCH_CTRL
);
334 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
335 case I830_GMCH_GMS_STOLEN_512
:
336 stolen_size
= KB(512);
338 case I830_GMCH_GMS_STOLEN_1024
:
341 case I830_GMCH_GMS_STOLEN_8192
:
344 case I830_GMCH_GMS_LOCAL
:
345 /* local memory isn't part of the normal address space */
355 static size_t __init
gen3_stolen_size(int num
, int slot
, int func
)
360 gmch_ctrl
= read_pci_config_16(0, 0, 0, I830_GMCH_CTRL
);
362 switch (gmch_ctrl
& I855_GMCH_GMS_MASK
) {
363 case I855_GMCH_GMS_STOLEN_1M
:
366 case I855_GMCH_GMS_STOLEN_4M
:
369 case I855_GMCH_GMS_STOLEN_8M
:
372 case I855_GMCH_GMS_STOLEN_16M
:
373 stolen_size
= MB(16);
375 case I855_GMCH_GMS_STOLEN_32M
:
376 stolen_size
= MB(32);
378 case I915_GMCH_GMS_STOLEN_48M
:
379 stolen_size
= MB(48);
381 case I915_GMCH_GMS_STOLEN_64M
:
382 stolen_size
= MB(64);
384 case G33_GMCH_GMS_STOLEN_128M
:
385 stolen_size
= MB(128);
387 case G33_GMCH_GMS_STOLEN_256M
:
388 stolen_size
= MB(256);
390 case INTEL_GMCH_GMS_STOLEN_96M
:
391 stolen_size
= MB(96);
393 case INTEL_GMCH_GMS_STOLEN_160M
:
394 stolen_size
= MB(160);
396 case INTEL_GMCH_GMS_STOLEN_224M
:
397 stolen_size
= MB(224);
399 case INTEL_GMCH_GMS_STOLEN_352M
:
400 stolen_size
= MB(352);
410 static size_t __init
gen6_stolen_size(int num
, int slot
, int func
)
414 gmch_ctrl
= read_pci_config_16(num
, slot
, func
, SNB_GMCH_CTRL
);
415 gmch_ctrl
>>= SNB_GMCH_GMS_SHIFT
;
416 gmch_ctrl
&= SNB_GMCH_GMS_MASK
;
418 return gmch_ctrl
<< 25; /* 32 MB units */
421 static size_t gen8_stolen_size(int num
, int slot
, int func
)
425 gmch_ctrl
= read_pci_config_16(num
, slot
, func
, SNB_GMCH_CTRL
);
426 gmch_ctrl
>>= BDW_GMCH_GMS_SHIFT
;
427 gmch_ctrl
&= BDW_GMCH_GMS_MASK
;
428 return gmch_ctrl
<< 25; /* 32 MB units */
432 struct intel_stolen_funcs
{
433 size_t (*size
)(int num
, int slot
, int func
);
434 u32 (*base
)(int num
, int slot
, int func
, size_t size
);
437 static const struct intel_stolen_funcs i830_stolen_funcs
= {
438 .base
= i830_stolen_base
,
439 .size
= i830_stolen_size
,
442 static const struct intel_stolen_funcs i845_stolen_funcs
= {
443 .base
= i845_stolen_base
,
444 .size
= i830_stolen_size
,
447 static const struct intel_stolen_funcs i85x_stolen_funcs
= {
448 .base
= i85x_stolen_base
,
449 .size
= gen3_stolen_size
,
452 static const struct intel_stolen_funcs i865_stolen_funcs
= {
453 .base
= i865_stolen_base
,
454 .size
= gen3_stolen_size
,
457 static const struct intel_stolen_funcs gen3_stolen_funcs
= {
458 .base
= intel_stolen_base
,
459 .size
= gen3_stolen_size
,
462 static const struct intel_stolen_funcs gen6_stolen_funcs
= {
463 .base
= intel_stolen_base
,
464 .size
= gen6_stolen_size
,
467 static const struct intel_stolen_funcs gen8_stolen_funcs
= {
468 .base
= intel_stolen_base
,
469 .size
= gen8_stolen_size
,
472 static struct pci_device_id intel_stolen_ids
[] __initdata
= {
473 INTEL_I830_IDS(&i830_stolen_funcs
),
474 INTEL_I845G_IDS(&i845_stolen_funcs
),
475 INTEL_I85X_IDS(&i85x_stolen_funcs
),
476 INTEL_I865G_IDS(&i865_stolen_funcs
),
477 INTEL_I915G_IDS(&gen3_stolen_funcs
),
478 INTEL_I915GM_IDS(&gen3_stolen_funcs
),
479 INTEL_I945G_IDS(&gen3_stolen_funcs
),
480 INTEL_I945GM_IDS(&gen3_stolen_funcs
),
481 INTEL_VLV_M_IDS(&gen6_stolen_funcs
),
482 INTEL_VLV_D_IDS(&gen6_stolen_funcs
),
483 INTEL_PINEVIEW_IDS(&gen3_stolen_funcs
),
484 INTEL_I965G_IDS(&gen3_stolen_funcs
),
485 INTEL_G33_IDS(&gen3_stolen_funcs
),
486 INTEL_I965GM_IDS(&gen3_stolen_funcs
),
487 INTEL_GM45_IDS(&gen3_stolen_funcs
),
488 INTEL_G45_IDS(&gen3_stolen_funcs
),
489 INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs
),
490 INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs
),
491 INTEL_SNB_D_IDS(&gen6_stolen_funcs
),
492 INTEL_SNB_M_IDS(&gen6_stolen_funcs
),
493 INTEL_IVB_M_IDS(&gen6_stolen_funcs
),
494 INTEL_IVB_D_IDS(&gen6_stolen_funcs
),
495 INTEL_HSW_D_IDS(&gen6_stolen_funcs
),
496 INTEL_HSW_M_IDS(&gen6_stolen_funcs
),
497 INTEL_BDW_M_IDS(&gen8_stolen_funcs
),
498 INTEL_BDW_D_IDS(&gen8_stolen_funcs
)
501 static void __init
intel_graphics_stolen(int num
, int slot
, int func
)
506 u16 device
, subvendor
, subdevice
;
508 device
= read_pci_config_16(num
, slot
, func
, PCI_DEVICE_ID
);
509 subvendor
= read_pci_config_16(num
, slot
, func
,
510 PCI_SUBSYSTEM_VENDOR_ID
);
511 subdevice
= read_pci_config_16(num
, slot
, func
, PCI_SUBSYSTEM_ID
);
513 for (i
= 0; i
< ARRAY_SIZE(intel_stolen_ids
); i
++) {
514 if (intel_stolen_ids
[i
].device
== device
) {
515 const struct intel_stolen_funcs
*stolen_funcs
=
516 (const struct intel_stolen_funcs
*)intel_stolen_ids
[i
].driver_data
;
517 size
= stolen_funcs
->size(num
, slot
, func
);
518 start
= stolen_funcs
->base(num
, slot
, func
, size
);
520 printk(KERN_INFO
"Reserving Intel graphics stolen memory at 0x%x-0x%x\n",
521 start
, start
+ (u32
)size
- 1);
522 /* Mark this space as reserved */
523 e820_add_region(start
, size
, E820_RESERVED
);
524 sanitize_e820_map(e820
.map
,
525 ARRAY_SIZE(e820
.map
),
533 #define QFLAG_APPLY_ONCE 0x1
534 #define QFLAG_APPLIED 0x2
535 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
542 void (*f
)(int num
, int slot
, int func
);
546 * Only works for devices on the root bus. If you add any devices
547 * not on bus 0 readd another loop level in early_quirks(). But
548 * be careful because at least the Nvidia quirk here relies on
549 * only matching on bus 0.
551 static struct chipset early_qrk
[] __initdata
= {
552 { PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
553 PCI_CLASS_BRIDGE_PCI
, PCI_ANY_ID
, QFLAG_APPLY_ONCE
, nvidia_bugs
},
554 { PCI_VENDOR_ID_VIA
, PCI_ANY_ID
,
555 PCI_CLASS_BRIDGE_PCI
, PCI_ANY_ID
, QFLAG_APPLY_ONCE
, via_bugs
},
556 { PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_K8_NB
,
557 PCI_CLASS_BRIDGE_HOST
, PCI_ANY_ID
, 0, fix_hypertransport_config
},
558 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP400_SMBUS
,
559 PCI_CLASS_SERIAL_SMBUS
, PCI_ANY_ID
, 0, ati_bugs
},
560 { PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
561 PCI_CLASS_SERIAL_SMBUS
, PCI_ANY_ID
, 0, ati_bugs_contd
},
562 { PCI_VENDOR_ID_INTEL
, 0x3403, PCI_CLASS_BRIDGE_HOST
,
563 PCI_BASE_CLASS_BRIDGE
, 0, intel_remapping_check
},
564 { PCI_VENDOR_ID_INTEL
, 0x3405, PCI_CLASS_BRIDGE_HOST
,
565 PCI_BASE_CLASS_BRIDGE
, 0, intel_remapping_check
},
566 { PCI_VENDOR_ID_INTEL
, 0x3406, PCI_CLASS_BRIDGE_HOST
,
567 PCI_BASE_CLASS_BRIDGE
, 0, intel_remapping_check
},
568 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, PCI_CLASS_DISPLAY_VGA
, PCI_ANY_ID
,
569 QFLAG_APPLY_ONCE
, intel_graphics_stolen
},
574 * check_dev_quirk - apply early quirks to a given PCI device
577 * @func: PCI function
579 * Check the vendor & device ID against the early quirks table.
581 * If the device is single function, let early_quirks() know so we don't
582 * poke at this device again.
584 static int __init
check_dev_quirk(int num
, int slot
, int func
)
592 class = read_pci_config_16(num
, slot
, func
, PCI_CLASS_DEVICE
);
595 return -1; /* no class, treat as single function */
597 vendor
= read_pci_config_16(num
, slot
, func
, PCI_VENDOR_ID
);
599 device
= read_pci_config_16(num
, slot
, func
, PCI_DEVICE_ID
);
601 for (i
= 0; early_qrk
[i
].f
!= NULL
; i
++) {
602 if (((early_qrk
[i
].vendor
== PCI_ANY_ID
) ||
603 (early_qrk
[i
].vendor
== vendor
)) &&
604 ((early_qrk
[i
].device
== PCI_ANY_ID
) ||
605 (early_qrk
[i
].device
== device
)) &&
606 (!((early_qrk
[i
].class ^ class) &
607 early_qrk
[i
].class_mask
))) {
608 if ((early_qrk
[i
].flags
&
609 QFLAG_DONE
) != QFLAG_DONE
)
610 early_qrk
[i
].f(num
, slot
, func
);
611 early_qrk
[i
].flags
|= QFLAG_APPLIED
;
615 type
= read_pci_config_byte(num
, slot
, func
,
623 void __init
early_quirks(void)
627 if (!early_pci_allowed())
630 /* Poor man's PCI discovery */
631 /* Only scan the root bus */
632 for (slot
= 0; slot
< 32; slot
++)
633 for (func
= 0; func
< 8; func
++) {
634 /* Only probe function 0 on single fn devices */
635 if (check_dev_quirk(0, slot
, func
))