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1 /* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
4 uniquely.
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
8 in standard PCI quirks
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
11
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/pci_ids.h>
15 #include <asm/pci-direct.h>
16 #include <asm/dma.h>
17 #include <asm/io_apic.h>
18 #include <asm/apic.h>
19 #include <asm/iommu.h>
20 #include <asm/gart.h>
21
22 static void __init fix_hypertransport_config(int num, int slot, int func)
23 {
24 u32 htcfg;
25 /*
26 * we found a hypertransport bus
27 * make sure that we are broadcasting
28 * interrupts to all cpus on the ht bus
29 * if we're using extended apic ids
30 */
31 htcfg = read_pci_config(num, slot, func, 0x68);
32 if (htcfg & (1 << 18)) {
33 printk(KERN_INFO "Detected use of extended apic ids "
34 "on hypertransport bus\n");
35 if ((htcfg & (1 << 17)) == 0) {
36 printk(KERN_INFO "Enabling hypertransport extended "
37 "apic interrupt broadcast\n");
38 printk(KERN_INFO "Note this is a bios bug, "
39 "please contact your hw vendor\n");
40 htcfg |= (1 << 17);
41 write_pci_config(num, slot, func, 0x68, htcfg);
42 }
43 }
44
45
46 }
47
48 static void __init via_bugs(int num, int slot, int func)
49 {
50 #ifdef CONFIG_GART_IOMMU
51 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
52 !gart_iommu_aperture_allowed) {
53 printk(KERN_INFO
54 "Looks like a VIA chipset. Disabling IOMMU."
55 " Override with iommu=allowed\n");
56 gart_iommu_aperture_disabled = 1;
57 }
58 #endif
59 }
60
61 #ifdef CONFIG_ACPI
62 #ifdef CONFIG_X86_IO_APIC
63
64 static int __init nvidia_hpet_check(struct acpi_table_header *header)
65 {
66 return 0;
67 }
68 #endif /* CONFIG_X86_IO_APIC */
69 #endif /* CONFIG_ACPI */
70
71 static void __init nvidia_bugs(int num, int slot, int func)
72 {
73 #ifdef CONFIG_ACPI
74 #ifdef CONFIG_X86_IO_APIC
75 /*
76 * All timer overrides on Nvidia are
77 * wrong unless HPET is enabled.
78 * Unfortunately that's not true on many Asus boards.
79 * We don't know yet how to detect this automatically, but
80 * at least allow a command line override.
81 */
82 if (acpi_use_timer_override)
83 return;
84
85 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
86 acpi_skip_timer_override = 1;
87 printk(KERN_INFO "Nvidia board "
88 "detected. Ignoring ACPI "
89 "timer override.\n");
90 printk(KERN_INFO "If you got timer trouble "
91 "try acpi_use_timer_override\n");
92 }
93 #endif
94 #endif
95 /* RED-PEN skip them on mptables too? */
96
97 }
98
99 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
100 static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
101 {
102 u32 d;
103 u8 b;
104
105 b = read_pci_config_byte(num, slot, func, 0xac);
106 b &= ~(1<<5);
107 write_pci_config_byte(num, slot, func, 0xac, b);
108
109 d = read_pci_config(num, slot, func, 0x70);
110 d |= 1<<8;
111 write_pci_config(num, slot, func, 0x70, d);
112
113 d = read_pci_config(num, slot, func, 0x8);
114 d &= 0xff;
115 return d;
116 }
117
118 static void __init ati_bugs(int num, int slot, int func)
119 {
120 u32 d;
121 u8 b;
122
123 if (acpi_use_timer_override)
124 return;
125
126 d = ati_ixp4x0_rev(num, slot, func);
127 if (d < 0x82)
128 acpi_skip_timer_override = 1;
129 else {
130 /* check for IRQ0 interrupt swap */
131 outb(0x72, 0xcd6); b = inb(0xcd7);
132 if (!(b & 0x2))
133 acpi_skip_timer_override = 1;
134 }
135
136 if (acpi_skip_timer_override) {
137 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
138 printk(KERN_INFO "Ignoring ACPI timer override.\n");
139 printk(KERN_INFO "If you got timer trouble "
140 "try acpi_use_timer_override\n");
141 }
142 }
143
144 static u32 __init ati_sbx00_rev(int num, int slot, int func)
145 {
146 u32 old, d;
147
148 d = read_pci_config(num, slot, func, 0x70);
149 old = d;
150 d &= ~(1<<8);
151 write_pci_config(num, slot, func, 0x70, d);
152 d = read_pci_config(num, slot, func, 0x8);
153 d &= 0xff;
154 write_pci_config(num, slot, func, 0x70, old);
155
156 return d;
157 }
158
159 static void __init ati_bugs_contd(int num, int slot, int func)
160 {
161 u32 d, rev;
162
163 if (acpi_use_timer_override)
164 return;
165
166 rev = ati_sbx00_rev(num, slot, func);
167 if (rev > 0x13)
168 return;
169
170 /* check for IRQ0 interrupt swap */
171 d = read_pci_config(num, slot, func, 0x64);
172 if (!(d & (1<<14)))
173 acpi_skip_timer_override = 1;
174
175 if (acpi_skip_timer_override) {
176 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
177 printk(KERN_INFO "Ignoring ACPI timer override.\n");
178 printk(KERN_INFO "If you got timer trouble "
179 "try acpi_use_timer_override\n");
180 }
181 }
182 #else
183 static void __init ati_bugs(int num, int slot, int func)
184 {
185 }
186
187 static void __init ati_bugs_contd(int num, int slot, int func)
188 {
189 }
190 #endif
191
192 #define QFLAG_APPLY_ONCE 0x1
193 #define QFLAG_APPLIED 0x2
194 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
195 struct chipset {
196 u32 vendor;
197 u32 device;
198 u32 class;
199 u32 class_mask;
200 u32 flags;
201 void (*f)(int num, int slot, int func);
202 };
203
204 static struct chipset early_qrk[] __initdata = {
205 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
206 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
207 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
208 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
209 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
210 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
212 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
214 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
215 {}
216 };
217
218 /**
219 * check_dev_quirk - apply early quirks to a given PCI device
220 * @num: bus number
221 * @slot: slot number
222 * @func: PCI function
223 *
224 * Check the vendor & device ID against the early quirks table.
225 *
226 * If the device is single function, let early_quirks() know so we don't
227 * poke at this device again.
228 */
229 static int __init check_dev_quirk(int num, int slot, int func)
230 {
231 u16 class;
232 u16 vendor;
233 u16 device;
234 u8 type;
235 int i;
236
237 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
238
239 if (class == 0xffff)
240 return -1; /* no class, treat as single function */
241
242 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
243
244 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
245
246 for (i = 0; early_qrk[i].f != NULL; i++) {
247 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
248 (early_qrk[i].vendor == vendor)) &&
249 ((early_qrk[i].device == PCI_ANY_ID) ||
250 (early_qrk[i].device == device)) &&
251 (!((early_qrk[i].class ^ class) &
252 early_qrk[i].class_mask))) {
253 if ((early_qrk[i].flags &
254 QFLAG_DONE) != QFLAG_DONE)
255 early_qrk[i].f(num, slot, func);
256 early_qrk[i].flags |= QFLAG_APPLIED;
257 }
258 }
259
260 type = read_pci_config_byte(num, slot, func,
261 PCI_HEADER_TYPE);
262 if (!(type & 0x80))
263 return -1;
264
265 return 0;
266 }
267
268 void __init early_quirks(void)
269 {
270 int num, slot, func;
271
272 if (!early_pci_allowed())
273 return;
274
275 /* Poor man's PCI discovery */
276 for (num = 0; num < 32; num++)
277 for (slot = 0; slot < 32; slot++)
278 for (func = 0; func < 8; func++) {
279 /* Only probe function 0 on single fn devices */
280 if (check_dev_quirk(num, slot, func))
281 break;
282 }
283 }