arch/x86/kernel/fpu/init.c

   1 /*
   2  * x86 FPU boot time init code:
   3  */
   4 #include <asm/fpu/internal.h>
   5 #include <asm/tlbflush.h>
   6
   7 /*
   8  * Initialize the TS bit in CR0 according to the style of context-switches
   9  * we are using:
  10  */
  11 static void fpu__init_cpu_ctx_switch(void)
  12 {
  13         if (!cpu_has_eager_fpu)
  14                 stts();
  15         else
  16                 clts();
  17 }
  18
  19 /*
  20  * Initialize the registers found in all CPUs, CR0 and CR4:
  21  */
  22 static void fpu__init_cpu_generic(void)
  23 {
  24         unsigned long cr0;
  25         unsigned long cr4_mask = 0;
  26
  27         if (cpu_has_fxsr)
  28                 cr4_mask |= X86_CR4_OSFXSR;
  29         if (cpu_has_xmm)
  30                 cr4_mask |= X86_CR4_OSXMMEXCPT;
  31         if (cr4_mask)
  32                 cr4_set_bits(cr4_mask);
  33
  34         cr0 = read_cr0();
  35         cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */
  36         if (!cpu_has_fpu)
  37                 cr0 |= X86_CR0_EM;
  38         write_cr0(cr0);
  39
  40         /* Flush out any pending x87 state: */
  41         asm volatile ("fninit");
  42 }
  43
  44 /*
  45  * Enable all supported FPU features. Called when a CPU is brought online:
  46  */
  47 void fpu__init_cpu(void)
  48 {
  49         fpu__init_cpu_generic();
  50         fpu__init_cpu_xstate();
  51         fpu__init_cpu_ctx_switch();
  52 }
  53
  54 /*
  55  * The earliest FPU detection code.
  56  *
  57  * Set the X86_FEATURE_FPU CPU-capability bit based on
  58  * trying to execute an actual sequence of FPU instructions:
  59  */
  60 static void fpu__init_system_early_generic(struct cpuinfo_x86 *c)
  61 {
  62         unsigned long cr0;
  63         u16 fsw, fcw;
  64
  65         fsw = fcw = 0xffff;
  66
  67         cr0 = read_cr0();
  68         cr0 &= ~(X86_CR0_TS | X86_CR0_EM);
  69         write_cr0(cr0);
  70
  71         asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
  72                      : "+m" (fsw), "+m" (fcw));
  73
  74         if (fsw == 0 && (fcw & 0x103f) == 0x003f)
  75                 set_cpu_cap(c, X86_FEATURE_FPU);
  76         else
  77                 clear_cpu_cap(c, X86_FEATURE_FPU);
  78
  79 #ifndef CONFIG_MATH_EMULATION
  80         if (!cpu_has_fpu) {
  81                 pr_emerg("x86/fpu: Giving up, no FPU found and no math emulation present\n");
  82                 for (;;)
  83                         asm volatile("hlt");
  84         }
  85 #endif
  86 }
  87
  88 /*
  89  * Boot time FPU feature detection code:
  90  */
  91 unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu;
  92
  93 static void __init fpu__init_system_mxcsr(void)
  94 {
  95         unsigned int mask = 0;
  96
  97         if (cpu_has_fxsr) {
  98                 struct fxregs_state fx_tmp __aligned(32) = { };
  99
 100                 asm volatile("fxsave %0" : "+m" (fx_tmp));
 101
 102                 mask = fx_tmp.mxcsr_mask;
 103
 104                 /*
 105                  * If zero then use the default features mask,
 106                  * which has all features set, except the
 107                  * denormals-are-zero feature bit:
 108                  */
 109                 if (mask == 0)
 110                         mask = 0x0000ffbf;
 111         }
 112         mxcsr_feature_mask &= mask;
 113 }
 114
 115 /*
 116  * Once per bootup FPU initialization sequences that will run on most x86 CPUs:
 117  */
 118 static void __init fpu__init_system_generic(void)
 119 {
 120         /*
 121          * Set up the legacy init FPU context. (xstate init might overwrite this
 122          * with a more modern format, if the CPU supports it.)
 123          */
 124         fpstate_init_fxstate(&init_fpstate.fxsave);
 125
 126         fpu__init_system_mxcsr();
 127 }
 128
 129 /*
 130  * Size of the FPU context state. All tasks in the system use the
 131  * same context size, regardless of what portion they use.
 132  * This is inherent to the XSAVE architecture which puts all state
 133  * components into a single, continuous memory block:
 134  */
 135 unsigned int xstate_size;
 136 EXPORT_SYMBOL_GPL(xstate_size);
 137
 138 /*
 139  * Set up the xstate_size based on the legacy FPU context size.
 140  *
 141  * We set this up first, and later it will be overwritten by
 142  * fpu__init_system_xstate() if the CPU knows about xstates.
 143  */
 144 static void __init fpu__init_system_xstate_size_legacy(void)
 145 {
 146         static int on_boot_cpu = 1;
 147
 148         WARN_ON_FPU(!on_boot_cpu);
 149         on_boot_cpu = 0;
 150
 151         /*
 152          * Note that xstate_size might be overwriten later during
 153          * fpu__init_system_xstate().
 154          */
 155
 156         if (!cpu_has_fpu) {
 157                 /*
 158                  * Disable xsave as we do not support it if i387
 159                  * emulation is enabled.
 160                  */
 161                 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
 162                 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
 163                 xstate_size = sizeof(struct swregs_state);
 164         } else {
 165                 if (cpu_has_fxsr)
 166                         xstate_size = sizeof(struct fxregs_state);
 167                 else
 168                         xstate_size = sizeof(struct fregs_state);
 169         }
 170         /*
 171          * Quirk: we don't yet handle the XSAVES* instructions
 172          * correctly, as we don't correctly convert between
 173          * standard and compacted format when interfacing
 174          * with user-space - so disable it for now.
 175          *
 176          * The difference is small: with recent CPUs the
 177          * compacted format is only marginally smaller than
 178          * the standard FPU state format.
 179          *
 180          * ( This is easy to backport while we are fixing
 181          *   XSAVES* support. )
 182          */
 183         setup_clear_cpu_cap(X86_FEATURE_XSAVES);
 184 }
 185
 186 /*
 187  * FPU context switching strategies:
 188  *
 189  * Against popular belief, we don't do lazy FPU saves, due to the
 190  * task migration complications it brings on SMP - we only do
 191  * lazy FPU restores.
 192  *
 193  * 'lazy' is the traditional strategy, which is based on setting
 194  * CR0::TS to 1 during context-switch (instead of doing a full
 195  * restore of the FPU state), which causes the first FPU instruction
 196  * after the context switch (whenever it is executed) to fault - at
 197  * which point we lazily restore the FPU state into FPU registers.
 198  *
 199  * Tasks are of course under no obligation to execute FPU instructions,
 200  * so it can easily happen that another context-switch occurs without
 201  * a single FPU instruction being executed. If we eventually switch
 202  * back to the original task (that still owns the FPU) then we have
 203  * not only saved the restores along the way, but we also have the
 204  * FPU ready to be used for the original task.
 205  *
 206  * 'eager' switching is used on modern CPUs, there we switch the FPU
 207  * state during every context switch, regardless of whether the task
 208  * has used FPU instructions in that time slice or not. This is done
 209  * because modern FPU context saving instructions are able to optimize
 210  * state saving and restoration in hardware: they can detect both
 211  * unused and untouched FPU state and optimize accordingly.
 212  *
 213  * [ Note that even in 'lazy' mode we might optimize context switches
 214  *   to use 'eager' restores, if we detect that a task is using the FPU
 215  *   frequently. See the fpu->counter logic in fpu/internal.h for that. ]
 216  */
 217 static enum { AUTO, ENABLE, DISABLE } eagerfpu = AUTO;
 218
 219 static int __init eager_fpu_setup(char *s)
 220 {
 221         if (!strcmp(s, "on"))
 222                 eagerfpu = ENABLE;
 223         else if (!strcmp(s, "off"))
 224                 eagerfpu = DISABLE;
 225         else if (!strcmp(s, "auto"))
 226                 eagerfpu = AUTO;
 227         return 1;
 228 }
 229 __setup("eagerfpu=", eager_fpu_setup);
 230
 231 /*
 232  * Pick the FPU context switching strategy:
 233  */
 234 static void __init fpu__init_system_ctx_switch(void)
 235 {
 236         static bool on_boot_cpu = 1;
 237
 238         WARN_ON_FPU(!on_boot_cpu);
 239         on_boot_cpu = 0;
 240
 241         WARN_ON_FPU(current->thread.fpu.fpstate_active);
 242         current_thread_info()->status = 0;
 243
 244         /* Auto enable eagerfpu for xsaveopt */
 245         if (cpu_has_xsaveopt && eagerfpu != DISABLE)
 246                 eagerfpu = ENABLE;
 247
 248         if (xfeatures_mask & XSTATE_EAGER) {
 249                 if (eagerfpu == DISABLE) {
 250                         pr_err("x86/fpu: eagerfpu switching disabled, disabling the following xstate features: 0x%llx.\n",
 251                                xfeatures_mask & XSTATE_EAGER);
 252                         xfeatures_mask &= ~XSTATE_EAGER;
 253                 } else {
 254                         eagerfpu = ENABLE;
 255                 }
 256         }
 257
 258         if (eagerfpu == ENABLE)
 259                 setup_force_cpu_cap(X86_FEATURE_EAGER_FPU);
 260
 261         printk(KERN_INFO "x86/fpu: Using '%s' FPU context switches.\n", eagerfpu == ENABLE ? "eager" : "lazy");
 262 }
 263
 264 /*
 265  * Called on the boot CPU once per system bootup, to set up the initial
 266  * FPU state that is later cloned into all processes:
 267  */
 268 void __init fpu__init_system(struct cpuinfo_x86 *c)
 269 {
 270         fpu__init_system_early_generic(c);
 271
 272         /*
 273          * The FPU has to be operational for some of the
 274          * later FPU init activities:
 275          */
 276         fpu__init_cpu();
 277
 278         /*
 279          * But don't leave CR0::TS set yet, as some of the FPU setup
 280          * methods depend on being able to execute FPU instructions
 281          * that will fault on a set TS, such as the FXSAVE in
 282          * fpu__init_system_mxcsr().
 283          */
 284         clts();
 285
 286         fpu__init_system_generic();
 287         fpu__init_system_xstate_size_legacy();
 288         fpu__init_system_xstate();
 289
 290         fpu__init_system_ctx_switch();
 291 }
 292
 293 /*
 294  * Boot parameter to turn off FPU support and fall back to math-emu:
 295  */
 296 static int __init no_387(char *s)
 297 {
 298         setup_clear_cpu_cap(X86_FEATURE_FPU);
 299         return 1;
 300 }
 301 __setup("no387", no_387);
 302
 303 /*
 304  * Disable all xstate CPU features:
 305  */
 306 static int __init x86_noxsave_setup(char *s)
 307 {
 308         if (strlen(s))
 309                 return 0;
 310
 311         setup_clear_cpu_cap(X86_FEATURE_XSAVE);
 312         setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
 313         setup_clear_cpu_cap(X86_FEATURE_XSAVES);
 314         setup_clear_cpu_cap(X86_FEATURE_AVX);
 315         setup_clear_cpu_cap(X86_FEATURE_AVX2);
 316
 317         return 1;
 318 }
 319 __setup("noxsave", x86_noxsave_setup);
 320
 321 /*
 322  * Disable the XSAVEOPT instruction specifically:
 323  */
 324 static int __init x86_noxsaveopt_setup(char *s)
 325 {
 326         setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
 327
 328         return 1;
 329 }
 330 __setup("noxsaveopt", x86_noxsaveopt_setup);
 331
 332 /*
 333  * Disable the XSAVES instruction:
 334  */
 335 static int __init x86_noxsaves_setup(char *s)
 336 {
 337         setup_clear_cpu_cap(X86_FEATURE_XSAVES);
 338
 339         return 1;
 340 }
 341 __setup("noxsaves", x86_noxsaves_setup);
 342
 343 /*
 344  * Disable FX save/restore and SSE support:
 345  */
 346 static int __init x86_nofxsr_setup(char *s)
 347 {
 348         setup_clear_cpu_cap(X86_FEATURE_FXSR);
 349         setup_clear_cpu_cap(X86_FEATURE_FXSR_OPT);
 350         setup_clear_cpu_cap(X86_FEATURE_XMM);
 351
 352         return 1;
 353 }
 354 __setup("nofxsr", x86_nofxsr_setup);