2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/kernel.h>
12 #include <linux/threads.h>
13 #include <linux/cpu.h>
14 #include <linux/cpumask.h>
15 #include <linux/string.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <linux/sched.h>
19 #include <linux/module.h>
20 #include <linux/hardirq.h>
21 #include <linux/timer.h>
22 #include <linux/proc_fs.h>
23 #include <asm/current.h>
27 #include <asm/pgtable.h>
28 #include <asm/uv/uv.h>
29 #include <asm/uv/uv_mmrs.h>
30 #include <asm/uv/uv_hub.h>
31 #include <asm/uv/bios.h>
33 DEFINE_PER_CPU(int, x2apic_extra_bits
);
35 static enum uv_system_type uv_system_type
;
37 static int uv_acpi_madt_oem_check(char *oem_id
, char *oem_table_id
)
39 if (!strcmp(oem_id
, "SGI")) {
40 if (!strcmp(oem_table_id
, "UVL"))
41 uv_system_type
= UV_LEGACY_APIC
;
42 else if (!strcmp(oem_table_id
, "UVX"))
43 uv_system_type
= UV_X2APIC
;
44 else if (!strcmp(oem_table_id
, "UVH")) {
45 uv_system_type
= UV_NON_UNIQUE_APIC
;
52 enum uv_system_type
get_uv_system_type(void)
54 return uv_system_type
;
57 int is_uv_system(void)
59 return uv_system_type
!= UV_NONE
;
61 EXPORT_SYMBOL_GPL(is_uv_system
);
63 DEFINE_PER_CPU(struct uv_hub_info_s
, __uv_hub_info
);
64 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info
);
66 struct uv_blade_info
*uv_blade_info
;
67 EXPORT_SYMBOL_GPL(uv_blade_info
);
69 short *uv_node_to_blade
;
70 EXPORT_SYMBOL_GPL(uv_node_to_blade
);
72 short *uv_cpu_to_blade
;
73 EXPORT_SYMBOL_GPL(uv_cpu_to_blade
);
75 short uv_possible_blades
;
76 EXPORT_SYMBOL_GPL(uv_possible_blades
);
78 unsigned long sn_rtc_cycles_per_second
;
79 EXPORT_SYMBOL(sn_rtc_cycles_per_second
);
81 /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
83 static const struct cpumask
*uv_target_cpus(void)
88 static void uv_vector_allocation_domain(int cpu
, struct cpumask
*retmask
)
90 cpumask_clear(retmask
);
91 cpumask_set_cpu(cpu
, retmask
);
94 int uv_wakeup_secondary(int phys_apicid
, unsigned int start_rip
)
99 pnode
= uv_apicid_to_pnode(phys_apicid
);
100 val
= (1UL << UVH_IPI_INT_SEND_SHFT
) |
101 (phys_apicid
<< UVH_IPI_INT_APIC_ID_SHFT
) |
102 (((long)start_rip
<< UVH_IPI_INT_VECTOR_SHFT
) >> 12) |
104 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
107 val
= (1UL << UVH_IPI_INT_SEND_SHFT
) |
108 (phys_apicid
<< UVH_IPI_INT_APIC_ID_SHFT
) |
109 (((long)start_rip
<< UVH_IPI_INT_VECTOR_SHFT
) >> 12) |
111 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
115 static void uv_send_IPI_one(int cpu
, int vector
)
117 unsigned long val
, apicid
;
120 apicid
= per_cpu(x86_cpu_to_apicid
, cpu
);
121 pnode
= uv_apicid_to_pnode(apicid
);
123 val
= (1UL << UVH_IPI_INT_SEND_SHFT
) |
124 (apicid
<< UVH_IPI_INT_APIC_ID_SHFT
) |
125 (vector
<< UVH_IPI_INT_VECTOR_SHFT
);
127 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
130 static void uv_send_IPI_mask(const struct cpumask
*mask
, int vector
)
134 for_each_cpu(cpu
, mask
)
135 uv_send_IPI_one(cpu
, vector
);
138 static void uv_send_IPI_mask_allbutself(const struct cpumask
*mask
, int vector
)
140 unsigned int this_cpu
= smp_processor_id();
143 for_each_cpu(cpu
, mask
) {
145 uv_send_IPI_one(cpu
, vector
);
149 static void uv_send_IPI_allbutself(int vector
)
151 unsigned int this_cpu
= smp_processor_id();
154 for_each_online_cpu(cpu
) {
156 uv_send_IPI_one(cpu
, vector
);
160 static void uv_send_IPI_all(int vector
)
162 uv_send_IPI_mask(cpu_online_mask
, vector
);
165 static int uv_apic_id_registered(void)
170 static void uv_init_apic_ldr(void)
174 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask
*cpumask
)
177 * We're using fixed IRQ delivery, can only return one phys APIC ID.
178 * May as well be the first.
180 int cpu
= cpumask_first(cpumask
);
182 if ((unsigned)cpu
< nr_cpu_ids
)
183 return per_cpu(x86_cpu_to_apicid
, cpu
);
189 uv_cpu_mask_to_apicid_and(const struct cpumask
*cpumask
,
190 const struct cpumask
*andmask
)
195 * We're using fixed IRQ delivery, can only return one phys APIC ID.
196 * May as well be the first.
198 for_each_cpu_and(cpu
, cpumask
, andmask
) {
199 if (cpumask_test_cpu(cpu
, cpu_online_mask
))
202 if (cpu
< nr_cpu_ids
)
203 return per_cpu(x86_cpu_to_apicid
, cpu
);
208 static unsigned int x2apic_get_apic_id(unsigned long x
)
212 WARN_ON(preemptible() && num_online_cpus() > 1);
213 id
= x
| __get_cpu_var(x2apic_extra_bits
);
218 static unsigned long set_apic_id(unsigned int id
)
222 /* maskout x2apic_extra_bits ? */
227 static unsigned int uv_read_apic_id(void)
230 return x2apic_get_apic_id(apic_read(APIC_ID
));
233 static int uv_phys_pkg_id(int initial_apicid
, int index_msb
)
235 return uv_read_apic_id() >> index_msb
;
238 static void uv_send_IPI_self(int vector
)
240 apic_write(APIC_SELF_IPI
, vector
);
243 struct genapic apic_x2apic_uv_x
= {
245 .name
= "UV large system",
247 .acpi_madt_oem_check
= uv_acpi_madt_oem_check
,
248 .apic_id_registered
= uv_apic_id_registered
,
250 .irq_delivery_mode
= dest_Fixed
,
251 .irq_dest_mode
= 1, /* logical */
253 .target_cpus
= uv_target_cpus
,
255 .dest_logical
= APIC_DEST_LOGICAL
,
256 .check_apicid_used
= NULL
,
257 .check_apicid_present
= NULL
,
259 .vector_allocation_domain
= uv_vector_allocation_domain
,
260 .init_apic_ldr
= uv_init_apic_ldr
,
262 .ioapic_phys_id_map
= NULL
,
263 .setup_apic_routing
= NULL
,
264 .multi_timer_check
= NULL
,
265 .apicid_to_node
= NULL
,
266 .cpu_to_logical_apicid
= NULL
,
267 .cpu_present_to_apicid
= default_cpu_present_to_apicid
,
268 .apicid_to_cpu_present
= NULL
,
269 .setup_portio_remap
= NULL
,
270 .check_phys_apicid_present
= default_check_phys_apicid_present
,
271 .enable_apic_mode
= NULL
,
272 .phys_pkg_id
= uv_phys_pkg_id
,
273 .mps_oem_check
= NULL
,
275 .get_apic_id
= x2apic_get_apic_id
,
276 .set_apic_id
= set_apic_id
,
277 .apic_id_mask
= 0xFFFFFFFFu
,
279 .cpu_mask_to_apicid
= uv_cpu_mask_to_apicid
,
280 .cpu_mask_to_apicid_and
= uv_cpu_mask_to_apicid_and
,
282 .send_IPI_mask
= uv_send_IPI_mask
,
283 .send_IPI_mask_allbutself
= uv_send_IPI_mask_allbutself
,
284 .send_IPI_allbutself
= uv_send_IPI_allbutself
,
285 .send_IPI_all
= uv_send_IPI_all
,
286 .send_IPI_self
= uv_send_IPI_self
,
289 .trampoline_phys_low
= DEFAULT_TRAMPOLINE_PHYS_LOW
,
290 .trampoline_phys_high
= DEFAULT_TRAMPOLINE_PHYS_HIGH
,
291 .wait_for_init_deassert
= NULL
,
292 .smp_callin_clear_local_apic
= NULL
,
293 .store_NMI_vector
= NULL
,
294 .inquire_remote_apic
= NULL
,
296 .read
= native_apic_msr_read
,
297 .write
= native_apic_msr_write
,
298 .icr_read
= native_x2apic_icr_read
,
299 .icr_write
= native_x2apic_icr_write
,
300 .wait_icr_idle
= native_x2apic_wait_icr_idle
,
301 .safe_wait_icr_idle
= native_safe_x2apic_wait_icr_idle
,
304 static __cpuinit
void set_x2apic_extra_bits(int pnode
)
306 __get_cpu_var(x2apic_extra_bits
) = (pnode
<< 6);
310 * Called on boot cpu.
312 static __init
int boot_pnode_to_blade(int pnode
)
316 for (blade
= 0; blade
< uv_num_possible_blades(); blade
++)
317 if (pnode
== uv_blade_info
[blade
].pnode
)
323 unsigned long redirect
;
327 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
329 static __initdata
struct redir_addr redir_addrs
[] = {
330 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR
, UVH_SI_ALIAS0_OVERLAY_CONFIG
},
331 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR
, UVH_SI_ALIAS1_OVERLAY_CONFIG
},
332 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR
, UVH_SI_ALIAS2_OVERLAY_CONFIG
},
335 static __init
void get_lowmem_redirect(unsigned long *base
, unsigned long *size
)
337 union uvh_si_alias0_overlay_config_u alias
;
338 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect
;
341 for (i
= 0; i
< ARRAY_SIZE(redir_addrs
); i
++) {
342 alias
.v
= uv_read_local_mmr(redir_addrs
[i
].alias
);
343 if (alias
.s
.base
== 0) {
344 *size
= (1UL << alias
.s
.m_alias
);
345 redirect
.v
= uv_read_local_mmr(redir_addrs
[i
].redirect
);
346 *base
= (unsigned long)redirect
.s
.dest_base
<< DEST_SHIFT
;
353 static __init
void map_low_mmrs(void)
355 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE
, UV_GLOBAL_MMR32_SIZE
);
356 init_extra_mapping_uc(UV_LOCAL_MMR_BASE
, UV_LOCAL_MMR_SIZE
);
359 enum map_type
{map_wb
, map_uc
};
361 static __init
void map_high(char *id
, unsigned long base
, int shift
,
362 int max_pnode
, enum map_type map_type
)
364 unsigned long bytes
, paddr
;
366 paddr
= base
<< shift
;
367 bytes
= (1UL << shift
) * (max_pnode
+ 1);
368 printk(KERN_INFO
"UV: Map %s_HI 0x%lx - 0x%lx\n", id
, paddr
,
370 if (map_type
== map_uc
)
371 init_extra_mapping_uc(paddr
, bytes
);
373 init_extra_mapping_wb(paddr
, bytes
);
376 static __init
void map_gru_high(int max_pnode
)
378 union uvh_rh_gam_gru_overlay_config_mmr_u gru
;
379 int shift
= UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT
;
381 gru
.v
= uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR
);
383 map_high("GRU", gru
.s
.base
, shift
, max_pnode
, map_wb
);
386 static __init
void map_config_high(int max_pnode
)
388 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg
;
389 int shift
= UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT
;
391 cfg
.v
= uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR
);
393 map_high("CONFIG", cfg
.s
.base
, shift
, max_pnode
, map_uc
);
396 static __init
void map_mmr_high(int max_pnode
)
398 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr
;
399 int shift
= UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT
;
401 mmr
.v
= uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR
);
403 map_high("MMR", mmr
.s
.base
, shift
, max_pnode
, map_uc
);
406 static __init
void map_mmioh_high(int max_pnode
)
408 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh
;
409 int shift
= UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT
;
411 mmioh
.v
= uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR
);
413 map_high("MMIOH", mmioh
.s
.base
, shift
, max_pnode
, map_uc
);
416 static __init
void uv_rtc_init(void)
421 status
= uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK
,
423 if (status
!= BIOS_STATUS_SUCCESS
|| ticks_per_sec
< 100000) {
425 "unable to determine platform RTC clock frequency, "
427 /* BIOS gives wrong value for clock freq. so guess */
428 sn_rtc_cycles_per_second
= 1000000000000UL / 30000UL;
430 sn_rtc_cycles_per_second
= ticks_per_sec
;
434 * percpu heartbeat timer
436 static void uv_heartbeat(unsigned long ignored
)
438 struct timer_list
*timer
= &uv_hub_info
->scir
.timer
;
439 unsigned char bits
= uv_hub_info
->scir
.state
;
441 /* flip heartbeat bit */
442 bits
^= SCIR_CPU_HEARTBEAT
;
444 /* is this cpu idle? */
445 if (idle_cpu(raw_smp_processor_id()))
446 bits
&= ~SCIR_CPU_ACTIVITY
;
448 bits
|= SCIR_CPU_ACTIVITY
;
450 /* update system controller interface reg */
451 uv_set_scir_bits(bits
);
453 /* enable next timer period */
454 mod_timer(timer
, jiffies
+ SCIR_CPU_HB_INTERVAL
);
457 static void __cpuinit
uv_heartbeat_enable(int cpu
)
459 if (!uv_cpu_hub_info(cpu
)->scir
.enabled
) {
460 struct timer_list
*timer
= &uv_cpu_hub_info(cpu
)->scir
.timer
;
462 uv_set_cpu_scir_bits(cpu
, SCIR_CPU_HEARTBEAT
|SCIR_CPU_ACTIVITY
);
463 setup_timer(timer
, uv_heartbeat
, cpu
);
464 timer
->expires
= jiffies
+ SCIR_CPU_HB_INTERVAL
;
465 add_timer_on(timer
, cpu
);
466 uv_cpu_hub_info(cpu
)->scir
.enabled
= 1;
470 if (!uv_cpu_hub_info(0)->scir
.enabled
)
471 uv_heartbeat_enable(0);
474 #ifdef CONFIG_HOTPLUG_CPU
475 static void __cpuinit
uv_heartbeat_disable(int cpu
)
477 if (uv_cpu_hub_info(cpu
)->scir
.enabled
) {
478 uv_cpu_hub_info(cpu
)->scir
.enabled
= 0;
479 del_timer(&uv_cpu_hub_info(cpu
)->scir
.timer
);
481 uv_set_cpu_scir_bits(cpu
, 0xff);
485 * cpu hotplug notifier
487 static __cpuinit
int uv_scir_cpu_notify(struct notifier_block
*self
,
488 unsigned long action
, void *hcpu
)
490 long cpu
= (long)hcpu
;
494 uv_heartbeat_enable(cpu
);
496 case CPU_DOWN_PREPARE
:
497 uv_heartbeat_disable(cpu
);
505 static __init
void uv_scir_register_cpu_notifier(void)
507 hotcpu_notifier(uv_scir_cpu_notify
, 0);
510 #else /* !CONFIG_HOTPLUG_CPU */
512 static __init
void uv_scir_register_cpu_notifier(void)
516 static __init
int uv_init_heartbeat(void)
521 for_each_online_cpu(cpu
)
522 uv_heartbeat_enable(cpu
);
526 late_initcall(uv_init_heartbeat
);
528 #endif /* !CONFIG_HOTPLUG_CPU */
531 * Called on each cpu to initialize the per_cpu UV data area.
532 * ZZZ hotplug not supported yet
534 void __cpuinit
uv_cpu_init(void)
536 /* CPU 0 initilization will be done via uv_system_init. */
540 uv_blade_info
[uv_numa_blade_id()].nr_online_cpus
++;
542 if (get_uv_system_type() == UV_NON_UNIQUE_APIC
)
543 set_x2apic_extra_bits(uv_hub_info
->pnode
);
547 void __init
uv_system_init(void)
549 union uvh_si_addr_map_config_u m_n_config
;
550 union uvh_node_id_u node_id
;
551 unsigned long gnode_upper
, lowmem_redir_base
, lowmem_redir_size
;
552 int bytes
, nid
, cpu
, lcpu
, pnode
, blade
, i
, j
, m_val
, n_val
;
554 unsigned long mmr_base
, present
;
558 m_n_config
.v
= uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG
);
559 m_val
= m_n_config
.s
.m_skt
;
560 n_val
= m_n_config
.s
.n_skt
;
562 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR
) &
564 printk(KERN_DEBUG
"UV: global MMR base 0x%lx\n", mmr_base
);
566 for(i
= 0; i
< UVH_NODE_PRESENT_TABLE_DEPTH
; i
++)
567 uv_possible_blades
+=
568 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE
+ i
* 8));
569 printk(KERN_DEBUG
"UV: Found %d blades\n", uv_num_possible_blades());
571 bytes
= sizeof(struct uv_blade_info
) * uv_num_possible_blades();
572 uv_blade_info
= kmalloc(bytes
, GFP_KERNEL
);
574 get_lowmem_redirect(&lowmem_redir_base
, &lowmem_redir_size
);
576 bytes
= sizeof(uv_node_to_blade
[0]) * num_possible_nodes();
577 uv_node_to_blade
= kmalloc(bytes
, GFP_KERNEL
);
578 memset(uv_node_to_blade
, 255, bytes
);
580 bytes
= sizeof(uv_cpu_to_blade
[0]) * num_possible_cpus();
581 uv_cpu_to_blade
= kmalloc(bytes
, GFP_KERNEL
);
582 memset(uv_cpu_to_blade
, 255, bytes
);
585 for (i
= 0; i
< UVH_NODE_PRESENT_TABLE_DEPTH
; i
++) {
586 present
= uv_read_local_mmr(UVH_NODE_PRESENT_TABLE
+ i
* 8);
587 for (j
= 0; j
< 64; j
++) {
588 if (!test_bit(j
, &present
))
590 uv_blade_info
[blade
].pnode
= (i
* 64 + j
);
591 uv_blade_info
[blade
].nr_possible_cpus
= 0;
592 uv_blade_info
[blade
].nr_online_cpus
= 0;
597 node_id
.v
= uv_read_local_mmr(UVH_NODE_ID
);
598 gnode_upper
= (((unsigned long)node_id
.s
.node_id
) &
599 ~((1 << n_val
) - 1)) << m_val
;
602 uv_bios_get_sn_info(0, &uv_type
, &sn_partition_id
,
603 &sn_coherency_id
, &sn_region_size
);
606 for_each_present_cpu(cpu
) {
607 nid
= cpu_to_node(cpu
);
608 pnode
= uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid
, cpu
));
609 blade
= boot_pnode_to_blade(pnode
);
610 lcpu
= uv_blade_info
[blade
].nr_possible_cpus
;
611 uv_blade_info
[blade
].nr_possible_cpus
++;
613 uv_cpu_hub_info(cpu
)->lowmem_remap_base
= lowmem_redir_base
;
614 uv_cpu_hub_info(cpu
)->lowmem_remap_top
= lowmem_redir_size
;
615 uv_cpu_hub_info(cpu
)->m_val
= m_val
;
616 uv_cpu_hub_info(cpu
)->n_val
= m_val
;
617 uv_cpu_hub_info(cpu
)->numa_blade_id
= blade
;
618 uv_cpu_hub_info(cpu
)->blade_processor_id
= lcpu
;
619 uv_cpu_hub_info(cpu
)->pnode
= pnode
;
620 uv_cpu_hub_info(cpu
)->pnode_mask
= (1 << n_val
) - 1;
621 uv_cpu_hub_info(cpu
)->gpa_mask
= (1 << (m_val
+ n_val
)) - 1;
622 uv_cpu_hub_info(cpu
)->gnode_upper
= gnode_upper
;
623 uv_cpu_hub_info(cpu
)->global_mmr_base
= mmr_base
;
624 uv_cpu_hub_info(cpu
)->coherency_domain_number
= sn_coherency_id
;
625 uv_cpu_hub_info(cpu
)->scir
.offset
= SCIR_LOCAL_MMR_BASE
+ lcpu
;
626 uv_node_to_blade
[nid
] = blade
;
627 uv_cpu_to_blade
[cpu
] = blade
;
628 max_pnode
= max(pnode
, max_pnode
);
630 printk(KERN_DEBUG
"UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
631 "lcpu %d, blade %d\n",
632 cpu
, per_cpu(x86_cpu_to_apicid
, cpu
), pnode
, nid
,
636 map_gru_high(max_pnode
);
637 map_mmr_high(max_pnode
);
638 map_config_high(max_pnode
);
639 map_mmioh_high(max_pnode
);
642 uv_scir_register_cpu_notifier();
643 proc_mkdir("sgi_uv", NULL
);