1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/export.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/i8253.h>
8 #include <linux/slab.h>
9 #include <linux/hpet.h>
10 #include <linux/init.h>
11 #include <linux/cpu.h>
15 #include <asm/cpufeature.h>
16 #include <asm/irqdomain.h>
17 #include <asm/fixmap.h>
21 #define HPET_MASK CLOCKSOURCE_MASK(32)
25 #define FSEC_PER_NSEC 1000000L
27 #define HPET_DEV_USED_BIT 2
28 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
29 #define HPET_DEV_VALID 0x8
30 #define HPET_DEV_FSB_CAP 0x1000
31 #define HPET_DEV_PERI_CAP 0x2000
33 #define HPET_MIN_CYCLES 128
34 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
37 * HPET address is set in acpi/boot.c, when an ACPI entry exists
39 unsigned long hpet_address
;
40 u8 hpet_blockid
; /* OS timer block num */
41 bool hpet_msi_disable
;
44 static unsigned int hpet_num_timers
;
46 static void __iomem
*hpet_virt_address
;
49 struct clock_event_device evt
;
57 static inline struct hpet_dev
*EVT_TO_HPET_DEV(struct clock_event_device
*evtdev
)
59 return container_of(evtdev
, struct hpet_dev
, evt
);
62 inline unsigned int hpet_readl(unsigned int a
)
64 return readl(hpet_virt_address
+ a
);
67 static inline void hpet_writel(unsigned int d
, unsigned int a
)
69 writel(d
, hpet_virt_address
+ a
);
73 #include <asm/pgtable.h>
76 static inline void hpet_set_mapping(void)
78 hpet_virt_address
= ioremap_nocache(hpet_address
, HPET_MMAP_SIZE
);
81 static inline void hpet_clear_mapping(void)
83 iounmap(hpet_virt_address
);
84 hpet_virt_address
= NULL
;
88 * HPET command line enable / disable
90 bool boot_hpet_disable
;
92 static bool hpet_verbose
;
94 static int __init
hpet_setup(char *str
)
97 char *next
= strchr(str
, ',');
101 if (!strncmp("disable", str
, 7))
102 boot_hpet_disable
= true;
103 if (!strncmp("force", str
, 5))
104 hpet_force_user
= true;
105 if (!strncmp("verbose", str
, 7))
111 __setup("hpet=", hpet_setup
);
113 static int __init
disable_hpet(char *str
)
115 boot_hpet_disable
= true;
118 __setup("nohpet", disable_hpet
);
120 static inline int is_hpet_capable(void)
122 return !boot_hpet_disable
&& hpet_address
;
126 * HPET timer interrupt enable / disable
128 static bool hpet_legacy_int_enabled
;
131 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
133 int is_hpet_enabled(void)
135 return is_hpet_capable() && hpet_legacy_int_enabled
;
137 EXPORT_SYMBOL_GPL(is_hpet_enabled
);
139 static void _hpet_print_config(const char *function
, int line
)
142 printk(KERN_INFO
"hpet: %s(%d):\n", function
, line
);
143 l
= hpet_readl(HPET_ID
);
144 h
= hpet_readl(HPET_PERIOD
);
145 timers
= ((l
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
146 printk(KERN_INFO
"hpet: ID: 0x%x, PERIOD: 0x%x\n", l
, h
);
147 l
= hpet_readl(HPET_CFG
);
148 h
= hpet_readl(HPET_STATUS
);
149 printk(KERN_INFO
"hpet: CFG: 0x%x, STATUS: 0x%x\n", l
, h
);
150 l
= hpet_readl(HPET_COUNTER
);
151 h
= hpet_readl(HPET_COUNTER
+4);
152 printk(KERN_INFO
"hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l
, h
);
154 for (i
= 0; i
< timers
; i
++) {
155 l
= hpet_readl(HPET_Tn_CFG(i
));
156 h
= hpet_readl(HPET_Tn_CFG(i
)+4);
157 printk(KERN_INFO
"hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
159 l
= hpet_readl(HPET_Tn_CMP(i
));
160 h
= hpet_readl(HPET_Tn_CMP(i
)+4);
161 printk(KERN_INFO
"hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
163 l
= hpet_readl(HPET_Tn_ROUTE(i
));
164 h
= hpet_readl(HPET_Tn_ROUTE(i
)+4);
165 printk(KERN_INFO
"hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
170 #define hpet_print_config() \
173 _hpet_print_config(__func__, __LINE__); \
177 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
178 * timer 0 and timer 1 in case of RTC emulation.
182 static void hpet_reserve_msi_timers(struct hpet_data
*hd
);
184 static void hpet_reserve_platform_timers(unsigned int id
)
186 struct hpet __iomem
*hpet
= hpet_virt_address
;
187 struct hpet_timer __iomem
*timer
= &hpet
->hpet_timers
[2];
188 unsigned int nrtimers
, i
;
191 nrtimers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
193 memset(&hd
, 0, sizeof(hd
));
194 hd
.hd_phys_address
= hpet_address
;
195 hd
.hd_address
= hpet
;
196 hd
.hd_nirqs
= nrtimers
;
197 hpet_reserve_timer(&hd
, 0);
199 #ifdef CONFIG_HPET_EMULATE_RTC
200 hpet_reserve_timer(&hd
, 1);
204 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
205 * is wrong for i8259!) not the output IRQ. Many BIOS writers
206 * don't bother configuring *any* comparator interrupts.
208 hd
.hd_irq
[0] = HPET_LEGACY_8254
;
209 hd
.hd_irq
[1] = HPET_LEGACY_RTC
;
211 for (i
= 2; i
< nrtimers
; timer
++, i
++) {
212 hd
.hd_irq
[i
] = (readl(&timer
->hpet_config
) &
213 Tn_INT_ROUTE_CNF_MASK
) >> Tn_INT_ROUTE_CNF_SHIFT
;
216 hpet_reserve_msi_timers(&hd
);
222 static void hpet_reserve_platform_timers(unsigned int id
) { }
228 static unsigned long hpet_freq
;
230 static struct clock_event_device hpet_clockevent
;
232 static void hpet_stop_counter(void)
234 u32 cfg
= hpet_readl(HPET_CFG
);
235 cfg
&= ~HPET_CFG_ENABLE
;
236 hpet_writel(cfg
, HPET_CFG
);
239 static void hpet_reset_counter(void)
241 hpet_writel(0, HPET_COUNTER
);
242 hpet_writel(0, HPET_COUNTER
+ 4);
245 static void hpet_start_counter(void)
247 unsigned int cfg
= hpet_readl(HPET_CFG
);
248 cfg
|= HPET_CFG_ENABLE
;
249 hpet_writel(cfg
, HPET_CFG
);
252 static void hpet_restart_counter(void)
255 hpet_reset_counter();
256 hpet_start_counter();
259 static void hpet_resume_device(void)
264 static void hpet_resume_counter(struct clocksource
*cs
)
266 hpet_resume_device();
267 hpet_restart_counter();
270 static void hpet_enable_legacy_int(void)
272 unsigned int cfg
= hpet_readl(HPET_CFG
);
274 cfg
|= HPET_CFG_LEGACY
;
275 hpet_writel(cfg
, HPET_CFG
);
276 hpet_legacy_int_enabled
= true;
279 static void hpet_legacy_clockevent_register(void)
281 /* Start HPET legacy interrupts */
282 hpet_enable_legacy_int();
285 * Start hpet with the boot cpu mask and make it
286 * global after the IO_APIC has been initialized.
288 hpet_clockevent
.cpumask
= cpumask_of(smp_processor_id());
289 clockevents_config_and_register(&hpet_clockevent
, hpet_freq
,
290 HPET_MIN_PROG_DELTA
, 0x7FFFFFFF);
291 global_clock_event
= &hpet_clockevent
;
292 printk(KERN_DEBUG
"hpet clockevent registered\n");
295 static int hpet_set_periodic(struct clock_event_device
*evt
, int timer
)
297 unsigned int cfg
, cmp
, now
;
301 delta
= ((uint64_t)(NSEC_PER_SEC
/ HZ
)) * evt
->mult
;
302 delta
>>= evt
->shift
;
303 now
= hpet_readl(HPET_COUNTER
);
304 cmp
= now
+ (unsigned int)delta
;
305 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
306 cfg
|= HPET_TN_ENABLE
| HPET_TN_PERIODIC
| HPET_TN_SETVAL
|
308 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
309 hpet_writel(cmp
, HPET_Tn_CMP(timer
));
312 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
313 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
314 * bit is automatically cleared after the first write.
315 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
316 * Publication # 24674)
318 hpet_writel((unsigned int)delta
, HPET_Tn_CMP(timer
));
319 hpet_start_counter();
325 static int hpet_set_oneshot(struct clock_event_device
*evt
, int timer
)
329 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
330 cfg
&= ~HPET_TN_PERIODIC
;
331 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
332 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
337 static int hpet_shutdown(struct clock_event_device
*evt
, int timer
)
341 cfg
= hpet_readl(HPET_Tn_CFG(timer
));
342 cfg
&= ~HPET_TN_ENABLE
;
343 hpet_writel(cfg
, HPET_Tn_CFG(timer
));
348 static int hpet_resume(struct clock_event_device
*evt
, int timer
)
351 hpet_enable_legacy_int();
353 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
355 irq_domain_deactivate_irq(irq_get_irq_data(hdev
->irq
));
356 irq_domain_activate_irq(irq_get_irq_data(hdev
->irq
));
357 disable_hardirq(hdev
->irq
);
358 irq_set_affinity(hdev
->irq
, cpumask_of(hdev
->cpu
));
359 enable_irq(hdev
->irq
);
366 static int hpet_next_event(unsigned long delta
,
367 struct clock_event_device
*evt
, int timer
)
372 cnt
= hpet_readl(HPET_COUNTER
);
374 hpet_writel(cnt
, HPET_Tn_CMP(timer
));
377 * HPETs are a complete disaster. The compare register is
378 * based on a equal comparison and neither provides a less
379 * than or equal functionality (which would require to take
380 * the wraparound into account) nor a simple count down event
381 * mode. Further the write to the comparator register is
382 * delayed internally up to two HPET clock cycles in certain
383 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
384 * longer delays. We worked around that by reading back the
385 * compare register, but that required another workaround for
386 * ICH9,10 chips where the first readout after write can
387 * return the old stale value. We already had a minimum
388 * programming delta of 5us enforced, but a NMI or SMI hitting
389 * between the counter readout and the comparator write can
390 * move us behind that point easily. Now instead of reading
391 * the compare register back several times, we make the ETIME
392 * decision based on the following: Return ETIME if the
393 * counter value after the write is less than HPET_MIN_CYCLES
394 * away from the event or if the counter is already ahead of
395 * the event. The minimum programming delta for the generic
396 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
398 res
= (s32
)(cnt
- hpet_readl(HPET_COUNTER
));
400 return res
< HPET_MIN_CYCLES
? -ETIME
: 0;
403 static int hpet_legacy_shutdown(struct clock_event_device
*evt
)
405 return hpet_shutdown(evt
, 0);
408 static int hpet_legacy_set_oneshot(struct clock_event_device
*evt
)
410 return hpet_set_oneshot(evt
, 0);
413 static int hpet_legacy_set_periodic(struct clock_event_device
*evt
)
415 return hpet_set_periodic(evt
, 0);
418 static int hpet_legacy_resume(struct clock_event_device
*evt
)
420 return hpet_resume(evt
, 0);
423 static int hpet_legacy_next_event(unsigned long delta
,
424 struct clock_event_device
*evt
)
426 return hpet_next_event(delta
, evt
, 0);
430 * The hpet clock event device
432 static struct clock_event_device hpet_clockevent
= {
434 .features
= CLOCK_EVT_FEAT_PERIODIC
|
435 CLOCK_EVT_FEAT_ONESHOT
,
436 .set_state_periodic
= hpet_legacy_set_periodic
,
437 .set_state_oneshot
= hpet_legacy_set_oneshot
,
438 .set_state_shutdown
= hpet_legacy_shutdown
,
439 .tick_resume
= hpet_legacy_resume
,
440 .set_next_event
= hpet_legacy_next_event
,
448 #ifdef CONFIG_PCI_MSI
450 static DEFINE_PER_CPU(struct hpet_dev
*, cpu_hpet_dev
);
451 static struct hpet_dev
*hpet_devs
;
452 static struct irq_domain
*hpet_domain
;
454 void hpet_msi_unmask(struct irq_data
*data
)
456 struct hpet_dev
*hdev
= irq_data_get_irq_handler_data(data
);
460 cfg
= hpet_readl(HPET_Tn_CFG(hdev
->num
));
461 cfg
|= HPET_TN_ENABLE
| HPET_TN_FSB
;
462 hpet_writel(cfg
, HPET_Tn_CFG(hdev
->num
));
465 void hpet_msi_mask(struct irq_data
*data
)
467 struct hpet_dev
*hdev
= irq_data_get_irq_handler_data(data
);
471 cfg
= hpet_readl(HPET_Tn_CFG(hdev
->num
));
472 cfg
&= ~(HPET_TN_ENABLE
| HPET_TN_FSB
);
473 hpet_writel(cfg
, HPET_Tn_CFG(hdev
->num
));
476 void hpet_msi_write(struct hpet_dev
*hdev
, struct msi_msg
*msg
)
478 hpet_writel(msg
->data
, HPET_Tn_ROUTE(hdev
->num
));
479 hpet_writel(msg
->address_lo
, HPET_Tn_ROUTE(hdev
->num
) + 4);
482 void hpet_msi_read(struct hpet_dev
*hdev
, struct msi_msg
*msg
)
484 msg
->data
= hpet_readl(HPET_Tn_ROUTE(hdev
->num
));
485 msg
->address_lo
= hpet_readl(HPET_Tn_ROUTE(hdev
->num
) + 4);
489 static int hpet_msi_shutdown(struct clock_event_device
*evt
)
491 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
493 return hpet_shutdown(evt
, hdev
->num
);
496 static int hpet_msi_set_oneshot(struct clock_event_device
*evt
)
498 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
500 return hpet_set_oneshot(evt
, hdev
->num
);
503 static int hpet_msi_set_periodic(struct clock_event_device
*evt
)
505 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
507 return hpet_set_periodic(evt
, hdev
->num
);
510 static int hpet_msi_resume(struct clock_event_device
*evt
)
512 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
514 return hpet_resume(evt
, hdev
->num
);
517 static int hpet_msi_next_event(unsigned long delta
,
518 struct clock_event_device
*evt
)
520 struct hpet_dev
*hdev
= EVT_TO_HPET_DEV(evt
);
521 return hpet_next_event(delta
, evt
, hdev
->num
);
524 static irqreturn_t
hpet_interrupt_handler(int irq
, void *data
)
526 struct hpet_dev
*dev
= (struct hpet_dev
*)data
;
527 struct clock_event_device
*hevt
= &dev
->evt
;
529 if (!hevt
->event_handler
) {
530 printk(KERN_INFO
"Spurious HPET timer interrupt on HPET timer %d\n",
535 hevt
->event_handler(hevt
);
539 static int hpet_setup_irq(struct hpet_dev
*dev
)
542 if (request_irq(dev
->irq
, hpet_interrupt_handler
,
543 IRQF_TIMER
| IRQF_NOBALANCING
,
547 disable_irq(dev
->irq
);
548 irq_set_affinity(dev
->irq
, cpumask_of(dev
->cpu
));
549 enable_irq(dev
->irq
);
551 printk(KERN_DEBUG
"hpet: %s irq %d for MSI\n",
552 dev
->name
, dev
->irq
);
557 /* This should be called in specific @cpu */
558 static void init_one_hpet_msi_clockevent(struct hpet_dev
*hdev
, int cpu
)
560 struct clock_event_device
*evt
= &hdev
->evt
;
562 WARN_ON(cpu
!= smp_processor_id());
563 if (!(hdev
->flags
& HPET_DEV_VALID
))
567 per_cpu(cpu_hpet_dev
, cpu
) = hdev
;
568 evt
->name
= hdev
->name
;
569 hpet_setup_irq(hdev
);
570 evt
->irq
= hdev
->irq
;
573 evt
->features
= CLOCK_EVT_FEAT_ONESHOT
;
574 if (hdev
->flags
& HPET_DEV_PERI_CAP
) {
575 evt
->features
|= CLOCK_EVT_FEAT_PERIODIC
;
576 evt
->set_state_periodic
= hpet_msi_set_periodic
;
579 evt
->set_state_shutdown
= hpet_msi_shutdown
;
580 evt
->set_state_oneshot
= hpet_msi_set_oneshot
;
581 evt
->tick_resume
= hpet_msi_resume
;
582 evt
->set_next_event
= hpet_msi_next_event
;
583 evt
->cpumask
= cpumask_of(hdev
->cpu
);
585 clockevents_config_and_register(evt
, hpet_freq
, HPET_MIN_PROG_DELTA
,
590 /* Reserve at least one timer for userspace (/dev/hpet) */
591 #define RESERVE_TIMERS 1
593 #define RESERVE_TIMERS 0
596 static void hpet_msi_capability_lookup(unsigned int start_timer
)
599 unsigned int num_timers
;
600 unsigned int num_timers_used
= 0;
603 if (hpet_msi_disable
)
606 if (boot_cpu_has(X86_FEATURE_ARAT
))
608 id
= hpet_readl(HPET_ID
);
610 num_timers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
);
611 num_timers
++; /* Value read out starts from 0 */
614 hpet_domain
= hpet_create_irq_domain(hpet_blockid
);
618 hpet_devs
= kzalloc(sizeof(struct hpet_dev
) * num_timers
, GFP_KERNEL
);
622 hpet_num_timers
= num_timers
;
624 for (i
= start_timer
; i
< num_timers
- RESERVE_TIMERS
; i
++) {
625 struct hpet_dev
*hdev
= &hpet_devs
[num_timers_used
];
626 unsigned int cfg
= hpet_readl(HPET_Tn_CFG(i
));
628 /* Only consider HPET timer with MSI support */
629 if (!(cfg
& HPET_TN_FSB_CAP
))
633 if (cfg
& HPET_TN_PERIODIC_CAP
)
634 hdev
->flags
|= HPET_DEV_PERI_CAP
;
635 sprintf(hdev
->name
, "hpet%d", i
);
638 irq
= hpet_assign_irq(hpet_domain
, hdev
, hdev
->num
);
643 hdev
->flags
|= HPET_DEV_FSB_CAP
;
644 hdev
->flags
|= HPET_DEV_VALID
;
646 if (num_timers_used
== num_possible_cpus())
650 printk(KERN_INFO
"HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
651 num_timers
, num_timers_used
);
655 static void hpet_reserve_msi_timers(struct hpet_data
*hd
)
662 for (i
= 0; i
< hpet_num_timers
; i
++) {
663 struct hpet_dev
*hdev
= &hpet_devs
[i
];
665 if (!(hdev
->flags
& HPET_DEV_VALID
))
668 hd
->hd_irq
[hdev
->num
] = hdev
->irq
;
669 hpet_reserve_timer(hd
, hdev
->num
);
674 static struct hpet_dev
*hpet_get_unused_timer(void)
681 for (i
= 0; i
< hpet_num_timers
; i
++) {
682 struct hpet_dev
*hdev
= &hpet_devs
[i
];
684 if (!(hdev
->flags
& HPET_DEV_VALID
))
686 if (test_and_set_bit(HPET_DEV_USED_BIT
,
687 (unsigned long *)&hdev
->flags
))
694 struct hpet_work_struct
{
695 struct delayed_work work
;
696 struct completion complete
;
699 static void hpet_work(struct work_struct
*w
)
701 struct hpet_dev
*hdev
;
702 int cpu
= smp_processor_id();
703 struct hpet_work_struct
*hpet_work
;
705 hpet_work
= container_of(w
, struct hpet_work_struct
, work
.work
);
707 hdev
= hpet_get_unused_timer();
709 init_one_hpet_msi_clockevent(hdev
, cpu
);
711 complete(&hpet_work
->complete
);
714 static int hpet_cpuhp_online(unsigned int cpu
)
716 struct hpet_work_struct work
;
718 INIT_DELAYED_WORK_ONSTACK(&work
.work
, hpet_work
);
719 init_completion(&work
.complete
);
720 /* FIXME: add schedule_work_on() */
721 schedule_delayed_work_on(cpu
, &work
.work
, 0);
722 wait_for_completion(&work
.complete
);
723 destroy_delayed_work_on_stack(&work
.work
);
727 static int hpet_cpuhp_dead(unsigned int cpu
)
729 struct hpet_dev
*hdev
= per_cpu(cpu_hpet_dev
, cpu
);
733 free_irq(hdev
->irq
, hdev
);
734 hdev
->flags
&= ~HPET_DEV_USED
;
735 per_cpu(cpu_hpet_dev
, cpu
) = NULL
;
740 static void hpet_msi_capability_lookup(unsigned int start_timer
)
746 static void hpet_reserve_msi_timers(struct hpet_data
*hd
)
752 #define hpet_cpuhp_online NULL
753 #define hpet_cpuhp_dead NULL
758 * Clock source related code
760 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
762 * Reading the HPET counter is a very slow operation. If a large number of
763 * CPUs are trying to access the HPET counter simultaneously, it can cause
764 * massive delay and slow down system performance dramatically. This may
765 * happen when HPET is the default clock source instead of TSC. For a
766 * really large system with hundreds of CPUs, the slowdown may be so
767 * severe that it may actually crash the system because of a NMI watchdog
768 * soft lockup, for example.
770 * If multiple CPUs are trying to access the HPET counter at the same time,
771 * we don't actually need to read the counter multiple times. Instead, the
772 * other CPUs can use the counter value read by the first CPU in the group.
774 * This special feature is only enabled on x86-64 systems. It is unlikely
775 * that 32-bit x86 systems will have enough CPUs to require this feature
776 * with its associated locking overhead. And we also need 64-bit atomic
779 * The lock and the hpet value are stored together and can be read in a
780 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
781 * is 32 bits in size.
785 arch_spinlock_t lock
;
791 static union hpet_lock hpet __cacheline_aligned
= {
792 { .lock
= __ARCH_SPIN_LOCK_UNLOCKED
, },
795 static u64
read_hpet(struct clocksource
*cs
)
798 union hpet_lock old
, new;
800 BUILD_BUG_ON(sizeof(union hpet_lock
) != 8);
803 * Read HPET directly if in NMI.
806 return (u64
)hpet_readl(HPET_COUNTER
);
809 * Read the current state of the lock and HPET value atomically.
811 old
.lockval
= READ_ONCE(hpet
.lockval
);
813 if (arch_spin_is_locked(&old
.lock
))
816 local_irq_save(flags
);
817 if (arch_spin_trylock(&hpet
.lock
)) {
818 new.value
= hpet_readl(HPET_COUNTER
);
820 * Use WRITE_ONCE() to prevent store tearing.
822 WRITE_ONCE(hpet
.value
, new.value
);
823 arch_spin_unlock(&hpet
.lock
);
824 local_irq_restore(flags
);
825 return (u64
)new.value
;
827 local_irq_restore(flags
);
833 * Wait until the HPET value change or the lock is free to indicate
834 * its value is up-to-date.
836 * It is possible that old.value has already contained the latest
837 * HPET value while the lock holder was in the process of releasing
838 * the lock. Checking for lock state change will enable us to return
839 * the value immediately instead of waiting for the next HPET reader
844 new.lockval
= READ_ONCE(hpet
.lockval
);
845 } while ((new.value
== old
.value
) && arch_spin_is_locked(&new.lock
));
847 return (u64
)new.value
;
853 static u64
read_hpet(struct clocksource
*cs
)
855 return (u64
)hpet_readl(HPET_COUNTER
);
859 static struct clocksource clocksource_hpet
= {
864 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
865 .resume
= hpet_resume_counter
,
868 static int hpet_clocksource_register(void)
873 /* Start the counter */
874 hpet_restart_counter();
876 /* Verify whether hpet counter works */
877 t1
= hpet_readl(HPET_COUNTER
);
881 * We don't know the TSC frequency yet, but waiting for
882 * 200000 TSC cycles is safe:
889 } while ((now
- start
) < 200000UL);
891 if (t1
== hpet_readl(HPET_COUNTER
)) {
893 "HPET counter not counting. HPET disabled\n");
897 clocksource_register_hz(&clocksource_hpet
, (u32
)hpet_freq
);
901 static u32
*hpet_boot_cfg
;
904 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
906 int __init
hpet_enable(void)
908 u32 hpet_period
, cfg
, id
;
910 unsigned int i
, last
;
912 if (!is_hpet_capable())
918 * Read the period and check for a sane value:
920 hpet_period
= hpet_readl(HPET_PERIOD
);
923 * AMD SB700 based systems with spread spectrum enabled use a
924 * SMM based HPET emulation to provide proper frequency
925 * setting. The SMM code is initialized with the first HPET
926 * register access and takes some time to complete. During
927 * this time the config register reads 0xffffffff. We check
928 * for max. 1000 loops whether the config register reads a non
929 * 0xffffffff value to make sure that HPET is up and running
930 * before we go further. A counting loop is safe, as the HPET
931 * access takes thousands of CPU cycles. On non SB700 based
932 * machines this check is only done once and has no side
935 for (i
= 0; hpet_readl(HPET_CFG
) == 0xFFFFFFFF; i
++) {
938 "HPET config register value = 0xFFFFFFFF. "
944 if (hpet_period
< HPET_MIN_PERIOD
|| hpet_period
> HPET_MAX_PERIOD
)
948 * The period is a femto seconds value. Convert it to a
952 do_div(freq
, hpet_period
);
956 * Read the HPET ID register to retrieve the IRQ routing
957 * information and the number of channels
959 id
= hpet_readl(HPET_ID
);
962 last
= (id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
;
964 #ifdef CONFIG_HPET_EMULATE_RTC
966 * The legacy routing mode needs at least two channels, tick timer
967 * and the rtc emulation channel.
973 cfg
= hpet_readl(HPET_CFG
);
974 hpet_boot_cfg
= kmalloc((last
+ 2) * sizeof(*hpet_boot_cfg
),
977 *hpet_boot_cfg
= cfg
;
979 pr_warn("HPET initial state will not be saved\n");
980 cfg
&= ~(HPET_CFG_ENABLE
| HPET_CFG_LEGACY
);
981 hpet_writel(cfg
, HPET_CFG
);
983 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
986 for (i
= 0; i
<= last
; ++i
) {
987 cfg
= hpet_readl(HPET_Tn_CFG(i
));
989 hpet_boot_cfg
[i
+ 1] = cfg
;
990 cfg
&= ~(HPET_TN_ENABLE
| HPET_TN_LEVEL
| HPET_TN_FSB
);
991 hpet_writel(cfg
, HPET_Tn_CFG(i
));
992 cfg
&= ~(HPET_TN_PERIODIC
| HPET_TN_PERIODIC_CAP
993 | HPET_TN_64BIT_CAP
| HPET_TN_32BIT
| HPET_TN_ROUTE
994 | HPET_TN_FSB
| HPET_TN_FSB_CAP
);
996 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
1001 if (hpet_clocksource_register())
1004 if (id
& HPET_ID_LEGSUP
) {
1005 hpet_legacy_clockevent_register();
1011 hpet_clear_mapping();
1017 * Needs to be late, as the reserve_timer code calls kalloc !
1019 * Not a problem on i386 as hpet_enable is called from late_time_init,
1020 * but on x86_64 it is necessary !
1022 static __init
int hpet_late_init(void)
1026 if (boot_hpet_disable
)
1029 if (!hpet_address
) {
1030 if (!force_hpet_address
)
1033 hpet_address
= force_hpet_address
;
1037 if (!hpet_virt_address
)
1040 if (hpet_readl(HPET_ID
) & HPET_ID_LEGSUP
)
1041 hpet_msi_capability_lookup(2);
1043 hpet_msi_capability_lookup(0);
1045 hpet_reserve_platform_timers(hpet_readl(HPET_ID
));
1046 hpet_print_config();
1048 if (hpet_msi_disable
)
1051 if (boot_cpu_has(X86_FEATURE_ARAT
))
1054 /* This notifier should be called after workqueue is ready */
1055 ret
= cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE
, "x86/hpet:online",
1056 hpet_cpuhp_online
, NULL
);
1059 ret
= cpuhp_setup_state(CPUHP_X86_HPET_DEAD
, "x86/hpet:dead", NULL
,
1066 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE
);
1069 fs_initcall(hpet_late_init
);
1071 void hpet_disable(void)
1073 if (is_hpet_capable() && hpet_virt_address
) {
1074 unsigned int cfg
= hpet_readl(HPET_CFG
), id
, last
;
1077 cfg
= *hpet_boot_cfg
;
1078 else if (hpet_legacy_int_enabled
) {
1079 cfg
&= ~HPET_CFG_LEGACY
;
1080 hpet_legacy_int_enabled
= false;
1082 cfg
&= ~HPET_CFG_ENABLE
;
1083 hpet_writel(cfg
, HPET_CFG
);
1088 id
= hpet_readl(HPET_ID
);
1089 last
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
);
1091 for (id
= 0; id
<= last
; ++id
)
1092 hpet_writel(hpet_boot_cfg
[id
+ 1], HPET_Tn_CFG(id
));
1094 if (*hpet_boot_cfg
& HPET_CFG_ENABLE
)
1095 hpet_writel(*hpet_boot_cfg
, HPET_CFG
);
1099 #ifdef CONFIG_HPET_EMULATE_RTC
1101 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1102 * is enabled, we support RTC interrupt functionality in software.
1103 * RTC has 3 kinds of interrupts:
1104 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1106 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1107 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1108 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1109 * (1) and (2) above are implemented using polling at a frequency of
1110 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1111 * overhead. (DEFAULT_RTC_INT_FREQ)
1112 * For (3), we use interrupts at 64Hz or user specified periodic
1113 * frequency, whichever is higher.
1115 #include <linux/mc146818rtc.h>
1116 #include <linux/rtc.h>
1118 #define DEFAULT_RTC_INT_FREQ 64
1119 #define DEFAULT_RTC_SHIFT 6
1120 #define RTC_NUM_INTS 1
1122 static unsigned long hpet_rtc_flags
;
1123 static int hpet_prev_update_sec
;
1124 static struct rtc_time hpet_alarm_time
;
1125 static unsigned long hpet_pie_count
;
1126 static u32 hpet_t1_cmp
;
1127 static u32 hpet_default_delta
;
1128 static u32 hpet_pie_delta
;
1129 static unsigned long hpet_pie_limit
;
1131 static rtc_irq_handler irq_handler
;
1134 * Check that the hpet counter c1 is ahead of the c2
1136 static inline int hpet_cnt_ahead(u32 c1
, u32 c2
)
1138 return (s32
)(c2
- c1
) < 0;
1142 * Registers a IRQ handler.
1144 int hpet_register_irq_handler(rtc_irq_handler handler
)
1146 if (!is_hpet_enabled())
1151 irq_handler
= handler
;
1155 EXPORT_SYMBOL_GPL(hpet_register_irq_handler
);
1158 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1161 void hpet_unregister_irq_handler(rtc_irq_handler handler
)
1163 if (!is_hpet_enabled())
1169 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler
);
1172 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1173 * is not supported by all HPET implementations for timer 1.
1175 * hpet_rtc_timer_init() is called when the rtc is initialized.
1177 int hpet_rtc_timer_init(void)
1179 unsigned int cfg
, cnt
, delta
;
1180 unsigned long flags
;
1182 if (!is_hpet_enabled())
1185 if (!hpet_default_delta
) {
1188 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
1189 clc
>>= hpet_clockevent
.shift
+ DEFAULT_RTC_SHIFT
;
1190 hpet_default_delta
= clc
;
1193 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
1194 delta
= hpet_default_delta
;
1196 delta
= hpet_pie_delta
;
1198 local_irq_save(flags
);
1200 cnt
= delta
+ hpet_readl(HPET_COUNTER
);
1201 hpet_writel(cnt
, HPET_T1_CMP
);
1204 cfg
= hpet_readl(HPET_T1_CFG
);
1205 cfg
&= ~HPET_TN_PERIODIC
;
1206 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
1207 hpet_writel(cfg
, HPET_T1_CFG
);
1209 local_irq_restore(flags
);
1213 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init
);
1215 static void hpet_disable_rtc_channel(void)
1217 u32 cfg
= hpet_readl(HPET_T1_CFG
);
1218 cfg
&= ~HPET_TN_ENABLE
;
1219 hpet_writel(cfg
, HPET_T1_CFG
);
1223 * The functions below are called from rtc driver.
1224 * Return 0 if HPET is not being used.
1225 * Otherwise do the necessary changes and return 1.
1227 int hpet_mask_rtc_irq_bit(unsigned long bit_mask
)
1229 if (!is_hpet_enabled())
1232 hpet_rtc_flags
&= ~bit_mask
;
1233 if (unlikely(!hpet_rtc_flags
))
1234 hpet_disable_rtc_channel();
1238 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit
);
1240 int hpet_set_rtc_irq_bit(unsigned long bit_mask
)
1242 unsigned long oldbits
= hpet_rtc_flags
;
1244 if (!is_hpet_enabled())
1247 hpet_rtc_flags
|= bit_mask
;
1249 if ((bit_mask
& RTC_UIE
) && !(oldbits
& RTC_UIE
))
1250 hpet_prev_update_sec
= -1;
1253 hpet_rtc_timer_init();
1257 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit
);
1259 int hpet_set_alarm_time(unsigned char hrs
, unsigned char min
,
1262 if (!is_hpet_enabled())
1265 hpet_alarm_time
.tm_hour
= hrs
;
1266 hpet_alarm_time
.tm_min
= min
;
1267 hpet_alarm_time
.tm_sec
= sec
;
1271 EXPORT_SYMBOL_GPL(hpet_set_alarm_time
);
1273 int hpet_set_periodic_freq(unsigned long freq
)
1277 if (!is_hpet_enabled())
1280 if (freq
<= DEFAULT_RTC_INT_FREQ
)
1281 hpet_pie_limit
= DEFAULT_RTC_INT_FREQ
/ freq
;
1283 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
1285 clc
>>= hpet_clockevent
.shift
;
1286 hpet_pie_delta
= clc
;
1291 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq
);
1293 int hpet_rtc_dropped_irq(void)
1295 return is_hpet_enabled();
1297 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq
);
1299 static void hpet_rtc_timer_reinit(void)
1304 if (unlikely(!hpet_rtc_flags
))
1305 hpet_disable_rtc_channel();
1307 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
1308 delta
= hpet_default_delta
;
1310 delta
= hpet_pie_delta
;
1313 * Increment the comparator value until we are ahead of the
1317 hpet_t1_cmp
+= delta
;
1318 hpet_writel(hpet_t1_cmp
, HPET_T1_CMP
);
1320 } while (!hpet_cnt_ahead(hpet_t1_cmp
, hpet_readl(HPET_COUNTER
)));
1323 if (hpet_rtc_flags
& RTC_PIE
)
1324 hpet_pie_count
+= lost_ints
;
1325 if (printk_ratelimit())
1326 printk(KERN_WARNING
"hpet1: lost %d rtc interrupts\n",
1331 irqreturn_t
hpet_rtc_interrupt(int irq
, void *dev_id
)
1333 struct rtc_time curr_time
;
1334 unsigned long rtc_int_flag
= 0;
1336 hpet_rtc_timer_reinit();
1337 memset(&curr_time
, 0, sizeof(struct rtc_time
));
1339 if (hpet_rtc_flags
& (RTC_UIE
| RTC_AIE
))
1340 mc146818_get_time(&curr_time
);
1342 if (hpet_rtc_flags
& RTC_UIE
&&
1343 curr_time
.tm_sec
!= hpet_prev_update_sec
) {
1344 if (hpet_prev_update_sec
>= 0)
1345 rtc_int_flag
= RTC_UF
;
1346 hpet_prev_update_sec
= curr_time
.tm_sec
;
1349 if (hpet_rtc_flags
& RTC_PIE
&&
1350 ++hpet_pie_count
>= hpet_pie_limit
) {
1351 rtc_int_flag
|= RTC_PF
;
1355 if (hpet_rtc_flags
& RTC_AIE
&&
1356 (curr_time
.tm_sec
== hpet_alarm_time
.tm_sec
) &&
1357 (curr_time
.tm_min
== hpet_alarm_time
.tm_min
) &&
1358 (curr_time
.tm_hour
== hpet_alarm_time
.tm_hour
))
1359 rtc_int_flag
|= RTC_AF
;
1362 rtc_int_flag
|= (RTC_IRQF
| (RTC_NUM_INTS
<< 8));
1364 irq_handler(rtc_int_flag
, dev_id
);
1368 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt
);