arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/delay.h>
   4 #include <linux/errno.h>
   5 #include <linux/hpet.h>
   6 #include <linux/init.h>
   7 #include <linux/sysdev.h>
   8 #include <linux/pm.h>
   9
  10 #include <asm/fixmap.h>
  11 #include <asm/hpet.h>
  12 #include <asm/i8253.h>
  13 #include <asm/io.h>
  14
  15 #define HPET_MASK       CLOCKSOURCE_MASK(32)
  16 #define HPET_SHIFT      22
  17
  18 /* FSEC = 10^-15
  19    NSEC = 10^-9 */
  20 #define FSEC_PER_NSEC   1000000L
  21
  22 /*
  23  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  24  */
  25 unsigned long hpet_address;
  26 static void __iomem *hpet_virt_address;
  27
  28 unsigned long hpet_readl(unsigned long a)
  29 {
  30         return readl(hpet_virt_address + a);
  31 }
  32
  33 static inline void hpet_writel(unsigned long d, unsigned long a)
  34 {
  35         writel(d, hpet_virt_address + a);
  36 }
  37
  38 #ifdef CONFIG_X86_64
  39 #include <asm/pgtable.h>
  40 #endif
  41
  42 static inline void hpet_set_mapping(void)
  43 {
  44         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  45 #ifdef CONFIG_X86_64
  46         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
  47 #endif
  48 }
  49
  50 static inline void hpet_clear_mapping(void)
  51 {
  52         iounmap(hpet_virt_address);
  53         hpet_virt_address = NULL;
  54 }
  55
  56 /*
  57  * HPET command line enable / disable
  58  */
  59 static int boot_hpet_disable;
  60 int hpet_force_user;
  61
  62 static int __init hpet_setup(char* str)
  63 {
  64         if (str) {
  65                 if (!strncmp("disable", str, 7))
  66                         boot_hpet_disable = 1;
  67                 if (!strncmp("force", str, 5))
  68                         hpet_force_user = 1;
  69         }
  70         return 1;
  71 }
  72 __setup("hpet=", hpet_setup);
  73
  74 static int __init disable_hpet(char *str)
  75 {
  76         boot_hpet_disable = 1;
  77         return 1;
  78 }
  79 __setup("nohpet", disable_hpet);
  80
  81 static inline int is_hpet_capable(void)
  82 {
  83         return (!boot_hpet_disable && hpet_address);
  84 }
  85
  86 /*
  87  * HPET timer interrupt enable / disable
  88  */
  89 static int hpet_legacy_int_enabled;
  90
  91 /**
  92  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
  93  */
  94 int is_hpet_enabled(void)
  95 {
  96         return is_hpet_capable() && hpet_legacy_int_enabled;
  97 }
  98 EXPORT_SYMBOL_GPL(is_hpet_enabled);
  99
 100 /*
 101  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 102  * timer 0 and timer 1 in case of RTC emulation.
 103  */
 104 #ifdef CONFIG_HPET
 105 static void hpet_reserve_platform_timers(unsigned long id)
 106 {
 107         struct hpet __iomem *hpet = hpet_virt_address;
 108         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 109         unsigned int nrtimers, i;
 110         struct hpet_data hd;
 111
 112         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 113
 114         memset(&hd, 0, sizeof (hd));
 115         hd.hd_phys_address = hpet_address;
 116         hd.hd_address = hpet;
 117         hd.hd_nirqs = nrtimers;
 118         hd.hd_flags = HPET_DATA_PLATFORM;
 119         hpet_reserve_timer(&hd, 0);
 120
 121 #ifdef CONFIG_HPET_EMULATE_RTC
 122         hpet_reserve_timer(&hd, 1);
 123 #endif
 124
 125         hd.hd_irq[0] = HPET_LEGACY_8254;
 126         hd.hd_irq[1] = HPET_LEGACY_RTC;
 127
 128         for (i = 2; i < nrtimers; timer++, i++) {
 129                 hd.hd_irq[i] = (readl(&timer->hpet_config) & Tn_INT_ROUTE_CNF_MASK) >>
 130                         Tn_INT_ROUTE_CNF_SHIFT;
 131         }
 132
 133         hpet_alloc(&hd);
 134
 135 }
 136 #else
 137 static void hpet_reserve_platform_timers(unsigned long id) { }
 138 #endif
 139
 140 /*
 141  * Common hpet info
 142  */
 143 static unsigned long hpet_period;
 144
 145 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 146                           struct clock_event_device *evt);
 147 static int hpet_legacy_next_event(unsigned long delta,
 148                            struct clock_event_device *evt);
 149
 150 /*
 151  * The hpet clock event device
 152  */
 153 static struct clock_event_device hpet_clockevent = {
 154         .name           = "hpet",
 155         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 156         .set_mode       = hpet_legacy_set_mode,
 157         .set_next_event = hpet_legacy_next_event,
 158         .shift          = 32,
 159         .irq            = 0,
 160         .rating         = 50,
 161 };
 162
 163 static void hpet_start_counter(void)
 164 {
 165         unsigned long cfg = hpet_readl(HPET_CFG);
 166
 167         cfg &= ~HPET_CFG_ENABLE;
 168         hpet_writel(cfg, HPET_CFG);
 169         hpet_writel(0, HPET_COUNTER);
 170         hpet_writel(0, HPET_COUNTER + 4);
 171         cfg |= HPET_CFG_ENABLE;
 172         hpet_writel(cfg, HPET_CFG);
 173 }
 174
 175 static void hpet_resume_device(void)
 176 {
 177         force_hpet_resume();
 178 }
 179
 180 static void hpet_restart_counter(void)
 181 {
 182         hpet_resume_device();
 183         hpet_start_counter();
 184 }
 185
 186 static void hpet_enable_legacy_int(void)
 187 {
 188         unsigned long cfg = hpet_readl(HPET_CFG);
 189
 190         cfg |= HPET_CFG_LEGACY;
 191         hpet_writel(cfg, HPET_CFG);
 192         hpet_legacy_int_enabled = 1;
 193 }
 194
 195 static void hpet_legacy_clockevent_register(void)
 196 {
 197         /* Start HPET legacy interrupts */
 198         hpet_enable_legacy_int();
 199
 200         /*
 201          * The mult factor is defined as (include/linux/clockchips.h)
 202          *  mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
 203          * hpet_period is in units of femtoseconds (per cycle), so
 204          *  mult/2^shift = cyc/ns = 10^6/hpet_period
 205          *  mult = (10^6 * 2^shift)/hpet_period
 206          *  mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
 207          */
 208         hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
 209                                       hpet_period, hpet_clockevent.shift);
 210         /* Calculate the min / max delta */
 211         hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
 212                                                            &hpet_clockevent);
 213         hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
 214                                                            &hpet_clockevent);
 215
 216         /*
 217          * Start hpet with the boot cpu mask and make it
 218          * global after the IO_APIC has been initialized.
 219          */
 220         hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
 221         clockevents_register_device(&hpet_clockevent);
 222         global_clock_event = &hpet_clockevent;
 223         printk(KERN_DEBUG "hpet clockevent registered\n");
 224 }
 225
 226 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 227                           struct clock_event_device *evt)
 228 {
 229         unsigned long cfg, cmp, now;
 230         uint64_t delta;
 231
 232         switch(mode) {
 233         case CLOCK_EVT_MODE_PERIODIC:
 234                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
 235                 delta >>= hpet_clockevent.shift;
 236                 now = hpet_readl(HPET_COUNTER);
 237                 cmp = now + (unsigned long) delta;
 238                 cfg = hpet_readl(HPET_T0_CFG);
 239                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 240                        HPET_TN_SETVAL | HPET_TN_32BIT;
 241                 hpet_writel(cfg, HPET_T0_CFG);
 242                 /*
 243                  * The first write after writing TN_SETVAL to the
 244                  * config register sets the counter value, the second
 245                  * write sets the period.
 246                  */
 247                 hpet_writel(cmp, HPET_T0_CMP);
 248                 udelay(1);
 249                 hpet_writel((unsigned long) delta, HPET_T0_CMP);
 250                 break;
 251
 252         case CLOCK_EVT_MODE_ONESHOT:
 253                 cfg = hpet_readl(HPET_T0_CFG);
 254                 cfg &= ~HPET_TN_PERIODIC;
 255                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 256                 hpet_writel(cfg, HPET_T0_CFG);
 257                 break;
 258
 259         case CLOCK_EVT_MODE_UNUSED:
 260         case CLOCK_EVT_MODE_SHUTDOWN:
 261                 cfg = hpet_readl(HPET_T0_CFG);
 262                 cfg &= ~HPET_TN_ENABLE;
 263                 hpet_writel(cfg, HPET_T0_CFG);
 264                 break;
 265
 266         case CLOCK_EVT_MODE_RESUME:
 267                 hpet_enable_legacy_int();
 268                 break;
 269         }
 270 }
 271
 272 static int hpet_legacy_next_event(unsigned long delta,
 273                            struct clock_event_device *evt)
 274 {
 275         unsigned long cnt;
 276
 277         cnt = hpet_readl(HPET_COUNTER);
 278         cnt += delta;
 279         hpet_writel(cnt, HPET_T0_CMP);
 280
 281         return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
 282 }
 283
 284 /*
 285  * Clock source related code
 286  */
 287 static cycle_t read_hpet(void)
 288 {
 289         return (cycle_t)hpet_readl(HPET_COUNTER);
 290 }
 291
 292 #ifdef CONFIG_X86_64
 293 static cycle_t __vsyscall_fn vread_hpet(void)
 294 {
 295         return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
 296 }
 297 #endif
 298
 299 static struct clocksource clocksource_hpet = {
 300         .name           = "hpet",
 301         .rating         = 250,
 302         .read           = read_hpet,
 303         .mask           = HPET_MASK,
 304         .shift          = HPET_SHIFT,
 305         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 306         .resume         = hpet_restart_counter,
 307 #ifdef CONFIG_X86_64
 308         .vread          = vread_hpet,
 309 #endif
 310 };
 311
 312 static int hpet_clocksource_register(void)
 313 {
 314         u64 start, now;
 315         cycle_t t1;
 316
 317         /* Start the counter */
 318         hpet_start_counter();
 319
 320         /* Verify whether hpet counter works */
 321         t1 = read_hpet();
 322         rdtscll(start);
 323
 324         /*
 325          * We don't know the TSC frequency yet, but waiting for
 326          * 200000 TSC cycles is safe:
 327          * 4 GHz == 50us
 328          * 1 GHz == 200us
 329          */
 330         do {
 331                 rep_nop();
 332                 rdtscll(now);
 333         } while ((now - start) < 200000UL);
 334
 335         if (t1 == read_hpet()) {
 336                 printk(KERN_WARNING
 337                        "HPET counter not counting. HPET disabled\n");
 338                 return -ENODEV;
 339         }
 340
 341         /*
 342          * The definition of mult is (include/linux/clocksource.h)
 343          * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
 344          * so we first need to convert hpet_period to ns/cyc units:
 345          *  mult/2^shift = ns/cyc = hpet_period/10^6
 346          *  mult = (hpet_period * 2^shift)/10^6
 347          *  mult = (hpet_period << shift)/FSEC_PER_NSEC
 348          */
 349         clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
 350
 351         clocksource_register(&clocksource_hpet);
 352
 353         return 0;
 354 }
 355
 356 /**
 357  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 358  */
 359 int __init hpet_enable(void)
 360 {
 361         unsigned long id;
 362         int i;
 363
 364         if (!is_hpet_capable())
 365                 return 0;
 366
 367         hpet_set_mapping();
 368
 369         /*
 370          * Read the period and check for a sane value:
 371          */
 372         hpet_period = hpet_readl(HPET_PERIOD);
 373
 374         /*
 375          * AMD SB700 based systems with spread spectrum enabled use a
 376          * SMM based HPET emulation to provide proper frequency
 377          * setting. The SMM code is initialized with the first HPET
 378          * register access and takes some time to complete. During
 379          * this time the config register reads 0xffffffff. We check
 380          * for max. 1000 loops whether the config register reads a non
 381          * 0xffffffff value to make sure that HPET is up and running
 382          * before we go further. A counting loop is safe, as the HPET
 383          * access takes thousands of CPU cycles. On non SB700 based
 384          * machines this check is only done once and has no side
 385          * effects.
 386          */
 387         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 388                 if (i == 1000) {
 389                         printk(KERN_WARNING
 390                                "HPET config register value = 0xFFFFFFFF. "
 391                                "Disabling HPET\n");
 392                         goto out_nohpet;
 393                 }
 394         }
 395
 396         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 397                 goto out_nohpet;
 398
 399         /*
 400          * Read the HPET ID register to retrieve the IRQ routing
 401          * information and the number of channels
 402          */
 403         id = hpet_readl(HPET_ID);
 404
 405 #ifdef CONFIG_HPET_EMULATE_RTC
 406         /*
 407          * The legacy routing mode needs at least two channels, tick timer
 408          * and the rtc emulation channel.
 409          */
 410         if (!(id & HPET_ID_NUMBER))
 411                 goto out_nohpet;
 412 #endif
 413
 414         if (hpet_clocksource_register())
 415                 goto out_nohpet;
 416
 417         if (id & HPET_ID_LEGSUP) {
 418                 hpet_legacy_clockevent_register();
 419                 return 1;
 420         }
 421         return 0;
 422
 423 out_nohpet:
 424         hpet_clear_mapping();
 425         boot_hpet_disable = 1;
 426         return 0;
 427 }
 428
 429 /*
 430  * Needs to be late, as the reserve_timer code calls kalloc !
 431  *
 432  * Not a problem on i386 as hpet_enable is called from late_time_init,
 433  * but on x86_64 it is necessary !
 434  */
 435 static __init int hpet_late_init(void)
 436 {
 437         if (boot_hpet_disable)
 438                 return -ENODEV;
 439
 440         if (!hpet_address) {
 441                 if (!force_hpet_address)
 442                         return -ENODEV;
 443
 444                 hpet_address = force_hpet_address;
 445                 hpet_enable();
 446                 if (!hpet_virt_address)
 447                         return -ENODEV;
 448         }
 449
 450         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 451
 452         return 0;
 453 }
 454 fs_initcall(hpet_late_init);
 455
 456 void hpet_disable(void)
 457 {
 458         if (is_hpet_capable()) {
 459                 unsigned long cfg = hpet_readl(HPET_CFG);
 460
 461                 if (hpet_legacy_int_enabled) {
 462                         cfg &= ~HPET_CFG_LEGACY;
 463                         hpet_legacy_int_enabled = 0;
 464                 }
 465                 cfg &= ~HPET_CFG_ENABLE;
 466                 hpet_writel(cfg, HPET_CFG);
 467         }
 468 }
 469
 470 #ifdef CONFIG_HPET_EMULATE_RTC
 471
 472 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 473  * is enabled, we support RTC interrupt functionality in software.
 474  * RTC has 3 kinds of interrupts:
 475  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 476  *    is updated
 477  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 478  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 479  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 480  * (1) and (2) above are implemented using polling at a frequency of
 481  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 482  * overhead. (DEFAULT_RTC_INT_FREQ)
 483  * For (3), we use interrupts at 64Hz or user specified periodic
 484  * frequency, whichever is higher.
 485  */
 486 #include <linux/mc146818rtc.h>
 487 #include <linux/rtc.h>
 488 #include <asm/rtc.h>
 489
 490 #define DEFAULT_RTC_INT_FREQ    64
 491 #define DEFAULT_RTC_SHIFT       6
 492 #define RTC_NUM_INTS            1
 493
 494 static unsigned long hpet_rtc_flags;
 495 static int hpet_prev_update_sec;
 496 static struct rtc_time hpet_alarm_time;
 497 static unsigned long hpet_pie_count;
 498 static unsigned long hpet_t1_cmp;
 499 static unsigned long hpet_default_delta;
 500 static unsigned long hpet_pie_delta;
 501 static unsigned long hpet_pie_limit;
 502
 503 static rtc_irq_handler irq_handler;
 504
 505 /*
 506  * Registers a IRQ handler.
 507  */
 508 int hpet_register_irq_handler(rtc_irq_handler handler)
 509 {
 510         if (!is_hpet_enabled())
 511                 return -ENODEV;
 512         if (irq_handler)
 513                 return -EBUSY;
 514
 515         irq_handler = handler;
 516
 517         return 0;
 518 }
 519 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
 520
 521 /*
 522  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
 523  * and does cleanup.
 524  */
 525 void hpet_unregister_irq_handler(rtc_irq_handler handler)
 526 {
 527         if (!is_hpet_enabled())
 528                 return;
 529
 530         irq_handler = NULL;
 531         hpet_rtc_flags = 0;
 532 }
 533 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
 534
 535 /*
 536  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 537  * is not supported by all HPET implementations for timer 1.
 538  *
 539  * hpet_rtc_timer_init() is called when the rtc is initialized.
 540  */
 541 int hpet_rtc_timer_init(void)
 542 {
 543         unsigned long cfg, cnt, delta, flags;
 544
 545         if (!is_hpet_enabled())
 546                 return 0;
 547
 548         if (!hpet_default_delta) {
 549                 uint64_t clc;
 550
 551                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
 552                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
 553                 hpet_default_delta = (unsigned long) clc;
 554         }
 555
 556         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
 557                 delta = hpet_default_delta;
 558         else
 559                 delta = hpet_pie_delta;
 560
 561         local_irq_save(flags);
 562
 563         cnt = delta + hpet_readl(HPET_COUNTER);
 564         hpet_writel(cnt, HPET_T1_CMP);
 565         hpet_t1_cmp = cnt;
 566
 567         cfg = hpet_readl(HPET_T1_CFG);
 568         cfg &= ~HPET_TN_PERIODIC;
 569         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 570         hpet_writel(cfg, HPET_T1_CFG);
 571
 572         local_irq_restore(flags);
 573
 574         return 1;
 575 }
 576 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
 577
 578 /*
 579  * The functions below are called from rtc driver.
 580  * Return 0 if HPET is not being used.
 581  * Otherwise do the necessary changes and return 1.
 582  */
 583 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
 584 {
 585         if (!is_hpet_enabled())
 586                 return 0;
 587
 588         hpet_rtc_flags &= ~bit_mask;
 589         return 1;
 590 }
 591 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
 592
 593 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
 594 {
 595         unsigned long oldbits = hpet_rtc_flags;
 596
 597         if (!is_hpet_enabled())
 598                 return 0;
 599
 600         hpet_rtc_flags |= bit_mask;
 601
 602         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
 603                 hpet_prev_update_sec = -1;
 604
 605         if (!oldbits)
 606                 hpet_rtc_timer_init();
 607
 608         return 1;
 609 }
 610 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
 611
 612 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
 613                         unsigned char sec)
 614 {
 615         if (!is_hpet_enabled())
 616                 return 0;
 617
 618         hpet_alarm_time.tm_hour = hrs;
 619         hpet_alarm_time.tm_min = min;
 620         hpet_alarm_time.tm_sec = sec;
 621
 622         return 1;
 623 }
 624 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
 625
 626 int hpet_set_periodic_freq(unsigned long freq)
 627 {
 628         uint64_t clc;
 629
 630         if (!is_hpet_enabled())
 631                 return 0;
 632
 633         if (freq <= DEFAULT_RTC_INT_FREQ)
 634                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
 635         else {
 636                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
 637                 do_div(clc, freq);
 638                 clc >>= hpet_clockevent.shift;
 639                 hpet_pie_delta = (unsigned long) clc;
 640         }
 641         return 1;
 642 }
 643 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
 644
 645 int hpet_rtc_dropped_irq(void)
 646 {
 647         return is_hpet_enabled();
 648 }
 649 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
 650
 651 static void hpet_rtc_timer_reinit(void)
 652 {
 653         unsigned long cfg, delta;
 654         int lost_ints = -1;
 655
 656         if (unlikely(!hpet_rtc_flags)) {
 657                 cfg = hpet_readl(HPET_T1_CFG);
 658                 cfg &= ~HPET_TN_ENABLE;
 659                 hpet_writel(cfg, HPET_T1_CFG);
 660                 return;
 661         }
 662
 663         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
 664                 delta = hpet_default_delta;
 665         else
 666                 delta = hpet_pie_delta;
 667
 668         /*
 669          * Increment the comparator value until we are ahead of the
 670          * current count.
 671          */
 672         do {
 673                 hpet_t1_cmp += delta;
 674                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
 675                 lost_ints++;
 676         } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
 677
 678         if (lost_ints) {
 679                 if (hpet_rtc_flags & RTC_PIE)
 680                         hpet_pie_count += lost_ints;
 681                 if (printk_ratelimit())
 682                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
 683                                 lost_ints);
 684         }
 685 }
 686
 687 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
 688 {
 689         struct rtc_time curr_time;
 690         unsigned long rtc_int_flag = 0;
 691
 692         hpet_rtc_timer_reinit();
 693         memset(&curr_time, 0, sizeof(struct rtc_time));
 694
 695         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
 696                 get_rtc_time(&curr_time);
 697
 698         if (hpet_rtc_flags & RTC_UIE &&
 699             curr_time.tm_sec != hpet_prev_update_sec) {
 700                 if (hpet_prev_update_sec >= 0)
 701                         rtc_int_flag = RTC_UF;
 702                 hpet_prev_update_sec = curr_time.tm_sec;
 703         }
 704
 705         if (hpet_rtc_flags & RTC_PIE &&
 706             ++hpet_pie_count >= hpet_pie_limit) {
 707                 rtc_int_flag |= RTC_PF;
 708                 hpet_pie_count = 0;
 709         }
 710
 711         if (hpet_rtc_flags & RTC_AIE &&
 712             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
 713             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
 714             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
 715                         rtc_int_flag |= RTC_AF;
 716
 717         if (rtc_int_flag) {
 718                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
 719                 if (irq_handler)
 720                         irq_handler(rtc_int_flag, dev_id);
 721         }
 722         return IRQ_HANDLED;
 723 }
 724 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
 725 #endif