arch/x86/kernel/i8259.c

   1 #include <linux/linkage.h>
   2 #include <linux/errno.h>
   3 #include <linux/signal.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/timex.h>
   8 #include <linux/random.h>
   9 #include <linux/init.h>
  10 #include <linux/kernel_stat.h>
  11 #include <linux/sysdev.h>
  12 #include <linux/bitops.h>
  13 #include <linux/acpi.h>
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16
  17 #include <asm/atomic.h>
  18 #include <asm/system.h>
  19 #include <asm/timer.h>
  20 #include <asm/hw_irq.h>
  21 #include <asm/pgtable.h>
  22 #include <asm/desc.h>
  23 #include <asm/apic.h>
  24 #include <asm/i8259.h>
  25
  26 /*
  27  * This is the 'legacy' 8259A Programmable Interrupt Controller,
  28  * present in the majority of PC/AT boxes.
  29  * plus some generic x86 specific things if generic specifics makes
  30  * any sense at all.
  31  */
  32
  33 static int i8259A_auto_eoi;
  34 DEFINE_RAW_SPINLOCK(i8259A_lock);
  35 static void mask_and_ack_8259A(unsigned int);
  36 static void mask_8259A(void);
  37 static void unmask_8259A(void);
  38 static void disable_8259A_irq(unsigned int irq);
  39 static void enable_8259A_irq(unsigned int irq);
  40 static void init_8259A(int auto_eoi);
  41 static int i8259A_irq_pending(unsigned int irq);
  42
  43 struct irq_chip i8259A_chip = {
  44         .name           = "XT-PIC",
  45         .mask           = disable_8259A_irq,
  46         .disable        = disable_8259A_irq,
  47         .unmask         = enable_8259A_irq,
  48         .mask_ack       = mask_and_ack_8259A,
  49 };
  50
  51 /*
  52  * 8259A PIC functions to handle ISA devices:
  53  */
  54
  55 /*
  56  * This contains the irq mask for both 8259A irq controllers,
  57  */
  58 unsigned int cached_irq_mask = 0xffff;
  59
  60 /*
  61  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
  62  * boards the timer interrupt is not really connected to any IO-APIC pin,
  63  * it's fed to the master 8259A's IR0 line only.
  64  *
  65  * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
  66  * this 'mixed mode' IRQ handling costs nothing because it's only used
  67  * at IRQ setup time.
  68  */
  69 unsigned long io_apic_irqs;
  70
  71 static void disable_8259A_irq(unsigned int irq)
  72 {
  73         unsigned int mask = 1 << irq;
  74         unsigned long flags;
  75
  76         raw_spin_lock_irqsave(&i8259A_lock, flags);
  77         cached_irq_mask |= mask;
  78         if (irq & 8)
  79                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  80         else
  81                 outb(cached_master_mask, PIC_MASTER_IMR);
  82         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
  83 }
  84
  85 static void enable_8259A_irq(unsigned int irq)
  86 {
  87         unsigned int mask = ~(1 << irq);
  88         unsigned long flags;
  89
  90         raw_spin_lock_irqsave(&i8259A_lock, flags);
  91         cached_irq_mask &= mask;
  92         if (irq & 8)
  93                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  94         else
  95                 outb(cached_master_mask, PIC_MASTER_IMR);
  96         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
  97 }
  98
  99 static int i8259A_irq_pending(unsigned int irq)
 100 {
 101         unsigned int mask = 1<<irq;
 102         unsigned long flags;
 103         int ret;
 104
 105         raw_spin_lock_irqsave(&i8259A_lock, flags);
 106         if (irq < 8)
 107                 ret = inb(PIC_MASTER_CMD) & mask;
 108         else
 109                 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
 110         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 111
 112         return ret;
 113 }
 114
 115 static void make_8259A_irq(unsigned int irq)
 116 {
 117         disable_irq_nosync(irq);
 118         io_apic_irqs &= ~(1<<irq);
 119         set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
 120                                       "XT");
 121         enable_irq(irq);
 122 }
 123
 124 /*
 125  * This function assumes to be called rarely. Switching between
 126  * 8259A registers is slow.
 127  * This has to be protected by the irq controller spinlock
 128  * before being called.
 129  */
 130 static inline int i8259A_irq_real(unsigned int irq)
 131 {
 132         int value;
 133         int irqmask = 1<<irq;
 134
 135         if (irq < 8) {
 136                 outb(0x0B, PIC_MASTER_CMD);     /* ISR register */
 137                 value = inb(PIC_MASTER_CMD) & irqmask;
 138                 outb(0x0A, PIC_MASTER_CMD);     /* back to the IRR register */
 139                 return value;
 140         }
 141         outb(0x0B, PIC_SLAVE_CMD);      /* ISR register */
 142         value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
 143         outb(0x0A, PIC_SLAVE_CMD);      /* back to the IRR register */
 144         return value;
 145 }
 146
 147 /*
 148  * Careful! The 8259A is a fragile beast, it pretty
 149  * much _has_ to be done exactly like this (mask it
 150  * first, _then_ send the EOI, and the order of EOI
 151  * to the two 8259s is important!
 152  */
 153 static void mask_and_ack_8259A(unsigned int irq)
 154 {
 155         unsigned int irqmask = 1 << irq;
 156         unsigned long flags;
 157
 158         raw_spin_lock_irqsave(&i8259A_lock, flags);
 159         /*
 160          * Lightweight spurious IRQ detection. We do not want
 161          * to overdo spurious IRQ handling - it's usually a sign
 162          * of hardware problems, so we only do the checks we can
 163          * do without slowing down good hardware unnecessarily.
 164          *
 165          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 166          * usually resulting from the 8259A-1|2 PICs) occur
 167          * even if the IRQ is masked in the 8259A. Thus we
 168          * can check spurious 8259A IRQs without doing the
 169          * quite slow i8259A_irq_real() call for every IRQ.
 170          * This does not cover 100% of spurious interrupts,
 171          * but should be enough to warn the user that there
 172          * is something bad going on ...
 173          */
 174         if (cached_irq_mask & irqmask)
 175                 goto spurious_8259A_irq;
 176         cached_irq_mask |= irqmask;
 177
 178 handle_real_irq:
 179         if (irq & 8) {
 180                 inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
 181                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 182                 /* 'Specific EOI' to slave */
 183                 outb(0x60+(irq&7), PIC_SLAVE_CMD);
 184                  /* 'Specific EOI' to master-IRQ2 */
 185                 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
 186         } else {
 187                 inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
 188                 outb(cached_master_mask, PIC_MASTER_IMR);
 189                 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
 190         }
 191         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 192         return;
 193
 194 spurious_8259A_irq:
 195         /*
 196          * this is the slow path - should happen rarely.
 197          */
 198         if (i8259A_irq_real(irq))
 199                 /*
 200                  * oops, the IRQ _is_ in service according to the
 201                  * 8259A - not spurious, go handle it.
 202                  */
 203                 goto handle_real_irq;
 204
 205         {
 206                 static int spurious_irq_mask;
 207                 /*
 208                  * At this point we can be sure the IRQ is spurious,
 209                  * lets ACK and report it. [once per IRQ]
 210                  */
 211                 if (!(spurious_irq_mask & irqmask)) {
 212                         printk(KERN_DEBUG
 213                                "spurious 8259A interrupt: IRQ%d.\n", irq);
 214                         spurious_irq_mask |= irqmask;
 215                 }
 216                 atomic_inc(&irq_err_count);
 217                 /*
 218                  * Theoretically we do not have to handle this IRQ,
 219                  * but in Linux this does not cause problems and is
 220                  * simpler for us.
 221                  */
 222                 goto handle_real_irq;
 223         }
 224 }
 225
 226 static char irq_trigger[2];
 227 /**
 228  * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 229  */
 230 static void restore_ELCR(char *trigger)
 231 {
 232         outb(trigger[0], 0x4d0);
 233         outb(trigger[1], 0x4d1);
 234 }
 235
 236 static void save_ELCR(char *trigger)
 237 {
 238         /* IRQ 0,1,2,8,13 are marked as reserved */
 239         trigger[0] = inb(0x4d0) & 0xF8;
 240         trigger[1] = inb(0x4d1) & 0xDE;
 241 }
 242
 243 static int i8259A_resume(struct sys_device *dev)
 244 {
 245         init_8259A(i8259A_auto_eoi);
 246         restore_ELCR(irq_trigger);
 247         return 0;
 248 }
 249
 250 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
 251 {
 252         save_ELCR(irq_trigger);
 253         return 0;
 254 }
 255
 256 static int i8259A_shutdown(struct sys_device *dev)
 257 {
 258         /* Put the i8259A into a quiescent state that
 259          * the kernel initialization code can get it
 260          * out of.
 261          */
 262         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 263         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-1 */
 264         return 0;
 265 }
 266
 267 static struct sysdev_class i8259_sysdev_class = {
 268         .name = "i8259",
 269         .suspend = i8259A_suspend,
 270         .resume = i8259A_resume,
 271         .shutdown = i8259A_shutdown,
 272 };
 273
 274 static struct sys_device device_i8259A = {
 275         .id     = 0,
 276         .cls    = &i8259_sysdev_class,
 277 };
 278
 279 static int __init i8259A_init_sysfs(void)
 280 {
 281         int error = sysdev_class_register(&i8259_sysdev_class);
 282         if (!error)
 283                 error = sysdev_register(&device_i8259A);
 284         return error;
 285 }
 286
 287 device_initcall(i8259A_init_sysfs);
 288
 289 static void mask_8259A(void)
 290 {
 291         unsigned long flags;
 292
 293         raw_spin_lock_irqsave(&i8259A_lock, flags);
 294
 295         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 296         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
 297
 298         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 299 }
 300
 301 static void unmask_8259A(void)
 302 {
 303         unsigned long flags;
 304
 305         raw_spin_lock_irqsave(&i8259A_lock, flags);
 306
 307         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
 308         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
 309
 310         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 311 }
 312
 313 static void init_8259A(int auto_eoi)
 314 {
 315         unsigned long flags;
 316
 317         i8259A_auto_eoi = auto_eoi;
 318
 319         raw_spin_lock_irqsave(&i8259A_lock, flags);
 320
 321         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 322         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
 323
 324         /*
 325          * outb_pic - this has to work on a wide range of PC hardware.
 326          */
 327         outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
 328
 329         /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
 330            to 0x20-0x27 on i386 */
 331         outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
 332
 333         /* 8259A-1 (the master) has a slave on IR2 */
 334         outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
 335
 336         if (auto_eoi)   /* master does Auto EOI */
 337                 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
 338         else            /* master expects normal EOI */
 339                 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 340
 341         outb_pic(0x11, PIC_SLAVE_CMD);  /* ICW1: select 8259A-2 init */
 342
 343         /* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
 344         outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
 345         /* 8259A-2 is a slave on master's IR2 */
 346         outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
 347         /* (slave's support for AEOI in flat mode is to be investigated) */
 348         outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
 349
 350         if (auto_eoi)
 351                 /*
 352                  * In AEOI mode we just have to mask the interrupt
 353                  * when acking.
 354                  */
 355                 i8259A_chip.mask_ack = disable_8259A_irq;
 356         else
 357                 i8259A_chip.mask_ack = mask_and_ack_8259A;
 358
 359         udelay(100);            /* wait for 8259A to initialize */
 360
 361         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
 362         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
 363
 364         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 365 }
 366
 367 /*
 368  * make i8259 a driver so that we can select pic functions at run time. the goal
 369  * is to make x86 binary compatible among pc compatible and non-pc compatible
 370  * platforms, such as x86 MID.
 371  */
 372
 373 static void legacy_pic_noop(void) { };
 374 static void legacy_pic_uint_noop(unsigned int unused) { };
 375 static void legacy_pic_int_noop(int unused) { };
 376
 377 static struct irq_chip dummy_pic_chip  = {
 378         .name = "dummy pic",
 379         .mask = legacy_pic_uint_noop,
 380         .unmask = legacy_pic_uint_noop,
 381         .disable = legacy_pic_uint_noop,
 382         .mask_ack = legacy_pic_uint_noop,
 383 };
 384 static int legacy_pic_irq_pending_noop(unsigned int irq)
 385 {
 386         return 0;
 387 }
 388
 389 struct legacy_pic null_legacy_pic = {
 390         .nr_legacy_irqs = 0,
 391         .chip = &dummy_pic_chip,
 392         .mask_all = legacy_pic_noop,
 393         .restore_mask = legacy_pic_noop,
 394         .init = legacy_pic_int_noop,
 395         .irq_pending = legacy_pic_irq_pending_noop,
 396         .make_irq = legacy_pic_uint_noop,
 397 };
 398
 399 struct legacy_pic default_legacy_pic = {
 400         .nr_legacy_irqs = NR_IRQS_LEGACY,
 401         .chip  = &i8259A_chip,
 402         .mask_all  = mask_8259A,
 403         .restore_mask = unmask_8259A,
 404         .init = init_8259A,
 405         .irq_pending = i8259A_irq_pending,
 406         .make_irq = make_8259A_irq,
 407 };
 408
 409 struct legacy_pic *legacy_pic = &default_legacy_pic;