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Merge branch 'cpus4096-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / io_apic.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/desc.h>
50 #include <asm/proto.h>
51 #include <asm/acpi.h>
52 #include <asm/dma.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
55 #include <asm/nmi.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
60 #include <asm/hpet.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
63
64 #include <mach_ipi.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
67
68 #define __apicdebuginit(type) static type __init
69
70 /*
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
73 */
74 int sis_apic_bug = -1;
75
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
78
79 /*
80 * # of IRQ routing registers
81 */
82 int nr_ioapic_registers[MAX_IO_APICS];
83
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
86 int nr_ioapics;
87
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
90
91 /* # of MP IRQ source entries */
92 int mp_irq_entries;
93
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
96 #endif
97
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99
100 int skip_ioapic_setup;
101
102 static int __init parse_noapic(char *str)
103 {
104 /* disable IO-APIC */
105 disable_ioapic_setup();
106 return 0;
107 }
108 early_param("noapic", parse_noapic);
109
110 struct irq_pin_list;
111
112 /*
113 * This is performance-critical, we want to do it O(1)
114 *
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
117 */
118
119 struct irq_pin_list {
120 int apic, pin;
121 struct irq_pin_list *next;
122 };
123
124 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
125 {
126 struct irq_pin_list *pin;
127 int node;
128
129 node = cpu_to_node(cpu);
130
131 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
132 printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node);
133
134 return pin;
135 }
136
137 struct irq_cfg {
138 struct irq_pin_list *irq_2_pin;
139 cpumask_var_t domain;
140 cpumask_var_t old_domain;
141 unsigned move_cleanup_count;
142 u8 vector;
143 u8 move_in_progress : 1;
144 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
145 u8 move_desc_pending : 1;
146 #endif
147 };
148
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx[] = {
152 #else
153 static struct irq_cfg irq_cfgx[NR_IRQS] = {
154 #endif
155 [0] = { .vector = IRQ0_VECTOR, },
156 [1] = { .vector = IRQ1_VECTOR, },
157 [2] = { .vector = IRQ2_VECTOR, },
158 [3] = { .vector = IRQ3_VECTOR, },
159 [4] = { .vector = IRQ4_VECTOR, },
160 [5] = { .vector = IRQ5_VECTOR, },
161 [6] = { .vector = IRQ6_VECTOR, },
162 [7] = { .vector = IRQ7_VECTOR, },
163 [8] = { .vector = IRQ8_VECTOR, },
164 [9] = { .vector = IRQ9_VECTOR, },
165 [10] = { .vector = IRQ10_VECTOR, },
166 [11] = { .vector = IRQ11_VECTOR, },
167 [12] = { .vector = IRQ12_VECTOR, },
168 [13] = { .vector = IRQ13_VECTOR, },
169 [14] = { .vector = IRQ14_VECTOR, },
170 [15] = { .vector = IRQ15_VECTOR, },
171 };
172
173 int __init arch_early_irq_init(void)
174 {
175 struct irq_cfg *cfg;
176 struct irq_desc *desc;
177 int count;
178 int i;
179
180 cfg = irq_cfgx;
181 count = ARRAY_SIZE(irq_cfgx);
182
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
186 alloc_bootmem_cpumask_var(&cfg[i].domain);
187 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
188 if (i < NR_IRQS_LEGACY)
189 cpumask_setall(cfg[i].domain);
190 }
191
192 return 0;
193 }
194
195 #ifdef CONFIG_SPARSE_IRQ
196 static struct irq_cfg *irq_cfg(unsigned int irq)
197 {
198 struct irq_cfg *cfg = NULL;
199 struct irq_desc *desc;
200
201 desc = irq_to_desc(irq);
202 if (desc)
203 cfg = desc->chip_data;
204
205 return cfg;
206 }
207
208 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
209 {
210 struct irq_cfg *cfg;
211 int node;
212
213 node = cpu_to_node(cpu);
214
215 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
216 if (cfg) {
217 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
218 kfree(cfg);
219 cfg = NULL;
220 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
221 GFP_ATOMIC, node)) {
222 free_cpumask_var(cfg->domain);
223 kfree(cfg);
224 cfg = NULL;
225 } else {
226 cpumask_clear(cfg->domain);
227 cpumask_clear(cfg->old_domain);
228 }
229 }
230 printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node);
231
232 return cfg;
233 }
234
235 int arch_init_chip_data(struct irq_desc *desc, int cpu)
236 {
237 struct irq_cfg *cfg;
238
239 cfg = desc->chip_data;
240 if (!cfg) {
241 desc->chip_data = get_one_free_irq_cfg(cpu);
242 if (!desc->chip_data) {
243 printk(KERN_ERR "can not alloc irq_cfg\n");
244 BUG_ON(1);
245 }
246 }
247
248 return 0;
249 }
250
251 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
252
253 static void
254 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
255 {
256 struct irq_pin_list *old_entry, *head, *tail, *entry;
257
258 cfg->irq_2_pin = NULL;
259 old_entry = old_cfg->irq_2_pin;
260 if (!old_entry)
261 return;
262
263 entry = get_one_free_irq_2_pin(cpu);
264 if (!entry)
265 return;
266
267 entry->apic = old_entry->apic;
268 entry->pin = old_entry->pin;
269 head = entry;
270 tail = entry;
271 old_entry = old_entry->next;
272 while (old_entry) {
273 entry = get_one_free_irq_2_pin(cpu);
274 if (!entry) {
275 entry = head;
276 while (entry) {
277 head = entry->next;
278 kfree(entry);
279 entry = head;
280 }
281 /* still use the old one */
282 return;
283 }
284 entry->apic = old_entry->apic;
285 entry->pin = old_entry->pin;
286 tail->next = entry;
287 tail = entry;
288 old_entry = old_entry->next;
289 }
290
291 tail->next = NULL;
292 cfg->irq_2_pin = head;
293 }
294
295 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
296 {
297 struct irq_pin_list *entry, *next;
298
299 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
300 return;
301
302 entry = old_cfg->irq_2_pin;
303
304 while (entry) {
305 next = entry->next;
306 kfree(entry);
307 entry = next;
308 }
309 old_cfg->irq_2_pin = NULL;
310 }
311
312 void arch_init_copy_chip_data(struct irq_desc *old_desc,
313 struct irq_desc *desc, int cpu)
314 {
315 struct irq_cfg *cfg;
316 struct irq_cfg *old_cfg;
317
318 cfg = get_one_free_irq_cfg(cpu);
319
320 if (!cfg)
321 return;
322
323 desc->chip_data = cfg;
324
325 old_cfg = old_desc->chip_data;
326
327 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
328
329 init_copy_irq_2_pin(old_cfg, cfg, cpu);
330 }
331
332 static void free_irq_cfg(struct irq_cfg *old_cfg)
333 {
334 kfree(old_cfg);
335 }
336
337 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
338 {
339 struct irq_cfg *old_cfg, *cfg;
340
341 old_cfg = old_desc->chip_data;
342 cfg = desc->chip_data;
343
344 if (old_cfg == cfg)
345 return;
346
347 if (old_cfg) {
348 free_irq_2_pin(old_cfg, cfg);
349 free_irq_cfg(old_cfg);
350 old_desc->chip_data = NULL;
351 }
352 }
353
354 static void
355 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
356 {
357 struct irq_cfg *cfg = desc->chip_data;
358
359 if (!cfg->move_in_progress) {
360 /* it means that domain is not changed */
361 if (!cpumask_intersects(&desc->affinity, mask))
362 cfg->move_desc_pending = 1;
363 }
364 }
365 #endif
366
367 #else
368 static struct irq_cfg *irq_cfg(unsigned int irq)
369 {
370 return irq < nr_irqs ? irq_cfgx + irq : NULL;
371 }
372
373 #endif
374
375 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
376 static inline void
377 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
378 {
379 }
380 #endif
381
382 struct io_apic {
383 unsigned int index;
384 unsigned int unused[3];
385 unsigned int data;
386 };
387
388 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
389 {
390 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
391 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
392 }
393
394 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
395 {
396 struct io_apic __iomem *io_apic = io_apic_base(apic);
397 writel(reg, &io_apic->index);
398 return readl(&io_apic->data);
399 }
400
401 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
402 {
403 struct io_apic __iomem *io_apic = io_apic_base(apic);
404 writel(reg, &io_apic->index);
405 writel(value, &io_apic->data);
406 }
407
408 /*
409 * Re-write a value: to be used for read-modify-write
410 * cycles where the read already set up the index register.
411 *
412 * Older SiS APIC requires we rewrite the index register
413 */
414 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
415 {
416 struct io_apic __iomem *io_apic = io_apic_base(apic);
417
418 if (sis_apic_bug)
419 writel(reg, &io_apic->index);
420 writel(value, &io_apic->data);
421 }
422
423 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
424 {
425 struct irq_pin_list *entry;
426 unsigned long flags;
427
428 spin_lock_irqsave(&ioapic_lock, flags);
429 entry = cfg->irq_2_pin;
430 for (;;) {
431 unsigned int reg;
432 int pin;
433
434 if (!entry)
435 break;
436 pin = entry->pin;
437 reg = io_apic_read(entry->apic, 0x10 + pin*2);
438 /* Is the remote IRR bit set? */
439 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
440 spin_unlock_irqrestore(&ioapic_lock, flags);
441 return true;
442 }
443 if (!entry->next)
444 break;
445 entry = entry->next;
446 }
447 spin_unlock_irqrestore(&ioapic_lock, flags);
448
449 return false;
450 }
451
452 union entry_union {
453 struct { u32 w1, w2; };
454 struct IO_APIC_route_entry entry;
455 };
456
457 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
458 {
459 union entry_union eu;
460 unsigned long flags;
461 spin_lock_irqsave(&ioapic_lock, flags);
462 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
463 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
464 spin_unlock_irqrestore(&ioapic_lock, flags);
465 return eu.entry;
466 }
467
468 /*
469 * When we write a new IO APIC routing entry, we need to write the high
470 * word first! If the mask bit in the low word is clear, we will enable
471 * the interrupt, and we need to make sure the entry is fully populated
472 * before that happens.
473 */
474 static void
475 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
476 {
477 union entry_union eu;
478 eu.entry = e;
479 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
480 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
481 }
482
483 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
484 {
485 unsigned long flags;
486 spin_lock_irqsave(&ioapic_lock, flags);
487 __ioapic_write_entry(apic, pin, e);
488 spin_unlock_irqrestore(&ioapic_lock, flags);
489 }
490
491 /*
492 * When we mask an IO APIC routing entry, we need to write the low
493 * word first, in order to set the mask bit before we change the
494 * high bits!
495 */
496 static void ioapic_mask_entry(int apic, int pin)
497 {
498 unsigned long flags;
499 union entry_union eu = { .entry.mask = 1 };
500
501 spin_lock_irqsave(&ioapic_lock, flags);
502 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
503 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
504 spin_unlock_irqrestore(&ioapic_lock, flags);
505 }
506
507 #ifdef CONFIG_SMP
508 static void send_cleanup_vector(struct irq_cfg *cfg)
509 {
510 cpumask_var_t cleanup_mask;
511
512 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
513 unsigned int i;
514 cfg->move_cleanup_count = 0;
515 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
516 cfg->move_cleanup_count++;
517 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
518 send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
519 } else {
520 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
521 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
522 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
523 free_cpumask_var(cleanup_mask);
524 }
525 cfg->move_in_progress = 0;
526 }
527
528 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
529 {
530 int apic, pin;
531 struct irq_pin_list *entry;
532 u8 vector = cfg->vector;
533
534 entry = cfg->irq_2_pin;
535 for (;;) {
536 unsigned int reg;
537
538 if (!entry)
539 break;
540
541 apic = entry->apic;
542 pin = entry->pin;
543 #ifdef CONFIG_INTR_REMAP
544 /*
545 * With interrupt-remapping, destination information comes
546 * from interrupt-remapping table entry.
547 */
548 if (!irq_remapped(irq))
549 io_apic_write(apic, 0x11 + pin*2, dest);
550 #else
551 io_apic_write(apic, 0x11 + pin*2, dest);
552 #endif
553 reg = io_apic_read(apic, 0x10 + pin*2);
554 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
555 reg |= vector;
556 io_apic_modify(apic, 0x10 + pin*2, reg);
557 if (!entry->next)
558 break;
559 entry = entry->next;
560 }
561 }
562
563 static int
564 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
565
566 /*
567 * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid
568 * of that, or returns BAD_APICID and leaves desc->affinity untouched.
569 */
570 static unsigned int
571 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
572 {
573 struct irq_cfg *cfg;
574 unsigned int irq;
575
576 if (!cpumask_intersects(mask, cpu_online_mask))
577 return BAD_APICID;
578
579 irq = desc->irq;
580 cfg = desc->chip_data;
581 if (assign_irq_vector(irq, cfg, mask))
582 return BAD_APICID;
583
584 cpumask_and(&desc->affinity, cfg->domain, mask);
585 set_extra_move_desc(desc, mask);
586 return cpu_mask_to_apicid_and(&desc->affinity, cpu_online_mask);
587 }
588
589 static void
590 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
591 {
592 struct irq_cfg *cfg;
593 unsigned long flags;
594 unsigned int dest;
595 unsigned int irq;
596
597 irq = desc->irq;
598 cfg = desc->chip_data;
599
600 spin_lock_irqsave(&ioapic_lock, flags);
601 dest = set_desc_affinity(desc, mask);
602 if (dest != BAD_APICID) {
603 /* Only the high 8 bits are valid. */
604 dest = SET_APIC_LOGICAL_ID(dest);
605 __target_IO_APIC_irq(irq, dest, cfg);
606 }
607 spin_unlock_irqrestore(&ioapic_lock, flags);
608 }
609
610 static void
611 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
612 {
613 struct irq_desc *desc;
614
615 desc = irq_to_desc(irq);
616
617 set_ioapic_affinity_irq_desc(desc, mask);
618 }
619 #endif /* CONFIG_SMP */
620
621 /*
622 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
623 * shared ISA-space IRQs, so we have to support them. We are super
624 * fast in the common case, and fast for shared ISA-space IRQs.
625 */
626 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
627 {
628 struct irq_pin_list *entry;
629
630 entry = cfg->irq_2_pin;
631 if (!entry) {
632 entry = get_one_free_irq_2_pin(cpu);
633 if (!entry) {
634 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
635 apic, pin);
636 return;
637 }
638 cfg->irq_2_pin = entry;
639 entry->apic = apic;
640 entry->pin = pin;
641 return;
642 }
643
644 while (entry->next) {
645 /* not again, please */
646 if (entry->apic == apic && entry->pin == pin)
647 return;
648
649 entry = entry->next;
650 }
651
652 entry->next = get_one_free_irq_2_pin(cpu);
653 entry = entry->next;
654 entry->apic = apic;
655 entry->pin = pin;
656 }
657
658 /*
659 * Reroute an IRQ to a different pin.
660 */
661 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
662 int oldapic, int oldpin,
663 int newapic, int newpin)
664 {
665 struct irq_pin_list *entry = cfg->irq_2_pin;
666 int replaced = 0;
667
668 while (entry) {
669 if (entry->apic == oldapic && entry->pin == oldpin) {
670 entry->apic = newapic;
671 entry->pin = newpin;
672 replaced = 1;
673 /* every one is different, right? */
674 break;
675 }
676 entry = entry->next;
677 }
678
679 /* why? call replace before add? */
680 if (!replaced)
681 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
682 }
683
684 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
685 int mask_and, int mask_or,
686 void (*final)(struct irq_pin_list *entry))
687 {
688 int pin;
689 struct irq_pin_list *entry;
690
691 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
692 unsigned int reg;
693 pin = entry->pin;
694 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
695 reg &= mask_and;
696 reg |= mask_or;
697 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
698 if (final)
699 final(entry);
700 }
701 }
702
703 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
704 {
705 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
706 }
707
708 #ifdef CONFIG_X86_64
709 static void io_apic_sync(struct irq_pin_list *entry)
710 {
711 /*
712 * Synchronize the IO-APIC and the CPU by doing
713 * a dummy read from the IO-APIC
714 */
715 struct io_apic __iomem *io_apic;
716 io_apic = io_apic_base(entry->apic);
717 readl(&io_apic->data);
718 }
719
720 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
721 {
722 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
723 }
724 #else /* CONFIG_X86_32 */
725 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
726 {
727 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
728 }
729
730 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
731 {
732 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
733 IO_APIC_REDIR_MASKED, NULL);
734 }
735
736 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
737 {
738 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
739 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
740 }
741 #endif /* CONFIG_X86_32 */
742
743 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
744 {
745 struct irq_cfg *cfg = desc->chip_data;
746 unsigned long flags;
747
748 BUG_ON(!cfg);
749
750 spin_lock_irqsave(&ioapic_lock, flags);
751 __mask_IO_APIC_irq(cfg);
752 spin_unlock_irqrestore(&ioapic_lock, flags);
753 }
754
755 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
756 {
757 struct irq_cfg *cfg = desc->chip_data;
758 unsigned long flags;
759
760 spin_lock_irqsave(&ioapic_lock, flags);
761 __unmask_IO_APIC_irq(cfg);
762 spin_unlock_irqrestore(&ioapic_lock, flags);
763 }
764
765 static void mask_IO_APIC_irq(unsigned int irq)
766 {
767 struct irq_desc *desc = irq_to_desc(irq);
768
769 mask_IO_APIC_irq_desc(desc);
770 }
771 static void unmask_IO_APIC_irq(unsigned int irq)
772 {
773 struct irq_desc *desc = irq_to_desc(irq);
774
775 unmask_IO_APIC_irq_desc(desc);
776 }
777
778 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
779 {
780 struct IO_APIC_route_entry entry;
781
782 /* Check delivery_mode to be sure we're not clearing an SMI pin */
783 entry = ioapic_read_entry(apic, pin);
784 if (entry.delivery_mode == dest_SMI)
785 return;
786 /*
787 * Disable it in the IO-APIC irq-routing table:
788 */
789 ioapic_mask_entry(apic, pin);
790 }
791
792 static void clear_IO_APIC (void)
793 {
794 int apic, pin;
795
796 for (apic = 0; apic < nr_ioapics; apic++)
797 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
798 clear_IO_APIC_pin(apic, pin);
799 }
800
801 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
802 void send_IPI_self(int vector)
803 {
804 unsigned int cfg;
805
806 /*
807 * Wait for idle.
808 */
809 apic_wait_icr_idle();
810 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
811 /*
812 * Send the IPI. The write to APIC_ICR fires this off.
813 */
814 apic_write(APIC_ICR, cfg);
815 }
816 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
817
818 #ifdef CONFIG_X86_32
819 /*
820 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
821 * specific CPU-side IRQs.
822 */
823
824 #define MAX_PIRQS 8
825 static int pirq_entries [MAX_PIRQS];
826 static int pirqs_enabled;
827
828 static int __init ioapic_pirq_setup(char *str)
829 {
830 int i, max;
831 int ints[MAX_PIRQS+1];
832
833 get_options(str, ARRAY_SIZE(ints), ints);
834
835 for (i = 0; i < MAX_PIRQS; i++)
836 pirq_entries[i] = -1;
837
838 pirqs_enabled = 1;
839 apic_printk(APIC_VERBOSE, KERN_INFO
840 "PIRQ redirection, working around broken MP-BIOS.\n");
841 max = MAX_PIRQS;
842 if (ints[0] < MAX_PIRQS)
843 max = ints[0];
844
845 for (i = 0; i < max; i++) {
846 apic_printk(APIC_VERBOSE, KERN_DEBUG
847 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
848 /*
849 * PIRQs are mapped upside down, usually.
850 */
851 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
852 }
853 return 1;
854 }
855
856 __setup("pirq=", ioapic_pirq_setup);
857 #endif /* CONFIG_X86_32 */
858
859 #ifdef CONFIG_INTR_REMAP
860 /* I/O APIC RTE contents at the OS boot up */
861 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
862
863 /*
864 * Saves and masks all the unmasked IO-APIC RTE's
865 */
866 int save_mask_IO_APIC_setup(void)
867 {
868 union IO_APIC_reg_01 reg_01;
869 unsigned long flags;
870 int apic, pin;
871
872 /*
873 * The number of IO-APIC IRQ registers (== #pins):
874 */
875 for (apic = 0; apic < nr_ioapics; apic++) {
876 spin_lock_irqsave(&ioapic_lock, flags);
877 reg_01.raw = io_apic_read(apic, 1);
878 spin_unlock_irqrestore(&ioapic_lock, flags);
879 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
880 }
881
882 for (apic = 0; apic < nr_ioapics; apic++) {
883 early_ioapic_entries[apic] =
884 kzalloc(sizeof(struct IO_APIC_route_entry) *
885 nr_ioapic_registers[apic], GFP_KERNEL);
886 if (!early_ioapic_entries[apic])
887 goto nomem;
888 }
889
890 for (apic = 0; apic < nr_ioapics; apic++)
891 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
892 struct IO_APIC_route_entry entry;
893
894 entry = early_ioapic_entries[apic][pin] =
895 ioapic_read_entry(apic, pin);
896 if (!entry.mask) {
897 entry.mask = 1;
898 ioapic_write_entry(apic, pin, entry);
899 }
900 }
901
902 return 0;
903
904 nomem:
905 while (apic >= 0)
906 kfree(early_ioapic_entries[apic--]);
907 memset(early_ioapic_entries, 0,
908 ARRAY_SIZE(early_ioapic_entries));
909
910 return -ENOMEM;
911 }
912
913 void restore_IO_APIC_setup(void)
914 {
915 int apic, pin;
916
917 for (apic = 0; apic < nr_ioapics; apic++) {
918 if (!early_ioapic_entries[apic])
919 break;
920 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
921 ioapic_write_entry(apic, pin,
922 early_ioapic_entries[apic][pin]);
923 kfree(early_ioapic_entries[apic]);
924 early_ioapic_entries[apic] = NULL;
925 }
926 }
927
928 void reinit_intr_remapped_IO_APIC(int intr_remapping)
929 {
930 /*
931 * for now plain restore of previous settings.
932 * TBD: In the case of OS enabling interrupt-remapping,
933 * IO-APIC RTE's need to be setup to point to interrupt-remapping
934 * table entries. for now, do a plain restore, and wait for
935 * the setup_IO_APIC_irqs() to do proper initialization.
936 */
937 restore_IO_APIC_setup();
938 }
939 #endif
940
941 /*
942 * Find the IRQ entry number of a certain pin.
943 */
944 static int find_irq_entry(int apic, int pin, int type)
945 {
946 int i;
947
948 for (i = 0; i < mp_irq_entries; i++)
949 if (mp_irqs[i].mp_irqtype == type &&
950 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
951 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
952 mp_irqs[i].mp_dstirq == pin)
953 return i;
954
955 return -1;
956 }
957
958 /*
959 * Find the pin to which IRQ[irq] (ISA) is connected
960 */
961 static int __init find_isa_irq_pin(int irq, int type)
962 {
963 int i;
964
965 for (i = 0; i < mp_irq_entries; i++) {
966 int lbus = mp_irqs[i].mp_srcbus;
967
968 if (test_bit(lbus, mp_bus_not_pci) &&
969 (mp_irqs[i].mp_irqtype == type) &&
970 (mp_irqs[i].mp_srcbusirq == irq))
971
972 return mp_irqs[i].mp_dstirq;
973 }
974 return -1;
975 }
976
977 static int __init find_isa_irq_apic(int irq, int type)
978 {
979 int i;
980
981 for (i = 0; i < mp_irq_entries; i++) {
982 int lbus = mp_irqs[i].mp_srcbus;
983
984 if (test_bit(lbus, mp_bus_not_pci) &&
985 (mp_irqs[i].mp_irqtype == type) &&
986 (mp_irqs[i].mp_srcbusirq == irq))
987 break;
988 }
989 if (i < mp_irq_entries) {
990 int apic;
991 for(apic = 0; apic < nr_ioapics; apic++) {
992 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
993 return apic;
994 }
995 }
996
997 return -1;
998 }
999
1000 /*
1001 * Find a specific PCI IRQ entry.
1002 * Not an __init, possibly needed by modules
1003 */
1004 static int pin_2_irq(int idx, int apic, int pin);
1005
1006 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1007 {
1008 int apic, i, best_guess = -1;
1009
1010 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1011 bus, slot, pin);
1012 if (test_bit(bus, mp_bus_not_pci)) {
1013 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1014 return -1;
1015 }
1016 for (i = 0; i < mp_irq_entries; i++) {
1017 int lbus = mp_irqs[i].mp_srcbus;
1018
1019 for (apic = 0; apic < nr_ioapics; apic++)
1020 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
1021 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
1022 break;
1023
1024 if (!test_bit(lbus, mp_bus_not_pci) &&
1025 !mp_irqs[i].mp_irqtype &&
1026 (bus == lbus) &&
1027 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
1028 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
1029
1030 if (!(apic || IO_APIC_IRQ(irq)))
1031 continue;
1032
1033 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
1034 return irq;
1035 /*
1036 * Use the first all-but-pin matching entry as a
1037 * best-guess fuzzy result for broken mptables.
1038 */
1039 if (best_guess < 0)
1040 best_guess = irq;
1041 }
1042 }
1043 return best_guess;
1044 }
1045
1046 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1047
1048 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1049 /*
1050 * EISA Edge/Level control register, ELCR
1051 */
1052 static int EISA_ELCR(unsigned int irq)
1053 {
1054 if (irq < NR_IRQS_LEGACY) {
1055 unsigned int port = 0x4d0 + (irq >> 3);
1056 return (inb(port) >> (irq & 7)) & 1;
1057 }
1058 apic_printk(APIC_VERBOSE, KERN_INFO
1059 "Broken MPtable reports ISA irq %d\n", irq);
1060 return 0;
1061 }
1062
1063 #endif
1064
1065 /* ISA interrupts are always polarity zero edge triggered,
1066 * when listed as conforming in the MP table. */
1067
1068 #define default_ISA_trigger(idx) (0)
1069 #define default_ISA_polarity(idx) (0)
1070
1071 /* EISA interrupts are always polarity zero and can be edge or level
1072 * trigger depending on the ELCR value. If an interrupt is listed as
1073 * EISA conforming in the MP table, that means its trigger type must
1074 * be read in from the ELCR */
1075
1076 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1077 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1078
1079 /* PCI interrupts are always polarity one level triggered,
1080 * when listed as conforming in the MP table. */
1081
1082 #define default_PCI_trigger(idx) (1)
1083 #define default_PCI_polarity(idx) (1)
1084
1085 /* MCA interrupts are always polarity zero level triggered,
1086 * when listed as conforming in the MP table. */
1087
1088 #define default_MCA_trigger(idx) (1)
1089 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1090
1091 static int MPBIOS_polarity(int idx)
1092 {
1093 int bus = mp_irqs[idx].mp_srcbus;
1094 int polarity;
1095
1096 /*
1097 * Determine IRQ line polarity (high active or low active):
1098 */
1099 switch (mp_irqs[idx].mp_irqflag & 3)
1100 {
1101 case 0: /* conforms, ie. bus-type dependent polarity */
1102 if (test_bit(bus, mp_bus_not_pci))
1103 polarity = default_ISA_polarity(idx);
1104 else
1105 polarity = default_PCI_polarity(idx);
1106 break;
1107 case 1: /* high active */
1108 {
1109 polarity = 0;
1110 break;
1111 }
1112 case 2: /* reserved */
1113 {
1114 printk(KERN_WARNING "broken BIOS!!\n");
1115 polarity = 1;
1116 break;
1117 }
1118 case 3: /* low active */
1119 {
1120 polarity = 1;
1121 break;
1122 }
1123 default: /* invalid */
1124 {
1125 printk(KERN_WARNING "broken BIOS!!\n");
1126 polarity = 1;
1127 break;
1128 }
1129 }
1130 return polarity;
1131 }
1132
1133 static int MPBIOS_trigger(int idx)
1134 {
1135 int bus = mp_irqs[idx].mp_srcbus;
1136 int trigger;
1137
1138 /*
1139 * Determine IRQ trigger mode (edge or level sensitive):
1140 */
1141 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1142 {
1143 case 0: /* conforms, ie. bus-type dependent */
1144 if (test_bit(bus, mp_bus_not_pci))
1145 trigger = default_ISA_trigger(idx);
1146 else
1147 trigger = default_PCI_trigger(idx);
1148 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1149 switch (mp_bus_id_to_type[bus]) {
1150 case MP_BUS_ISA: /* ISA pin */
1151 {
1152 /* set before the switch */
1153 break;
1154 }
1155 case MP_BUS_EISA: /* EISA pin */
1156 {
1157 trigger = default_EISA_trigger(idx);
1158 break;
1159 }
1160 case MP_BUS_PCI: /* PCI pin */
1161 {
1162 /* set before the switch */
1163 break;
1164 }
1165 case MP_BUS_MCA: /* MCA pin */
1166 {
1167 trigger = default_MCA_trigger(idx);
1168 break;
1169 }
1170 default:
1171 {
1172 printk(KERN_WARNING "broken BIOS!!\n");
1173 trigger = 1;
1174 break;
1175 }
1176 }
1177 #endif
1178 break;
1179 case 1: /* edge */
1180 {
1181 trigger = 0;
1182 break;
1183 }
1184 case 2: /* reserved */
1185 {
1186 printk(KERN_WARNING "broken BIOS!!\n");
1187 trigger = 1;
1188 break;
1189 }
1190 case 3: /* level */
1191 {
1192 trigger = 1;
1193 break;
1194 }
1195 default: /* invalid */
1196 {
1197 printk(KERN_WARNING "broken BIOS!!\n");
1198 trigger = 0;
1199 break;
1200 }
1201 }
1202 return trigger;
1203 }
1204
1205 static inline int irq_polarity(int idx)
1206 {
1207 return MPBIOS_polarity(idx);
1208 }
1209
1210 static inline int irq_trigger(int idx)
1211 {
1212 return MPBIOS_trigger(idx);
1213 }
1214
1215 int (*ioapic_renumber_irq)(int ioapic, int irq);
1216 static int pin_2_irq(int idx, int apic, int pin)
1217 {
1218 int irq, i;
1219 int bus = mp_irqs[idx].mp_srcbus;
1220
1221 /*
1222 * Debugging check, we are in big trouble if this message pops up!
1223 */
1224 if (mp_irqs[idx].mp_dstirq != pin)
1225 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1226
1227 if (test_bit(bus, mp_bus_not_pci)) {
1228 irq = mp_irqs[idx].mp_srcbusirq;
1229 } else {
1230 /*
1231 * PCI IRQs are mapped in order
1232 */
1233 i = irq = 0;
1234 while (i < apic)
1235 irq += nr_ioapic_registers[i++];
1236 irq += pin;
1237 /*
1238 * For MPS mode, so far only needed by ES7000 platform
1239 */
1240 if (ioapic_renumber_irq)
1241 irq = ioapic_renumber_irq(apic, irq);
1242 }
1243
1244 #ifdef CONFIG_X86_32
1245 /*
1246 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1247 */
1248 if ((pin >= 16) && (pin <= 23)) {
1249 if (pirq_entries[pin-16] != -1) {
1250 if (!pirq_entries[pin-16]) {
1251 apic_printk(APIC_VERBOSE, KERN_DEBUG
1252 "disabling PIRQ%d\n", pin-16);
1253 } else {
1254 irq = pirq_entries[pin-16];
1255 apic_printk(APIC_VERBOSE, KERN_DEBUG
1256 "using PIRQ%d -> IRQ %d\n",
1257 pin-16, irq);
1258 }
1259 }
1260 }
1261 #endif
1262
1263 return irq;
1264 }
1265
1266 void lock_vector_lock(void)
1267 {
1268 /* Used to the online set of cpus does not change
1269 * during assign_irq_vector.
1270 */
1271 spin_lock(&vector_lock);
1272 }
1273
1274 void unlock_vector_lock(void)
1275 {
1276 spin_unlock(&vector_lock);
1277 }
1278
1279 static int
1280 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1281 {
1282 /*
1283 * NOTE! The local APIC isn't very good at handling
1284 * multiple interrupts at the same interrupt level.
1285 * As the interrupt level is determined by taking the
1286 * vector number and shifting that right by 4, we
1287 * want to spread these out a bit so that they don't
1288 * all fall in the same interrupt level.
1289 *
1290 * Also, we've got to be careful not to trash gate
1291 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1292 */
1293 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1294 unsigned int old_vector;
1295 int cpu, err;
1296 cpumask_var_t tmp_mask;
1297
1298 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1299 return -EBUSY;
1300
1301 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1302 return -ENOMEM;
1303
1304 old_vector = cfg->vector;
1305 if (old_vector) {
1306 cpumask_and(tmp_mask, mask, cpu_online_mask);
1307 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1308 if (!cpumask_empty(tmp_mask)) {
1309 free_cpumask_var(tmp_mask);
1310 return 0;
1311 }
1312 }
1313
1314 /* Only try and allocate irqs on cpus that are present */
1315 err = -ENOSPC;
1316 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1317 int new_cpu;
1318 int vector, offset;
1319
1320 vector_allocation_domain(cpu, tmp_mask);
1321
1322 vector = current_vector;
1323 offset = current_offset;
1324 next:
1325 vector += 8;
1326 if (vector >= first_system_vector) {
1327 /* If out of vectors on large boxen, must share them. */
1328 offset = (offset + 1) % 8;
1329 vector = FIRST_DEVICE_VECTOR + offset;
1330 }
1331 if (unlikely(current_vector == vector))
1332 continue;
1333
1334 if (test_bit(vector, used_vectors))
1335 goto next;
1336
1337 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1338 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1339 goto next;
1340 /* Found one! */
1341 current_vector = vector;
1342 current_offset = offset;
1343 if (old_vector) {
1344 cfg->move_in_progress = 1;
1345 cpumask_copy(cfg->old_domain, cfg->domain);
1346 }
1347 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1348 per_cpu(vector_irq, new_cpu)[vector] = irq;
1349 cfg->vector = vector;
1350 cpumask_copy(cfg->domain, tmp_mask);
1351 err = 0;
1352 break;
1353 }
1354 free_cpumask_var(tmp_mask);
1355 return err;
1356 }
1357
1358 static int
1359 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1360 {
1361 int err;
1362 unsigned long flags;
1363
1364 spin_lock_irqsave(&vector_lock, flags);
1365 err = __assign_irq_vector(irq, cfg, mask);
1366 spin_unlock_irqrestore(&vector_lock, flags);
1367 return err;
1368 }
1369
1370 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1371 {
1372 int cpu, vector;
1373
1374 BUG_ON(!cfg->vector);
1375
1376 vector = cfg->vector;
1377 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1378 per_cpu(vector_irq, cpu)[vector] = -1;
1379
1380 cfg->vector = 0;
1381 cpumask_clear(cfg->domain);
1382
1383 if (likely(!cfg->move_in_progress))
1384 return;
1385 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1386 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1387 vector++) {
1388 if (per_cpu(vector_irq, cpu)[vector] != irq)
1389 continue;
1390 per_cpu(vector_irq, cpu)[vector] = -1;
1391 break;
1392 }
1393 }
1394 cfg->move_in_progress = 0;
1395 }
1396
1397 void __setup_vector_irq(int cpu)
1398 {
1399 /* Initialize vector_irq on a new cpu */
1400 /* This function must be called with vector_lock held */
1401 int irq, vector;
1402 struct irq_cfg *cfg;
1403 struct irq_desc *desc;
1404
1405 /* Mark the inuse vectors */
1406 for_each_irq_desc(irq, desc) {
1407 cfg = desc->chip_data;
1408 if (!cpumask_test_cpu(cpu, cfg->domain))
1409 continue;
1410 vector = cfg->vector;
1411 per_cpu(vector_irq, cpu)[vector] = irq;
1412 }
1413 /* Mark the free vectors */
1414 for (vector = 0; vector < NR_VECTORS; ++vector) {
1415 irq = per_cpu(vector_irq, cpu)[vector];
1416 if (irq < 0)
1417 continue;
1418
1419 cfg = irq_cfg(irq);
1420 if (!cpumask_test_cpu(cpu, cfg->domain))
1421 per_cpu(vector_irq, cpu)[vector] = -1;
1422 }
1423 }
1424
1425 static struct irq_chip ioapic_chip;
1426 #ifdef CONFIG_INTR_REMAP
1427 static struct irq_chip ir_ioapic_chip;
1428 #endif
1429
1430 #define IOAPIC_AUTO -1
1431 #define IOAPIC_EDGE 0
1432 #define IOAPIC_LEVEL 1
1433
1434 #ifdef CONFIG_X86_32
1435 static inline int IO_APIC_irq_trigger(int irq)
1436 {
1437 int apic, idx, pin;
1438
1439 for (apic = 0; apic < nr_ioapics; apic++) {
1440 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1441 idx = find_irq_entry(apic, pin, mp_INT);
1442 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1443 return irq_trigger(idx);
1444 }
1445 }
1446 /*
1447 * nonexistent IRQs are edge default
1448 */
1449 return 0;
1450 }
1451 #else
1452 static inline int IO_APIC_irq_trigger(int irq)
1453 {
1454 return 1;
1455 }
1456 #endif
1457
1458 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1459 {
1460
1461 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1462 trigger == IOAPIC_LEVEL)
1463 desc->status |= IRQ_LEVEL;
1464 else
1465 desc->status &= ~IRQ_LEVEL;
1466
1467 #ifdef CONFIG_INTR_REMAP
1468 if (irq_remapped(irq)) {
1469 desc->status |= IRQ_MOVE_PCNTXT;
1470 if (trigger)
1471 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1472 handle_fasteoi_irq,
1473 "fasteoi");
1474 else
1475 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1476 handle_edge_irq, "edge");
1477 return;
1478 }
1479 #endif
1480 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1481 trigger == IOAPIC_LEVEL)
1482 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1483 handle_fasteoi_irq,
1484 "fasteoi");
1485 else
1486 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1487 handle_edge_irq, "edge");
1488 }
1489
1490 static int setup_ioapic_entry(int apic, int irq,
1491 struct IO_APIC_route_entry *entry,
1492 unsigned int destination, int trigger,
1493 int polarity, int vector)
1494 {
1495 /*
1496 * add it to the IO-APIC irq-routing table:
1497 */
1498 memset(entry,0,sizeof(*entry));
1499
1500 #ifdef CONFIG_INTR_REMAP
1501 if (intr_remapping_enabled) {
1502 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1503 struct irte irte;
1504 struct IR_IO_APIC_route_entry *ir_entry =
1505 (struct IR_IO_APIC_route_entry *) entry;
1506 int index;
1507
1508 if (!iommu)
1509 panic("No mapping iommu for ioapic %d\n", apic);
1510
1511 index = alloc_irte(iommu, irq, 1);
1512 if (index < 0)
1513 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1514
1515 memset(&irte, 0, sizeof(irte));
1516
1517 irte.present = 1;
1518 irte.dst_mode = INT_DEST_MODE;
1519 irte.trigger_mode = trigger;
1520 irte.dlvry_mode = INT_DELIVERY_MODE;
1521 irte.vector = vector;
1522 irte.dest_id = IRTE_DEST(destination);
1523
1524 modify_irte(irq, &irte);
1525
1526 ir_entry->index2 = (index >> 15) & 0x1;
1527 ir_entry->zero = 0;
1528 ir_entry->format = 1;
1529 ir_entry->index = (index & 0x7fff);
1530 } else
1531 #endif
1532 {
1533 entry->delivery_mode = INT_DELIVERY_MODE;
1534 entry->dest_mode = INT_DEST_MODE;
1535 entry->dest = destination;
1536 }
1537
1538 entry->mask = 0; /* enable IRQ */
1539 entry->trigger = trigger;
1540 entry->polarity = polarity;
1541 entry->vector = vector;
1542
1543 /* Mask level triggered irqs.
1544 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1545 */
1546 if (trigger)
1547 entry->mask = 1;
1548 return 0;
1549 }
1550
1551 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc,
1552 int trigger, int polarity)
1553 {
1554 struct irq_cfg *cfg;
1555 struct IO_APIC_route_entry entry;
1556 unsigned int dest;
1557
1558 if (!IO_APIC_IRQ(irq))
1559 return;
1560
1561 cfg = desc->chip_data;
1562
1563 if (assign_irq_vector(irq, cfg, TARGET_CPUS))
1564 return;
1565
1566 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
1567
1568 apic_printk(APIC_VERBOSE,KERN_DEBUG
1569 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1570 "IRQ %d Mode:%i Active:%i)\n",
1571 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1572 irq, trigger, polarity);
1573
1574
1575 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1576 dest, trigger, polarity, cfg->vector)) {
1577 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1578 mp_ioapics[apic].mp_apicid, pin);
1579 __clear_irq_vector(irq, cfg);
1580 return;
1581 }
1582
1583 ioapic_register_intr(irq, desc, trigger);
1584 if (irq < NR_IRQS_LEGACY)
1585 disable_8259A_irq(irq);
1586
1587 ioapic_write_entry(apic, pin, entry);
1588 }
1589
1590 static void __init setup_IO_APIC_irqs(void)
1591 {
1592 int apic, pin, idx, irq;
1593 int notcon = 0;
1594 struct irq_desc *desc;
1595 struct irq_cfg *cfg;
1596 int cpu = boot_cpu_id;
1597
1598 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1599
1600 for (apic = 0; apic < nr_ioapics; apic++) {
1601 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1602
1603 idx = find_irq_entry(apic, pin, mp_INT);
1604 if (idx == -1) {
1605 if (!notcon) {
1606 notcon = 1;
1607 apic_printk(APIC_VERBOSE,
1608 KERN_DEBUG " %d-%d",
1609 mp_ioapics[apic].mp_apicid,
1610 pin);
1611 } else
1612 apic_printk(APIC_VERBOSE, " %d-%d",
1613 mp_ioapics[apic].mp_apicid,
1614 pin);
1615 continue;
1616 }
1617 if (notcon) {
1618 apic_printk(APIC_VERBOSE,
1619 " (apicid-pin) not connected\n");
1620 notcon = 0;
1621 }
1622
1623 irq = pin_2_irq(idx, apic, pin);
1624 #ifdef CONFIG_X86_32
1625 if (multi_timer_check(apic, irq))
1626 continue;
1627 #endif
1628 desc = irq_to_desc_alloc_cpu(irq, cpu);
1629 if (!desc) {
1630 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1631 continue;
1632 }
1633 cfg = desc->chip_data;
1634 add_pin_to_irq_cpu(cfg, cpu, apic, pin);
1635
1636 setup_IO_APIC_irq(apic, pin, irq, desc,
1637 irq_trigger(idx), irq_polarity(idx));
1638 }
1639 }
1640
1641 if (notcon)
1642 apic_printk(APIC_VERBOSE,
1643 " (apicid-pin) not connected\n");
1644 }
1645
1646 /*
1647 * Set up the timer pin, possibly with the 8259A-master behind.
1648 */
1649 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1650 int vector)
1651 {
1652 struct IO_APIC_route_entry entry;
1653
1654 #ifdef CONFIG_INTR_REMAP
1655 if (intr_remapping_enabled)
1656 return;
1657 #endif
1658
1659 memset(&entry, 0, sizeof(entry));
1660
1661 /*
1662 * We use logical delivery to get the timer IRQ
1663 * to the first CPU.
1664 */
1665 entry.dest_mode = INT_DEST_MODE;
1666 entry.mask = 1; /* mask IRQ now */
1667 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1668 entry.delivery_mode = INT_DELIVERY_MODE;
1669 entry.polarity = 0;
1670 entry.trigger = 0;
1671 entry.vector = vector;
1672
1673 /*
1674 * The timer IRQ doesn't have to know that behind the
1675 * scene we may have a 8259A-master in AEOI mode ...
1676 */
1677 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1678
1679 /*
1680 * Add it to the IO-APIC irq-routing table:
1681 */
1682 ioapic_write_entry(apic, pin, entry);
1683 }
1684
1685
1686 __apicdebuginit(void) print_IO_APIC(void)
1687 {
1688 int apic, i;
1689 union IO_APIC_reg_00 reg_00;
1690 union IO_APIC_reg_01 reg_01;
1691 union IO_APIC_reg_02 reg_02;
1692 union IO_APIC_reg_03 reg_03;
1693 unsigned long flags;
1694 struct irq_cfg *cfg;
1695 struct irq_desc *desc;
1696 unsigned int irq;
1697
1698 if (apic_verbosity == APIC_QUIET)
1699 return;
1700
1701 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1702 for (i = 0; i < nr_ioapics; i++)
1703 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1704 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1705
1706 /*
1707 * We are a bit conservative about what we expect. We have to
1708 * know about every hardware change ASAP.
1709 */
1710 printk(KERN_INFO "testing the IO APIC.......................\n");
1711
1712 for (apic = 0; apic < nr_ioapics; apic++) {
1713
1714 spin_lock_irqsave(&ioapic_lock, flags);
1715 reg_00.raw = io_apic_read(apic, 0);
1716 reg_01.raw = io_apic_read(apic, 1);
1717 if (reg_01.bits.version >= 0x10)
1718 reg_02.raw = io_apic_read(apic, 2);
1719 if (reg_01.bits.version >= 0x20)
1720 reg_03.raw = io_apic_read(apic, 3);
1721 spin_unlock_irqrestore(&ioapic_lock, flags);
1722
1723 printk("\n");
1724 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1725 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1726 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1727 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1728 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1729
1730 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1731 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1732
1733 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1734 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1735
1736 /*
1737 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1738 * but the value of reg_02 is read as the previous read register
1739 * value, so ignore it if reg_02 == reg_01.
1740 */
1741 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1742 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1743 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1744 }
1745
1746 /*
1747 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1748 * or reg_03, but the value of reg_0[23] is read as the previous read
1749 * register value, so ignore it if reg_03 == reg_0[12].
1750 */
1751 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1752 reg_03.raw != reg_01.raw) {
1753 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1754 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1755 }
1756
1757 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1758
1759 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1760 " Stat Dmod Deli Vect: \n");
1761
1762 for (i = 0; i <= reg_01.bits.entries; i++) {
1763 struct IO_APIC_route_entry entry;
1764
1765 entry = ioapic_read_entry(apic, i);
1766
1767 printk(KERN_DEBUG " %02x %03X ",
1768 i,
1769 entry.dest
1770 );
1771
1772 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1773 entry.mask,
1774 entry.trigger,
1775 entry.irr,
1776 entry.polarity,
1777 entry.delivery_status,
1778 entry.dest_mode,
1779 entry.delivery_mode,
1780 entry.vector
1781 );
1782 }
1783 }
1784 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1785 for_each_irq_desc(irq, desc) {
1786 struct irq_pin_list *entry;
1787
1788 cfg = desc->chip_data;
1789 entry = cfg->irq_2_pin;
1790 if (!entry)
1791 continue;
1792 printk(KERN_DEBUG "IRQ%d ", irq);
1793 for (;;) {
1794 printk("-> %d:%d", entry->apic, entry->pin);
1795 if (!entry->next)
1796 break;
1797 entry = entry->next;
1798 }
1799 printk("\n");
1800 }
1801
1802 printk(KERN_INFO ".................................... done.\n");
1803
1804 return;
1805 }
1806
1807 __apicdebuginit(void) print_APIC_bitfield(int base)
1808 {
1809 unsigned int v;
1810 int i, j;
1811
1812 if (apic_verbosity == APIC_QUIET)
1813 return;
1814
1815 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1816 for (i = 0; i < 8; i++) {
1817 v = apic_read(base + i*0x10);
1818 for (j = 0; j < 32; j++) {
1819 if (v & (1<<j))
1820 printk("1");
1821 else
1822 printk("0");
1823 }
1824 printk("\n");
1825 }
1826 }
1827
1828 __apicdebuginit(void) print_local_APIC(void *dummy)
1829 {
1830 unsigned int v, ver, maxlvt;
1831 u64 icr;
1832
1833 if (apic_verbosity == APIC_QUIET)
1834 return;
1835
1836 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1837 smp_processor_id(), hard_smp_processor_id());
1838 v = apic_read(APIC_ID);
1839 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1840 v = apic_read(APIC_LVR);
1841 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1842 ver = GET_APIC_VERSION(v);
1843 maxlvt = lapic_get_maxlvt();
1844
1845 v = apic_read(APIC_TASKPRI);
1846 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1847
1848 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1849 if (!APIC_XAPIC(ver)) {
1850 v = apic_read(APIC_ARBPRI);
1851 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1852 v & APIC_ARBPRI_MASK);
1853 }
1854 v = apic_read(APIC_PROCPRI);
1855 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1856 }
1857
1858 /*
1859 * Remote read supported only in the 82489DX and local APIC for
1860 * Pentium processors.
1861 */
1862 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1863 v = apic_read(APIC_RRR);
1864 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1865 }
1866
1867 v = apic_read(APIC_LDR);
1868 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1869 if (!x2apic_enabled()) {
1870 v = apic_read(APIC_DFR);
1871 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1872 }
1873 v = apic_read(APIC_SPIV);
1874 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1875
1876 printk(KERN_DEBUG "... APIC ISR field:\n");
1877 print_APIC_bitfield(APIC_ISR);
1878 printk(KERN_DEBUG "... APIC TMR field:\n");
1879 print_APIC_bitfield(APIC_TMR);
1880 printk(KERN_DEBUG "... APIC IRR field:\n");
1881 print_APIC_bitfield(APIC_IRR);
1882
1883 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1884 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1885 apic_write(APIC_ESR, 0);
1886
1887 v = apic_read(APIC_ESR);
1888 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1889 }
1890
1891 icr = apic_icr_read();
1892 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1893 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1894
1895 v = apic_read(APIC_LVTT);
1896 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1897
1898 if (maxlvt > 3) { /* PC is LVT#4. */
1899 v = apic_read(APIC_LVTPC);
1900 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1901 }
1902 v = apic_read(APIC_LVT0);
1903 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1904 v = apic_read(APIC_LVT1);
1905 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1906
1907 if (maxlvt > 2) { /* ERR is LVT#3. */
1908 v = apic_read(APIC_LVTERR);
1909 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1910 }
1911
1912 v = apic_read(APIC_TMICT);
1913 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1914 v = apic_read(APIC_TMCCT);
1915 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1916 v = apic_read(APIC_TDCR);
1917 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1918 printk("\n");
1919 }
1920
1921 __apicdebuginit(void) print_all_local_APICs(void)
1922 {
1923 int cpu;
1924
1925 preempt_disable();
1926 for_each_online_cpu(cpu)
1927 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1928 preempt_enable();
1929 }
1930
1931 __apicdebuginit(void) print_PIC(void)
1932 {
1933 unsigned int v;
1934 unsigned long flags;
1935
1936 if (apic_verbosity == APIC_QUIET)
1937 return;
1938
1939 printk(KERN_DEBUG "\nprinting PIC contents\n");
1940
1941 spin_lock_irqsave(&i8259A_lock, flags);
1942
1943 v = inb(0xa1) << 8 | inb(0x21);
1944 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1945
1946 v = inb(0xa0) << 8 | inb(0x20);
1947 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1948
1949 outb(0x0b,0xa0);
1950 outb(0x0b,0x20);
1951 v = inb(0xa0) << 8 | inb(0x20);
1952 outb(0x0a,0xa0);
1953 outb(0x0a,0x20);
1954
1955 spin_unlock_irqrestore(&i8259A_lock, flags);
1956
1957 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1958
1959 v = inb(0x4d1) << 8 | inb(0x4d0);
1960 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1961 }
1962
1963 __apicdebuginit(int) print_all_ICs(void)
1964 {
1965 print_PIC();
1966 print_all_local_APICs();
1967 print_IO_APIC();
1968
1969 return 0;
1970 }
1971
1972 fs_initcall(print_all_ICs);
1973
1974
1975 /* Where if anywhere is the i8259 connect in external int mode */
1976 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1977
1978 void __init enable_IO_APIC(void)
1979 {
1980 union IO_APIC_reg_01 reg_01;
1981 int i8259_apic, i8259_pin;
1982 int apic;
1983 unsigned long flags;
1984
1985 #ifdef CONFIG_X86_32
1986 int i;
1987 if (!pirqs_enabled)
1988 for (i = 0; i < MAX_PIRQS; i++)
1989 pirq_entries[i] = -1;
1990 #endif
1991
1992 /*
1993 * The number of IO-APIC IRQ registers (== #pins):
1994 */
1995 for (apic = 0; apic < nr_ioapics; apic++) {
1996 spin_lock_irqsave(&ioapic_lock, flags);
1997 reg_01.raw = io_apic_read(apic, 1);
1998 spin_unlock_irqrestore(&ioapic_lock, flags);
1999 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2000 }
2001 for(apic = 0; apic < nr_ioapics; apic++) {
2002 int pin;
2003 /* See if any of the pins is in ExtINT mode */
2004 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2005 struct IO_APIC_route_entry entry;
2006 entry = ioapic_read_entry(apic, pin);
2007
2008 /* If the interrupt line is enabled and in ExtInt mode
2009 * I have found the pin where the i8259 is connected.
2010 */
2011 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2012 ioapic_i8259.apic = apic;
2013 ioapic_i8259.pin = pin;
2014 goto found_i8259;
2015 }
2016 }
2017 }
2018 found_i8259:
2019 /* Look to see what if the MP table has reported the ExtINT */
2020 /* If we could not find the appropriate pin by looking at the ioapic
2021 * the i8259 probably is not connected the ioapic but give the
2022 * mptable a chance anyway.
2023 */
2024 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2025 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2026 /* Trust the MP table if nothing is setup in the hardware */
2027 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2028 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2029 ioapic_i8259.pin = i8259_pin;
2030 ioapic_i8259.apic = i8259_apic;
2031 }
2032 /* Complain if the MP table and the hardware disagree */
2033 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2034 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2035 {
2036 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2037 }
2038
2039 /*
2040 * Do not trust the IO-APIC being empty at bootup
2041 */
2042 clear_IO_APIC();
2043 }
2044
2045 /*
2046 * Not an __init, needed by the reboot code
2047 */
2048 void disable_IO_APIC(void)
2049 {
2050 /*
2051 * Clear the IO-APIC before rebooting:
2052 */
2053 clear_IO_APIC();
2054
2055 /*
2056 * If the i8259 is routed through an IOAPIC
2057 * Put that IOAPIC in virtual wire mode
2058 * so legacy interrupts can be delivered.
2059 */
2060 if (ioapic_i8259.pin != -1) {
2061 struct IO_APIC_route_entry entry;
2062
2063 memset(&entry, 0, sizeof(entry));
2064 entry.mask = 0; /* Enabled */
2065 entry.trigger = 0; /* Edge */
2066 entry.irr = 0;
2067 entry.polarity = 0; /* High */
2068 entry.delivery_status = 0;
2069 entry.dest_mode = 0; /* Physical */
2070 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2071 entry.vector = 0;
2072 entry.dest = read_apic_id();
2073
2074 /*
2075 * Add it to the IO-APIC irq-routing table:
2076 */
2077 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2078 }
2079
2080 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2081 }
2082
2083 #ifdef CONFIG_X86_32
2084 /*
2085 * function to set the IO-APIC physical IDs based on the
2086 * values stored in the MPC table.
2087 *
2088 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2089 */
2090
2091 static void __init setup_ioapic_ids_from_mpc(void)
2092 {
2093 union IO_APIC_reg_00 reg_00;
2094 physid_mask_t phys_id_present_map;
2095 int apic;
2096 int i;
2097 unsigned char old_id;
2098 unsigned long flags;
2099
2100 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2101 return;
2102
2103 /*
2104 * Don't check I/O APIC IDs for xAPIC systems. They have
2105 * no meaning without the serial APIC bus.
2106 */
2107 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2108 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2109 return;
2110 /*
2111 * This is broken; anything with a real cpu count has to
2112 * circumvent this idiocy regardless.
2113 */
2114 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2115
2116 /*
2117 * Set the IOAPIC ID to the value stored in the MPC table.
2118 */
2119 for (apic = 0; apic < nr_ioapics; apic++) {
2120
2121 /* Read the register 0 value */
2122 spin_lock_irqsave(&ioapic_lock, flags);
2123 reg_00.raw = io_apic_read(apic, 0);
2124 spin_unlock_irqrestore(&ioapic_lock, flags);
2125
2126 old_id = mp_ioapics[apic].mp_apicid;
2127
2128 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
2129 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2130 apic, mp_ioapics[apic].mp_apicid);
2131 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2132 reg_00.bits.ID);
2133 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
2134 }
2135
2136 /*
2137 * Sanity check, is the ID really free? Every APIC in a
2138 * system must have a unique ID or we get lots of nice
2139 * 'stuck on smp_invalidate_needed IPI wait' messages.
2140 */
2141 if (check_apicid_used(phys_id_present_map,
2142 mp_ioapics[apic].mp_apicid)) {
2143 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2144 apic, mp_ioapics[apic].mp_apicid);
2145 for (i = 0; i < get_physical_broadcast(); i++)
2146 if (!physid_isset(i, phys_id_present_map))
2147 break;
2148 if (i >= get_physical_broadcast())
2149 panic("Max APIC ID exceeded!\n");
2150 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2151 i);
2152 physid_set(i, phys_id_present_map);
2153 mp_ioapics[apic].mp_apicid = i;
2154 } else {
2155 physid_mask_t tmp;
2156 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
2157 apic_printk(APIC_VERBOSE, "Setting %d in the "
2158 "phys_id_present_map\n",
2159 mp_ioapics[apic].mp_apicid);
2160 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2161 }
2162
2163
2164 /*
2165 * We need to adjust the IRQ routing table
2166 * if the ID changed.
2167 */
2168 if (old_id != mp_ioapics[apic].mp_apicid)
2169 for (i = 0; i < mp_irq_entries; i++)
2170 if (mp_irqs[i].mp_dstapic == old_id)
2171 mp_irqs[i].mp_dstapic
2172 = mp_ioapics[apic].mp_apicid;
2173
2174 /*
2175 * Read the right value from the MPC table and
2176 * write it into the ID register.
2177 */
2178 apic_printk(APIC_VERBOSE, KERN_INFO
2179 "...changing IO-APIC physical APIC ID to %d ...",
2180 mp_ioapics[apic].mp_apicid);
2181
2182 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
2183 spin_lock_irqsave(&ioapic_lock, flags);
2184 io_apic_write(apic, 0, reg_00.raw);
2185 spin_unlock_irqrestore(&ioapic_lock, flags);
2186
2187 /*
2188 * Sanity check
2189 */
2190 spin_lock_irqsave(&ioapic_lock, flags);
2191 reg_00.raw = io_apic_read(apic, 0);
2192 spin_unlock_irqrestore(&ioapic_lock, flags);
2193 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
2194 printk("could not set ID!\n");
2195 else
2196 apic_printk(APIC_VERBOSE, " ok.\n");
2197 }
2198 }
2199 #endif
2200
2201 int no_timer_check __initdata;
2202
2203 static int __init notimercheck(char *s)
2204 {
2205 no_timer_check = 1;
2206 return 1;
2207 }
2208 __setup("no_timer_check", notimercheck);
2209
2210 /*
2211 * There is a nasty bug in some older SMP boards, their mptable lies
2212 * about the timer IRQ. We do the following to work around the situation:
2213 *
2214 * - timer IRQ defaults to IO-APIC IRQ
2215 * - if this function detects that timer IRQs are defunct, then we fall
2216 * back to ISA timer IRQs
2217 */
2218 static int __init timer_irq_works(void)
2219 {
2220 unsigned long t1 = jiffies;
2221 unsigned long flags;
2222
2223 if (no_timer_check)
2224 return 1;
2225
2226 local_save_flags(flags);
2227 local_irq_enable();
2228 /* Let ten ticks pass... */
2229 mdelay((10 * 1000) / HZ);
2230 local_irq_restore(flags);
2231
2232 /*
2233 * Expect a few ticks at least, to be sure some possible
2234 * glue logic does not lock up after one or two first
2235 * ticks in a non-ExtINT mode. Also the local APIC
2236 * might have cached one ExtINT interrupt. Finally, at
2237 * least one tick may be lost due to delays.
2238 */
2239
2240 /* jiffies wrap? */
2241 if (time_after(jiffies, t1 + 4))
2242 return 1;
2243 return 0;
2244 }
2245
2246 /*
2247 * In the SMP+IOAPIC case it might happen that there are an unspecified
2248 * number of pending IRQ events unhandled. These cases are very rare,
2249 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2250 * better to do it this way as thus we do not have to be aware of
2251 * 'pending' interrupts in the IRQ path, except at this point.
2252 */
2253 /*
2254 * Edge triggered needs to resend any interrupt
2255 * that was delayed but this is now handled in the device
2256 * independent code.
2257 */
2258
2259 /*
2260 * Starting up a edge-triggered IO-APIC interrupt is
2261 * nasty - we need to make sure that we get the edge.
2262 * If it is already asserted for some reason, we need
2263 * return 1 to indicate that is was pending.
2264 *
2265 * This is not complete - we should be able to fake
2266 * an edge even if it isn't on the 8259A...
2267 */
2268
2269 static unsigned int startup_ioapic_irq(unsigned int irq)
2270 {
2271 int was_pending = 0;
2272 unsigned long flags;
2273 struct irq_cfg *cfg;
2274
2275 spin_lock_irqsave(&ioapic_lock, flags);
2276 if (irq < NR_IRQS_LEGACY) {
2277 disable_8259A_irq(irq);
2278 if (i8259A_irq_pending(irq))
2279 was_pending = 1;
2280 }
2281 cfg = irq_cfg(irq);
2282 __unmask_IO_APIC_irq(cfg);
2283 spin_unlock_irqrestore(&ioapic_lock, flags);
2284
2285 return was_pending;
2286 }
2287
2288 #ifdef CONFIG_X86_64
2289 static int ioapic_retrigger_irq(unsigned int irq)
2290 {
2291
2292 struct irq_cfg *cfg = irq_cfg(irq);
2293 unsigned long flags;
2294
2295 spin_lock_irqsave(&vector_lock, flags);
2296 send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2297 spin_unlock_irqrestore(&vector_lock, flags);
2298
2299 return 1;
2300 }
2301 #else
2302 static int ioapic_retrigger_irq(unsigned int irq)
2303 {
2304 send_IPI_self(irq_cfg(irq)->vector);
2305
2306 return 1;
2307 }
2308 #endif
2309
2310 /*
2311 * Level and edge triggered IO-APIC interrupts need different handling,
2312 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2313 * handled with the level-triggered descriptor, but that one has slightly
2314 * more overhead. Level-triggered interrupts cannot be handled with the
2315 * edge-triggered handler, without risking IRQ storms and other ugly
2316 * races.
2317 */
2318
2319 #ifdef CONFIG_SMP
2320
2321 #ifdef CONFIG_INTR_REMAP
2322 static void ir_irq_migration(struct work_struct *work);
2323
2324 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2325
2326 /*
2327 * Migrate the IO-APIC irq in the presence of intr-remapping.
2328 *
2329 * For edge triggered, irq migration is a simple atomic update(of vector
2330 * and cpu destination) of IRTE and flush the hardware cache.
2331 *
2332 * For level triggered, we need to modify the io-apic RTE aswell with the update
2333 * vector information, along with modifying IRTE with vector and destination.
2334 * So irq migration for level triggered is little bit more complex compared to
2335 * edge triggered migration. But the good news is, we use the same algorithm
2336 * for level triggered migration as we have today, only difference being,
2337 * we now initiate the irq migration from process context instead of the
2338 * interrupt context.
2339 *
2340 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2341 * suppression) to the IO-APIC, level triggered irq migration will also be
2342 * as simple as edge triggered migration and we can do the irq migration
2343 * with a simple atomic update to IO-APIC RTE.
2344 */
2345 static void
2346 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2347 {
2348 struct irq_cfg *cfg;
2349 struct irte irte;
2350 int modify_ioapic_rte;
2351 unsigned int dest;
2352 unsigned long flags;
2353 unsigned int irq;
2354
2355 if (!cpumask_intersects(mask, cpu_online_mask))
2356 return;
2357
2358 irq = desc->irq;
2359 if (get_irte(irq, &irte))
2360 return;
2361
2362 cfg = desc->chip_data;
2363 if (assign_irq_vector(irq, cfg, mask))
2364 return;
2365
2366 set_extra_move_desc(desc, mask);
2367
2368 dest = cpu_mask_to_apicid_and(cfg->domain, mask);
2369
2370 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2371 if (modify_ioapic_rte) {
2372 spin_lock_irqsave(&ioapic_lock, flags);
2373 __target_IO_APIC_irq(irq, dest, cfg);
2374 spin_unlock_irqrestore(&ioapic_lock, flags);
2375 }
2376
2377 irte.vector = cfg->vector;
2378 irte.dest_id = IRTE_DEST(dest);
2379
2380 /*
2381 * Modified the IRTE and flushes the Interrupt entry cache.
2382 */
2383 modify_irte(irq, &irte);
2384
2385 if (cfg->move_in_progress)
2386 send_cleanup_vector(cfg);
2387
2388 cpumask_copy(&desc->affinity, mask);
2389 }
2390
2391 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2392 {
2393 int ret = -1;
2394 struct irq_cfg *cfg = desc->chip_data;
2395
2396 mask_IO_APIC_irq_desc(desc);
2397
2398 if (io_apic_level_ack_pending(cfg)) {
2399 /*
2400 * Interrupt in progress. Migrating irq now will change the
2401 * vector information in the IO-APIC RTE and that will confuse
2402 * the EOI broadcast performed by cpu.
2403 * So, delay the irq migration to the next instance.
2404 */
2405 schedule_delayed_work(&ir_migration_work, 1);
2406 goto unmask;
2407 }
2408
2409 /* everthing is clear. we have right of way */
2410 migrate_ioapic_irq_desc(desc, &desc->pending_mask);
2411
2412 ret = 0;
2413 desc->status &= ~IRQ_MOVE_PENDING;
2414 cpumask_clear(&desc->pending_mask);
2415
2416 unmask:
2417 unmask_IO_APIC_irq_desc(desc);
2418
2419 return ret;
2420 }
2421
2422 static void ir_irq_migration(struct work_struct *work)
2423 {
2424 unsigned int irq;
2425 struct irq_desc *desc;
2426
2427 for_each_irq_desc(irq, desc) {
2428 if (desc->status & IRQ_MOVE_PENDING) {
2429 unsigned long flags;
2430
2431 spin_lock_irqsave(&desc->lock, flags);
2432 if (!desc->chip->set_affinity ||
2433 !(desc->status & IRQ_MOVE_PENDING)) {
2434 desc->status &= ~IRQ_MOVE_PENDING;
2435 spin_unlock_irqrestore(&desc->lock, flags);
2436 continue;
2437 }
2438
2439 desc->chip->set_affinity(irq, &desc->pending_mask);
2440 spin_unlock_irqrestore(&desc->lock, flags);
2441 }
2442 }
2443 }
2444
2445 /*
2446 * Migrates the IRQ destination in the process context.
2447 */
2448 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2449 const struct cpumask *mask)
2450 {
2451 if (desc->status & IRQ_LEVEL) {
2452 desc->status |= IRQ_MOVE_PENDING;
2453 cpumask_copy(&desc->pending_mask, mask);
2454 migrate_irq_remapped_level_desc(desc);
2455 return;
2456 }
2457
2458 migrate_ioapic_irq_desc(desc, mask);
2459 }
2460 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2461 const struct cpumask *mask)
2462 {
2463 struct irq_desc *desc = irq_to_desc(irq);
2464
2465 set_ir_ioapic_affinity_irq_desc(desc, mask);
2466 }
2467 #endif
2468
2469 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2470 {
2471 unsigned vector, me;
2472
2473 ack_APIC_irq();
2474 exit_idle();
2475 irq_enter();
2476
2477 me = smp_processor_id();
2478 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2479 unsigned int irq;
2480 struct irq_desc *desc;
2481 struct irq_cfg *cfg;
2482 irq = __get_cpu_var(vector_irq)[vector];
2483
2484 if (irq == -1)
2485 continue;
2486
2487 desc = irq_to_desc(irq);
2488 if (!desc)
2489 continue;
2490
2491 cfg = irq_cfg(irq);
2492 spin_lock(&desc->lock);
2493 if (!cfg->move_cleanup_count)
2494 goto unlock;
2495
2496 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2497 goto unlock;
2498
2499 __get_cpu_var(vector_irq)[vector] = -1;
2500 cfg->move_cleanup_count--;
2501 unlock:
2502 spin_unlock(&desc->lock);
2503 }
2504
2505 irq_exit();
2506 }
2507
2508 static void irq_complete_move(struct irq_desc **descp)
2509 {
2510 struct irq_desc *desc = *descp;
2511 struct irq_cfg *cfg = desc->chip_data;
2512 unsigned vector, me;
2513
2514 if (likely(!cfg->move_in_progress)) {
2515 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2516 if (likely(!cfg->move_desc_pending))
2517 return;
2518
2519 /* domain has not changed, but affinity did */
2520 me = smp_processor_id();
2521 if (cpu_isset(me, desc->affinity)) {
2522 *descp = desc = move_irq_desc(desc, me);
2523 /* get the new one */
2524 cfg = desc->chip_data;
2525 cfg->move_desc_pending = 0;
2526 }
2527 #endif
2528 return;
2529 }
2530
2531 vector = ~get_irq_regs()->orig_ax;
2532 me = smp_processor_id();
2533 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2534 *descp = desc = move_irq_desc(desc, me);
2535 /* get the new one */
2536 cfg = desc->chip_data;
2537 #endif
2538
2539 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2540 send_cleanup_vector(cfg);
2541 }
2542 #else
2543 static inline void irq_complete_move(struct irq_desc **descp) {}
2544 #endif
2545
2546 #ifdef CONFIG_INTR_REMAP
2547 static void ack_x2apic_level(unsigned int irq)
2548 {
2549 ack_x2APIC_irq();
2550 }
2551
2552 static void ack_x2apic_edge(unsigned int irq)
2553 {
2554 ack_x2APIC_irq();
2555 }
2556
2557 #endif
2558
2559 static void ack_apic_edge(unsigned int irq)
2560 {
2561 struct irq_desc *desc = irq_to_desc(irq);
2562
2563 irq_complete_move(&desc);
2564 move_native_irq(irq);
2565 ack_APIC_irq();
2566 }
2567
2568 atomic_t irq_mis_count;
2569
2570 static void ack_apic_level(unsigned int irq)
2571 {
2572 struct irq_desc *desc = irq_to_desc(irq);
2573
2574 #ifdef CONFIG_X86_32
2575 unsigned long v;
2576 int i;
2577 #endif
2578 struct irq_cfg *cfg;
2579 int do_unmask_irq = 0;
2580
2581 irq_complete_move(&desc);
2582 #ifdef CONFIG_GENERIC_PENDING_IRQ
2583 /* If we are moving the irq we need to mask it */
2584 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2585 do_unmask_irq = 1;
2586 mask_IO_APIC_irq_desc(desc);
2587 }
2588 #endif
2589
2590 #ifdef CONFIG_X86_32
2591 /*
2592 * It appears there is an erratum which affects at least version 0x11
2593 * of I/O APIC (that's the 82093AA and cores integrated into various
2594 * chipsets). Under certain conditions a level-triggered interrupt is
2595 * erroneously delivered as edge-triggered one but the respective IRR
2596 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2597 * message but it will never arrive and further interrupts are blocked
2598 * from the source. The exact reason is so far unknown, but the
2599 * phenomenon was observed when two consecutive interrupt requests
2600 * from a given source get delivered to the same CPU and the source is
2601 * temporarily disabled in between.
2602 *
2603 * A workaround is to simulate an EOI message manually. We achieve it
2604 * by setting the trigger mode to edge and then to level when the edge
2605 * trigger mode gets detected in the TMR of a local APIC for a
2606 * level-triggered interrupt. We mask the source for the time of the
2607 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2608 * The idea is from Manfred Spraul. --macro
2609 */
2610 cfg = desc->chip_data;
2611 i = cfg->vector;
2612
2613 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2614 #endif
2615
2616 /*
2617 * We must acknowledge the irq before we move it or the acknowledge will
2618 * not propagate properly.
2619 */
2620 ack_APIC_irq();
2621
2622 /* Now we can move and renable the irq */
2623 if (unlikely(do_unmask_irq)) {
2624 /* Only migrate the irq if the ack has been received.
2625 *
2626 * On rare occasions the broadcast level triggered ack gets
2627 * delayed going to ioapics, and if we reprogram the
2628 * vector while Remote IRR is still set the irq will never
2629 * fire again.
2630 *
2631 * To prevent this scenario we read the Remote IRR bit
2632 * of the ioapic. This has two effects.
2633 * - On any sane system the read of the ioapic will
2634 * flush writes (and acks) going to the ioapic from
2635 * this cpu.
2636 * - We get to see if the ACK has actually been delivered.
2637 *
2638 * Based on failed experiments of reprogramming the
2639 * ioapic entry from outside of irq context starting
2640 * with masking the ioapic entry and then polling until
2641 * Remote IRR was clear before reprogramming the
2642 * ioapic I don't trust the Remote IRR bit to be
2643 * completey accurate.
2644 *
2645 * However there appears to be no other way to plug
2646 * this race, so if the Remote IRR bit is not
2647 * accurate and is causing problems then it is a hardware bug
2648 * and you can go talk to the chipset vendor about it.
2649 */
2650 cfg = desc->chip_data;
2651 if (!io_apic_level_ack_pending(cfg))
2652 move_masked_irq(irq);
2653 unmask_IO_APIC_irq_desc(desc);
2654 }
2655
2656 #ifdef CONFIG_X86_32
2657 if (!(v & (1 << (i & 0x1f)))) {
2658 atomic_inc(&irq_mis_count);
2659 spin_lock(&ioapic_lock);
2660 __mask_and_edge_IO_APIC_irq(cfg);
2661 __unmask_and_level_IO_APIC_irq(cfg);
2662 spin_unlock(&ioapic_lock);
2663 }
2664 #endif
2665 }
2666
2667 static struct irq_chip ioapic_chip __read_mostly = {
2668 .name = "IO-APIC",
2669 .startup = startup_ioapic_irq,
2670 .mask = mask_IO_APIC_irq,
2671 .unmask = unmask_IO_APIC_irq,
2672 .ack = ack_apic_edge,
2673 .eoi = ack_apic_level,
2674 #ifdef CONFIG_SMP
2675 .set_affinity = set_ioapic_affinity_irq,
2676 #endif
2677 .retrigger = ioapic_retrigger_irq,
2678 };
2679
2680 #ifdef CONFIG_INTR_REMAP
2681 static struct irq_chip ir_ioapic_chip __read_mostly = {
2682 .name = "IR-IO-APIC",
2683 .startup = startup_ioapic_irq,
2684 .mask = mask_IO_APIC_irq,
2685 .unmask = unmask_IO_APIC_irq,
2686 .ack = ack_x2apic_edge,
2687 .eoi = ack_x2apic_level,
2688 #ifdef CONFIG_SMP
2689 .set_affinity = set_ir_ioapic_affinity_irq,
2690 #endif
2691 .retrigger = ioapic_retrigger_irq,
2692 };
2693 #endif
2694
2695 static inline void init_IO_APIC_traps(void)
2696 {
2697 int irq;
2698 struct irq_desc *desc;
2699 struct irq_cfg *cfg;
2700
2701 /*
2702 * NOTE! The local APIC isn't very good at handling
2703 * multiple interrupts at the same interrupt level.
2704 * As the interrupt level is determined by taking the
2705 * vector number and shifting that right by 4, we
2706 * want to spread these out a bit so that they don't
2707 * all fall in the same interrupt level.
2708 *
2709 * Also, we've got to be careful not to trash gate
2710 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2711 */
2712 for_each_irq_desc(irq, desc) {
2713 cfg = desc->chip_data;
2714 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2715 /*
2716 * Hmm.. We don't have an entry for this,
2717 * so default to an old-fashioned 8259
2718 * interrupt if we can..
2719 */
2720 if (irq < NR_IRQS_LEGACY)
2721 make_8259A_irq(irq);
2722 else
2723 /* Strange. Oh, well.. */
2724 desc->chip = &no_irq_chip;
2725 }
2726 }
2727 }
2728
2729 /*
2730 * The local APIC irq-chip implementation:
2731 */
2732
2733 static void mask_lapic_irq(unsigned int irq)
2734 {
2735 unsigned long v;
2736
2737 v = apic_read(APIC_LVT0);
2738 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2739 }
2740
2741 static void unmask_lapic_irq(unsigned int irq)
2742 {
2743 unsigned long v;
2744
2745 v = apic_read(APIC_LVT0);
2746 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2747 }
2748
2749 static void ack_lapic_irq(unsigned int irq)
2750 {
2751 ack_APIC_irq();
2752 }
2753
2754 static struct irq_chip lapic_chip __read_mostly = {
2755 .name = "local-APIC",
2756 .mask = mask_lapic_irq,
2757 .unmask = unmask_lapic_irq,
2758 .ack = ack_lapic_irq,
2759 };
2760
2761 static void lapic_register_intr(int irq, struct irq_desc *desc)
2762 {
2763 desc->status &= ~IRQ_LEVEL;
2764 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2765 "edge");
2766 }
2767
2768 static void __init setup_nmi(void)
2769 {
2770 /*
2771 * Dirty trick to enable the NMI watchdog ...
2772 * We put the 8259A master into AEOI mode and
2773 * unmask on all local APICs LVT0 as NMI.
2774 *
2775 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2776 * is from Maciej W. Rozycki - so we do not have to EOI from
2777 * the NMI handler or the timer interrupt.
2778 */
2779 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2780
2781 enable_NMI_through_LVT0();
2782
2783 apic_printk(APIC_VERBOSE, " done.\n");
2784 }
2785
2786 /*
2787 * This looks a bit hackish but it's about the only one way of sending
2788 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2789 * not support the ExtINT mode, unfortunately. We need to send these
2790 * cycles as some i82489DX-based boards have glue logic that keeps the
2791 * 8259A interrupt line asserted until INTA. --macro
2792 */
2793 static inline void __init unlock_ExtINT_logic(void)
2794 {
2795 int apic, pin, i;
2796 struct IO_APIC_route_entry entry0, entry1;
2797 unsigned char save_control, save_freq_select;
2798
2799 pin = find_isa_irq_pin(8, mp_INT);
2800 if (pin == -1) {
2801 WARN_ON_ONCE(1);
2802 return;
2803 }
2804 apic = find_isa_irq_apic(8, mp_INT);
2805 if (apic == -1) {
2806 WARN_ON_ONCE(1);
2807 return;
2808 }
2809
2810 entry0 = ioapic_read_entry(apic, pin);
2811 clear_IO_APIC_pin(apic, pin);
2812
2813 memset(&entry1, 0, sizeof(entry1));
2814
2815 entry1.dest_mode = 0; /* physical delivery */
2816 entry1.mask = 0; /* unmask IRQ now */
2817 entry1.dest = hard_smp_processor_id();
2818 entry1.delivery_mode = dest_ExtINT;
2819 entry1.polarity = entry0.polarity;
2820 entry1.trigger = 0;
2821 entry1.vector = 0;
2822
2823 ioapic_write_entry(apic, pin, entry1);
2824
2825 save_control = CMOS_READ(RTC_CONTROL);
2826 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2827 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2828 RTC_FREQ_SELECT);
2829 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2830
2831 i = 100;
2832 while (i-- > 0) {
2833 mdelay(10);
2834 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2835 i -= 10;
2836 }
2837
2838 CMOS_WRITE(save_control, RTC_CONTROL);
2839 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2840 clear_IO_APIC_pin(apic, pin);
2841
2842 ioapic_write_entry(apic, pin, entry0);
2843 }
2844
2845 static int disable_timer_pin_1 __initdata;
2846 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2847 static int __init disable_timer_pin_setup(char *arg)
2848 {
2849 disable_timer_pin_1 = 1;
2850 return 0;
2851 }
2852 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2853
2854 int timer_through_8259 __initdata;
2855
2856 /*
2857 * This code may look a bit paranoid, but it's supposed to cooperate with
2858 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2859 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2860 * fanatically on his truly buggy board.
2861 *
2862 * FIXME: really need to revamp this for all platforms.
2863 */
2864 static inline void __init check_timer(void)
2865 {
2866 struct irq_desc *desc = irq_to_desc(0);
2867 struct irq_cfg *cfg = desc->chip_data;
2868 int cpu = boot_cpu_id;
2869 int apic1, pin1, apic2, pin2;
2870 unsigned long flags;
2871 unsigned int ver;
2872 int no_pin1 = 0;
2873
2874 local_irq_save(flags);
2875
2876 ver = apic_read(APIC_LVR);
2877 ver = GET_APIC_VERSION(ver);
2878
2879 /*
2880 * get/set the timer IRQ vector:
2881 */
2882 disable_8259A_irq(0);
2883 assign_irq_vector(0, cfg, TARGET_CPUS);
2884
2885 /*
2886 * As IRQ0 is to be enabled in the 8259A, the virtual
2887 * wire has to be disabled in the local APIC. Also
2888 * timer interrupts need to be acknowledged manually in
2889 * the 8259A for the i82489DX when using the NMI
2890 * watchdog as that APIC treats NMIs as level-triggered.
2891 * The AEOI mode will finish them in the 8259A
2892 * automatically.
2893 */
2894 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2895 init_8259A(1);
2896 #ifdef CONFIG_X86_32
2897 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2898 #endif
2899
2900 pin1 = find_isa_irq_pin(0, mp_INT);
2901 apic1 = find_isa_irq_apic(0, mp_INT);
2902 pin2 = ioapic_i8259.pin;
2903 apic2 = ioapic_i8259.apic;
2904
2905 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2906 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2907 cfg->vector, apic1, pin1, apic2, pin2);
2908
2909 /*
2910 * Some BIOS writers are clueless and report the ExtINTA
2911 * I/O APIC input from the cascaded 8259A as the timer
2912 * interrupt input. So just in case, if only one pin
2913 * was found above, try it both directly and through the
2914 * 8259A.
2915 */
2916 if (pin1 == -1) {
2917 #ifdef CONFIG_INTR_REMAP
2918 if (intr_remapping_enabled)
2919 panic("BIOS bug: timer not connected to IO-APIC");
2920 #endif
2921 pin1 = pin2;
2922 apic1 = apic2;
2923 no_pin1 = 1;
2924 } else if (pin2 == -1) {
2925 pin2 = pin1;
2926 apic2 = apic1;
2927 }
2928
2929 if (pin1 != -1) {
2930 /*
2931 * Ok, does IRQ0 through the IOAPIC work?
2932 */
2933 if (no_pin1) {
2934 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2935 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2936 }
2937 unmask_IO_APIC_irq_desc(desc);
2938 if (timer_irq_works()) {
2939 if (nmi_watchdog == NMI_IO_APIC) {
2940 setup_nmi();
2941 enable_8259A_irq(0);
2942 }
2943 if (disable_timer_pin_1 > 0)
2944 clear_IO_APIC_pin(0, pin1);
2945 goto out;
2946 }
2947 #ifdef CONFIG_INTR_REMAP
2948 if (intr_remapping_enabled)
2949 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2950 #endif
2951 clear_IO_APIC_pin(apic1, pin1);
2952 if (!no_pin1)
2953 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2954 "8254 timer not connected to IO-APIC\n");
2955
2956 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2957 "(IRQ0) through the 8259A ...\n");
2958 apic_printk(APIC_QUIET, KERN_INFO
2959 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2960 /*
2961 * legacy devices should be connected to IO APIC #0
2962 */
2963 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2964 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2965 unmask_IO_APIC_irq_desc(desc);
2966 enable_8259A_irq(0);
2967 if (timer_irq_works()) {
2968 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2969 timer_through_8259 = 1;
2970 if (nmi_watchdog == NMI_IO_APIC) {
2971 disable_8259A_irq(0);
2972 setup_nmi();
2973 enable_8259A_irq(0);
2974 }
2975 goto out;
2976 }
2977 /*
2978 * Cleanup, just in case ...
2979 */
2980 disable_8259A_irq(0);
2981 clear_IO_APIC_pin(apic2, pin2);
2982 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2983 }
2984
2985 if (nmi_watchdog == NMI_IO_APIC) {
2986 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2987 "through the IO-APIC - disabling NMI Watchdog!\n");
2988 nmi_watchdog = NMI_NONE;
2989 }
2990 #ifdef CONFIG_X86_32
2991 timer_ack = 0;
2992 #endif
2993
2994 apic_printk(APIC_QUIET, KERN_INFO
2995 "...trying to set up timer as Virtual Wire IRQ...\n");
2996
2997 lapic_register_intr(0, desc);
2998 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2999 enable_8259A_irq(0);
3000
3001 if (timer_irq_works()) {
3002 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3003 goto out;
3004 }
3005 disable_8259A_irq(0);
3006 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3007 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3008
3009 apic_printk(APIC_QUIET, KERN_INFO
3010 "...trying to set up timer as ExtINT IRQ...\n");
3011
3012 init_8259A(0);
3013 make_8259A_irq(0);
3014 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3015
3016 unlock_ExtINT_logic();
3017
3018 if (timer_irq_works()) {
3019 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3020 goto out;
3021 }
3022 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3023 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3024 "report. Then try booting with the 'noapic' option.\n");
3025 out:
3026 local_irq_restore(flags);
3027 }
3028
3029 /*
3030 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3031 * to devices. However there may be an I/O APIC pin available for
3032 * this interrupt regardless. The pin may be left unconnected, but
3033 * typically it will be reused as an ExtINT cascade interrupt for
3034 * the master 8259A. In the MPS case such a pin will normally be
3035 * reported as an ExtINT interrupt in the MP table. With ACPI
3036 * there is no provision for ExtINT interrupts, and in the absence
3037 * of an override it would be treated as an ordinary ISA I/O APIC
3038 * interrupt, that is edge-triggered and unmasked by default. We
3039 * used to do this, but it caused problems on some systems because
3040 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3041 * the same ExtINT cascade interrupt to drive the local APIC of the
3042 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3043 * the I/O APIC in all cases now. No actual device should request
3044 * it anyway. --macro
3045 */
3046 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3047
3048 void __init setup_IO_APIC(void)
3049 {
3050
3051 #ifdef CONFIG_X86_32
3052 enable_IO_APIC();
3053 #else
3054 /*
3055 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3056 */
3057 #endif
3058
3059 io_apic_irqs = ~PIC_IRQS;
3060
3061 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3062 /*
3063 * Set up IO-APIC IRQ routing.
3064 */
3065 #ifdef CONFIG_X86_32
3066 if (!acpi_ioapic)
3067 setup_ioapic_ids_from_mpc();
3068 #endif
3069 sync_Arb_IDs();
3070 setup_IO_APIC_irqs();
3071 init_IO_APIC_traps();
3072 check_timer();
3073 }
3074
3075 /*
3076 * Called after all the initialization is done. If we didnt find any
3077 * APIC bugs then we can allow the modify fast path
3078 */
3079
3080 static int __init io_apic_bug_finalize(void)
3081 {
3082 if (sis_apic_bug == -1)
3083 sis_apic_bug = 0;
3084 return 0;
3085 }
3086
3087 late_initcall(io_apic_bug_finalize);
3088
3089 struct sysfs_ioapic_data {
3090 struct sys_device dev;
3091 struct IO_APIC_route_entry entry[0];
3092 };
3093 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3094
3095 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3096 {
3097 struct IO_APIC_route_entry *entry;
3098 struct sysfs_ioapic_data *data;
3099 int i;
3100
3101 data = container_of(dev, struct sysfs_ioapic_data, dev);
3102 entry = data->entry;
3103 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3104 *entry = ioapic_read_entry(dev->id, i);
3105
3106 return 0;
3107 }
3108
3109 static int ioapic_resume(struct sys_device *dev)
3110 {
3111 struct IO_APIC_route_entry *entry;
3112 struct sysfs_ioapic_data *data;
3113 unsigned long flags;
3114 union IO_APIC_reg_00 reg_00;
3115 int i;
3116
3117 data = container_of(dev, struct sysfs_ioapic_data, dev);
3118 entry = data->entry;
3119
3120 spin_lock_irqsave(&ioapic_lock, flags);
3121 reg_00.raw = io_apic_read(dev->id, 0);
3122 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
3123 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
3124 io_apic_write(dev->id, 0, reg_00.raw);
3125 }
3126 spin_unlock_irqrestore(&ioapic_lock, flags);
3127 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3128 ioapic_write_entry(dev->id, i, entry[i]);
3129
3130 return 0;
3131 }
3132
3133 static struct sysdev_class ioapic_sysdev_class = {
3134 .name = "ioapic",
3135 .suspend = ioapic_suspend,
3136 .resume = ioapic_resume,
3137 };
3138
3139 static int __init ioapic_init_sysfs(void)
3140 {
3141 struct sys_device * dev;
3142 int i, size, error;
3143
3144 error = sysdev_class_register(&ioapic_sysdev_class);
3145 if (error)
3146 return error;
3147
3148 for (i = 0; i < nr_ioapics; i++ ) {
3149 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3150 * sizeof(struct IO_APIC_route_entry);
3151 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3152 if (!mp_ioapic_data[i]) {
3153 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3154 continue;
3155 }
3156 dev = &mp_ioapic_data[i]->dev;
3157 dev->id = i;
3158 dev->cls = &ioapic_sysdev_class;
3159 error = sysdev_register(dev);
3160 if (error) {
3161 kfree(mp_ioapic_data[i]);
3162 mp_ioapic_data[i] = NULL;
3163 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3164 continue;
3165 }
3166 }
3167
3168 return 0;
3169 }
3170
3171 device_initcall(ioapic_init_sysfs);
3172
3173 /*
3174 * Dynamic irq allocate and deallocation
3175 */
3176 unsigned int create_irq_nr(unsigned int irq_want)
3177 {
3178 /* Allocate an unused irq */
3179 unsigned int irq;
3180 unsigned int new;
3181 unsigned long flags;
3182 struct irq_cfg *cfg_new = NULL;
3183 int cpu = boot_cpu_id;
3184 struct irq_desc *desc_new = NULL;
3185
3186 irq = 0;
3187 spin_lock_irqsave(&vector_lock, flags);
3188 for (new = irq_want; new < NR_IRQS; new++) {
3189 if (platform_legacy_irq(new))
3190 continue;
3191
3192 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3193 if (!desc_new) {
3194 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3195 continue;
3196 }
3197 cfg_new = desc_new->chip_data;
3198
3199 if (cfg_new->vector != 0)
3200 continue;
3201 if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0)
3202 irq = new;
3203 break;
3204 }
3205 spin_unlock_irqrestore(&vector_lock, flags);
3206
3207 if (irq > 0) {
3208 dynamic_irq_init(irq);
3209 /* restore it, in case dynamic_irq_init clear it */
3210 if (desc_new)
3211 desc_new->chip_data = cfg_new;
3212 }
3213 return irq;
3214 }
3215
3216 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3217 int create_irq(void)
3218 {
3219 unsigned int irq_want;
3220 int irq;
3221
3222 irq_want = nr_irqs_gsi;
3223 irq = create_irq_nr(irq_want);
3224
3225 if (irq == 0)
3226 irq = -1;
3227
3228 return irq;
3229 }
3230
3231 void destroy_irq(unsigned int irq)
3232 {
3233 unsigned long flags;
3234 struct irq_cfg *cfg;
3235 struct irq_desc *desc;
3236
3237 /* store it, in case dynamic_irq_cleanup clear it */
3238 desc = irq_to_desc(irq);
3239 cfg = desc->chip_data;
3240 dynamic_irq_cleanup(irq);
3241 /* connect back irq_cfg */
3242 if (desc)
3243 desc->chip_data = cfg;
3244
3245 #ifdef CONFIG_INTR_REMAP
3246 free_irte(irq);
3247 #endif
3248 spin_lock_irqsave(&vector_lock, flags);
3249 __clear_irq_vector(irq, cfg);
3250 spin_unlock_irqrestore(&vector_lock, flags);
3251 }
3252
3253 /*
3254 * MSI message composition
3255 */
3256 #ifdef CONFIG_PCI_MSI
3257 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3258 {
3259 struct irq_cfg *cfg;
3260 int err;
3261 unsigned dest;
3262
3263 cfg = irq_cfg(irq);
3264 err = assign_irq_vector(irq, cfg, TARGET_CPUS);
3265 if (err)
3266 return err;
3267
3268 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
3269
3270 #ifdef CONFIG_INTR_REMAP
3271 if (irq_remapped(irq)) {
3272 struct irte irte;
3273 int ir_index;
3274 u16 sub_handle;
3275
3276 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3277 BUG_ON(ir_index == -1);
3278
3279 memset (&irte, 0, sizeof(irte));
3280
3281 irte.present = 1;
3282 irte.dst_mode = INT_DEST_MODE;
3283 irte.trigger_mode = 0; /* edge */
3284 irte.dlvry_mode = INT_DELIVERY_MODE;
3285 irte.vector = cfg->vector;
3286 irte.dest_id = IRTE_DEST(dest);
3287
3288 modify_irte(irq, &irte);
3289
3290 msg->address_hi = MSI_ADDR_BASE_HI;
3291 msg->data = sub_handle;
3292 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3293 MSI_ADDR_IR_SHV |
3294 MSI_ADDR_IR_INDEX1(ir_index) |
3295 MSI_ADDR_IR_INDEX2(ir_index);
3296 } else
3297 #endif
3298 {
3299 msg->address_hi = MSI_ADDR_BASE_HI;
3300 msg->address_lo =
3301 MSI_ADDR_BASE_LO |
3302 ((INT_DEST_MODE == 0) ?
3303 MSI_ADDR_DEST_MODE_PHYSICAL:
3304 MSI_ADDR_DEST_MODE_LOGICAL) |
3305 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3306 MSI_ADDR_REDIRECTION_CPU:
3307 MSI_ADDR_REDIRECTION_LOWPRI) |
3308 MSI_ADDR_DEST_ID(dest);
3309
3310 msg->data =
3311 MSI_DATA_TRIGGER_EDGE |
3312 MSI_DATA_LEVEL_ASSERT |
3313 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3314 MSI_DATA_DELIVERY_FIXED:
3315 MSI_DATA_DELIVERY_LOWPRI) |
3316 MSI_DATA_VECTOR(cfg->vector);
3317 }
3318 return err;
3319 }
3320
3321 #ifdef CONFIG_SMP
3322 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3323 {
3324 struct irq_desc *desc = irq_to_desc(irq);
3325 struct irq_cfg *cfg;
3326 struct msi_msg msg;
3327 unsigned int dest;
3328
3329 dest = set_desc_affinity(desc, mask);
3330 if (dest == BAD_APICID)
3331 return;
3332
3333 cfg = desc->chip_data;
3334
3335 read_msi_msg_desc(desc, &msg);
3336
3337 msg.data &= ~MSI_DATA_VECTOR_MASK;
3338 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3339 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3340 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3341
3342 write_msi_msg_desc(desc, &msg);
3343 }
3344 #ifdef CONFIG_INTR_REMAP
3345 /*
3346 * Migrate the MSI irq to another cpumask. This migration is
3347 * done in the process context using interrupt-remapping hardware.
3348 */
3349 static void
3350 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3351 {
3352 struct irq_desc *desc = irq_to_desc(irq);
3353 struct irq_cfg *cfg = desc->chip_data;
3354 unsigned int dest;
3355 struct irte irte;
3356
3357 if (get_irte(irq, &irte))
3358 return;
3359
3360 dest = set_desc_affinity(desc, mask);
3361 if (dest == BAD_APICID)
3362 return;
3363
3364 irte.vector = cfg->vector;
3365 irte.dest_id = IRTE_DEST(dest);
3366
3367 /*
3368 * atomically update the IRTE with the new destination and vector.
3369 */
3370 modify_irte(irq, &irte);
3371
3372 /*
3373 * After this point, all the interrupts will start arriving
3374 * at the new destination. So, time to cleanup the previous
3375 * vector allocation.
3376 */
3377 if (cfg->move_in_progress)
3378 send_cleanup_vector(cfg);
3379 }
3380
3381 #endif
3382 #endif /* CONFIG_SMP */
3383
3384 /*
3385 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3386 * which implement the MSI or MSI-X Capability Structure.
3387 */
3388 static struct irq_chip msi_chip = {
3389 .name = "PCI-MSI",
3390 .unmask = unmask_msi_irq,
3391 .mask = mask_msi_irq,
3392 .ack = ack_apic_edge,
3393 #ifdef CONFIG_SMP
3394 .set_affinity = set_msi_irq_affinity,
3395 #endif
3396 .retrigger = ioapic_retrigger_irq,
3397 };
3398
3399 #ifdef CONFIG_INTR_REMAP
3400 static struct irq_chip msi_ir_chip = {
3401 .name = "IR-PCI-MSI",
3402 .unmask = unmask_msi_irq,
3403 .mask = mask_msi_irq,
3404 .ack = ack_x2apic_edge,
3405 #ifdef CONFIG_SMP
3406 .set_affinity = ir_set_msi_irq_affinity,
3407 #endif
3408 .retrigger = ioapic_retrigger_irq,
3409 };
3410
3411 /*
3412 * Map the PCI dev to the corresponding remapping hardware unit
3413 * and allocate 'nvec' consecutive interrupt-remapping table entries
3414 * in it.
3415 */
3416 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3417 {
3418 struct intel_iommu *iommu;
3419 int index;
3420
3421 iommu = map_dev_to_ir(dev);
3422 if (!iommu) {
3423 printk(KERN_ERR
3424 "Unable to map PCI %s to iommu\n", pci_name(dev));
3425 return -ENOENT;
3426 }
3427
3428 index = alloc_irte(iommu, irq, nvec);
3429 if (index < 0) {
3430 printk(KERN_ERR
3431 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3432 pci_name(dev));
3433 return -ENOSPC;
3434 }
3435 return index;
3436 }
3437 #endif
3438
3439 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3440 {
3441 int ret;
3442 struct msi_msg msg;
3443
3444 ret = msi_compose_msg(dev, irq, &msg);
3445 if (ret < 0)
3446 return ret;
3447
3448 set_irq_msi(irq, msidesc);
3449 write_msi_msg(irq, &msg);
3450
3451 #ifdef CONFIG_INTR_REMAP
3452 if (irq_remapped(irq)) {
3453 struct irq_desc *desc = irq_to_desc(irq);
3454 /*
3455 * irq migration in process context
3456 */
3457 desc->status |= IRQ_MOVE_PCNTXT;
3458 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3459 } else
3460 #endif
3461 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3462
3463 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3464
3465 return 0;
3466 }
3467
3468 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc)
3469 {
3470 unsigned int irq;
3471 int ret;
3472 unsigned int irq_want;
3473
3474 irq_want = nr_irqs_gsi;
3475 irq = create_irq_nr(irq_want);
3476 if (irq == 0)
3477 return -1;
3478
3479 #ifdef CONFIG_INTR_REMAP
3480 if (!intr_remapping_enabled)
3481 goto no_ir;
3482
3483 ret = msi_alloc_irte(dev, irq, 1);
3484 if (ret < 0)
3485 goto error;
3486 no_ir:
3487 #endif
3488 ret = setup_msi_irq(dev, msidesc, irq);
3489 if (ret < 0) {
3490 destroy_irq(irq);
3491 return ret;
3492 }
3493 return 0;
3494
3495 #ifdef CONFIG_INTR_REMAP
3496 error:
3497 destroy_irq(irq);
3498 return ret;
3499 #endif
3500 }
3501
3502 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3503 {
3504 unsigned int irq;
3505 int ret, sub_handle;
3506 struct msi_desc *msidesc;
3507 unsigned int irq_want;
3508
3509 #ifdef CONFIG_INTR_REMAP
3510 struct intel_iommu *iommu = 0;
3511 int index = 0;
3512 #endif
3513
3514 irq_want = nr_irqs_gsi;
3515 sub_handle = 0;
3516 list_for_each_entry(msidesc, &dev->msi_list, list) {
3517 irq = create_irq_nr(irq_want);
3518 irq_want++;
3519 if (irq == 0)
3520 return -1;
3521 #ifdef CONFIG_INTR_REMAP
3522 if (!intr_remapping_enabled)
3523 goto no_ir;
3524
3525 if (!sub_handle) {
3526 /*
3527 * allocate the consecutive block of IRTE's
3528 * for 'nvec'
3529 */
3530 index = msi_alloc_irte(dev, irq, nvec);
3531 if (index < 0) {
3532 ret = index;
3533 goto error;
3534 }
3535 } else {
3536 iommu = map_dev_to_ir(dev);
3537 if (!iommu) {
3538 ret = -ENOENT;
3539 goto error;
3540 }
3541 /*
3542 * setup the mapping between the irq and the IRTE
3543 * base index, the sub_handle pointing to the
3544 * appropriate interrupt remap table entry.
3545 */
3546 set_irte_irq(irq, iommu, index, sub_handle);
3547 }
3548 no_ir:
3549 #endif
3550 ret = setup_msi_irq(dev, msidesc, irq);
3551 if (ret < 0)
3552 goto error;
3553 sub_handle++;
3554 }
3555 return 0;
3556
3557 error:
3558 destroy_irq(irq);
3559 return ret;
3560 }
3561
3562 void arch_teardown_msi_irq(unsigned int irq)
3563 {
3564 destroy_irq(irq);
3565 }
3566
3567 #ifdef CONFIG_DMAR
3568 #ifdef CONFIG_SMP
3569 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3570 {
3571 struct irq_desc *desc = irq_to_desc(irq);
3572 struct irq_cfg *cfg;
3573 struct msi_msg msg;
3574 unsigned int dest;
3575
3576 dest = set_desc_affinity(desc, mask);
3577 if (dest == BAD_APICID)
3578 return;
3579
3580 cfg = desc->chip_data;
3581
3582 dmar_msi_read(irq, &msg);
3583
3584 msg.data &= ~MSI_DATA_VECTOR_MASK;
3585 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3586 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3587 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3588
3589 dmar_msi_write(irq, &msg);
3590 }
3591
3592 #endif /* CONFIG_SMP */
3593
3594 struct irq_chip dmar_msi_type = {
3595 .name = "DMAR_MSI",
3596 .unmask = dmar_msi_unmask,
3597 .mask = dmar_msi_mask,
3598 .ack = ack_apic_edge,
3599 #ifdef CONFIG_SMP
3600 .set_affinity = dmar_msi_set_affinity,
3601 #endif
3602 .retrigger = ioapic_retrigger_irq,
3603 };
3604
3605 int arch_setup_dmar_msi(unsigned int irq)
3606 {
3607 int ret;
3608 struct msi_msg msg;
3609
3610 ret = msi_compose_msg(NULL, irq, &msg);
3611 if (ret < 0)
3612 return ret;
3613 dmar_msi_write(irq, &msg);
3614 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3615 "edge");
3616 return 0;
3617 }
3618 #endif
3619
3620 #ifdef CONFIG_HPET_TIMER
3621
3622 #ifdef CONFIG_SMP
3623 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3624 {
3625 struct irq_desc *desc = irq_to_desc(irq);
3626 struct irq_cfg *cfg;
3627 struct msi_msg msg;
3628 unsigned int dest;
3629
3630 dest = set_desc_affinity(desc, mask);
3631 if (dest == BAD_APICID)
3632 return;
3633
3634 cfg = desc->chip_data;
3635
3636 hpet_msi_read(irq, &msg);
3637
3638 msg.data &= ~MSI_DATA_VECTOR_MASK;
3639 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3640 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3641 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3642
3643 hpet_msi_write(irq, &msg);
3644 }
3645
3646 #endif /* CONFIG_SMP */
3647
3648 struct irq_chip hpet_msi_type = {
3649 .name = "HPET_MSI",
3650 .unmask = hpet_msi_unmask,
3651 .mask = hpet_msi_mask,
3652 .ack = ack_apic_edge,
3653 #ifdef CONFIG_SMP
3654 .set_affinity = hpet_msi_set_affinity,
3655 #endif
3656 .retrigger = ioapic_retrigger_irq,
3657 };
3658
3659 int arch_setup_hpet_msi(unsigned int irq)
3660 {
3661 int ret;
3662 struct msi_msg msg;
3663
3664 ret = msi_compose_msg(NULL, irq, &msg);
3665 if (ret < 0)
3666 return ret;
3667
3668 hpet_msi_write(irq, &msg);
3669 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3670 "edge");
3671
3672 return 0;
3673 }
3674 #endif
3675
3676 #endif /* CONFIG_PCI_MSI */
3677 /*
3678 * Hypertransport interrupt support
3679 */
3680 #ifdef CONFIG_HT_IRQ
3681
3682 #ifdef CONFIG_SMP
3683
3684 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3685 {
3686 struct ht_irq_msg msg;
3687 fetch_ht_irq_msg(irq, &msg);
3688
3689 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3690 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3691
3692 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3693 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3694
3695 write_ht_irq_msg(irq, &msg);
3696 }
3697
3698 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3699 {
3700 struct irq_desc *desc = irq_to_desc(irq);
3701 struct irq_cfg *cfg;
3702 unsigned int dest;
3703
3704 dest = set_desc_affinity(desc, mask);
3705 if (dest == BAD_APICID)
3706 return;
3707
3708 cfg = desc->chip_data;
3709
3710 target_ht_irq(irq, dest, cfg->vector);
3711 }
3712
3713 #endif
3714
3715 static struct irq_chip ht_irq_chip = {
3716 .name = "PCI-HT",
3717 .mask = mask_ht_irq,
3718 .unmask = unmask_ht_irq,
3719 .ack = ack_apic_edge,
3720 #ifdef CONFIG_SMP
3721 .set_affinity = set_ht_irq_affinity,
3722 #endif
3723 .retrigger = ioapic_retrigger_irq,
3724 };
3725
3726 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3727 {
3728 struct irq_cfg *cfg;
3729 int err;
3730
3731 cfg = irq_cfg(irq);
3732 err = assign_irq_vector(irq, cfg, TARGET_CPUS);
3733 if (!err) {
3734 struct ht_irq_msg msg;
3735 unsigned dest;
3736
3737 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
3738
3739 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3740
3741 msg.address_lo =
3742 HT_IRQ_LOW_BASE |
3743 HT_IRQ_LOW_DEST_ID(dest) |
3744 HT_IRQ_LOW_VECTOR(cfg->vector) |
3745 ((INT_DEST_MODE == 0) ?
3746 HT_IRQ_LOW_DM_PHYSICAL :
3747 HT_IRQ_LOW_DM_LOGICAL) |
3748 HT_IRQ_LOW_RQEOI_EDGE |
3749 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3750 HT_IRQ_LOW_MT_FIXED :
3751 HT_IRQ_LOW_MT_ARBITRATED) |
3752 HT_IRQ_LOW_IRQ_MASKED;
3753
3754 write_ht_irq_msg(irq, &msg);
3755
3756 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3757 handle_edge_irq, "edge");
3758
3759 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3760 }
3761 return err;
3762 }
3763 #endif /* CONFIG_HT_IRQ */
3764
3765 #ifdef CONFIG_X86_64
3766 /*
3767 * Re-target the irq to the specified CPU and enable the specified MMR located
3768 * on the specified blade to allow the sending of MSIs to the specified CPU.
3769 */
3770 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3771 unsigned long mmr_offset)
3772 {
3773 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3774 struct irq_cfg *cfg;
3775 int mmr_pnode;
3776 unsigned long mmr_value;
3777 struct uv_IO_APIC_route_entry *entry;
3778 unsigned long flags;
3779 int err;
3780
3781 cfg = irq_cfg(irq);
3782
3783 err = assign_irq_vector(irq, cfg, eligible_cpu);
3784 if (err != 0)
3785 return err;
3786
3787 spin_lock_irqsave(&vector_lock, flags);
3788 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3789 irq_name);
3790 spin_unlock_irqrestore(&vector_lock, flags);
3791
3792 mmr_value = 0;
3793 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3794 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3795
3796 entry->vector = cfg->vector;
3797 entry->delivery_mode = INT_DELIVERY_MODE;
3798 entry->dest_mode = INT_DEST_MODE;
3799 entry->polarity = 0;
3800 entry->trigger = 0;
3801 entry->mask = 0;
3802 entry->dest = cpu_mask_to_apicid(eligible_cpu);
3803
3804 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3805 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3806
3807 return irq;
3808 }
3809
3810 /*
3811 * Disable the specified MMR located on the specified blade so that MSIs are
3812 * longer allowed to be sent.
3813 */
3814 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3815 {
3816 unsigned long mmr_value;
3817 struct uv_IO_APIC_route_entry *entry;
3818 int mmr_pnode;
3819
3820 mmr_value = 0;
3821 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3822 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3823
3824 entry->mask = 1;
3825
3826 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3827 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3828 }
3829 #endif /* CONFIG_X86_64 */
3830
3831 int __init io_apic_get_redir_entries (int ioapic)
3832 {
3833 union IO_APIC_reg_01 reg_01;
3834 unsigned long flags;
3835
3836 spin_lock_irqsave(&ioapic_lock, flags);
3837 reg_01.raw = io_apic_read(ioapic, 1);
3838 spin_unlock_irqrestore(&ioapic_lock, flags);
3839
3840 return reg_01.bits.entries;
3841 }
3842
3843 void __init probe_nr_irqs_gsi(void)
3844 {
3845 int idx;
3846 int nr = 0;
3847
3848 for (idx = 0; idx < nr_ioapics; idx++)
3849 nr += io_apic_get_redir_entries(idx) + 1;
3850
3851 if (nr > nr_irqs_gsi)
3852 nr_irqs_gsi = nr;
3853 }
3854
3855 /* --------------------------------------------------------------------------
3856 ACPI-based IOAPIC Configuration
3857 -------------------------------------------------------------------------- */
3858
3859 #ifdef CONFIG_ACPI
3860
3861 #ifdef CONFIG_X86_32
3862 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3863 {
3864 union IO_APIC_reg_00 reg_00;
3865 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3866 physid_mask_t tmp;
3867 unsigned long flags;
3868 int i = 0;
3869
3870 /*
3871 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3872 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3873 * supports up to 16 on one shared APIC bus.
3874 *
3875 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3876 * advantage of new APIC bus architecture.
3877 */
3878
3879 if (physids_empty(apic_id_map))
3880 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3881
3882 spin_lock_irqsave(&ioapic_lock, flags);
3883 reg_00.raw = io_apic_read(ioapic, 0);
3884 spin_unlock_irqrestore(&ioapic_lock, flags);
3885
3886 if (apic_id >= get_physical_broadcast()) {
3887 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3888 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3889 apic_id = reg_00.bits.ID;
3890 }
3891
3892 /*
3893 * Every APIC in a system must have a unique ID or we get lots of nice
3894 * 'stuck on smp_invalidate_needed IPI wait' messages.
3895 */
3896 if (check_apicid_used(apic_id_map, apic_id)) {
3897
3898 for (i = 0; i < get_physical_broadcast(); i++) {
3899 if (!check_apicid_used(apic_id_map, i))
3900 break;
3901 }
3902
3903 if (i == get_physical_broadcast())
3904 panic("Max apic_id exceeded!\n");
3905
3906 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3907 "trying %d\n", ioapic, apic_id, i);
3908
3909 apic_id = i;
3910 }
3911
3912 tmp = apicid_to_cpu_present(apic_id);
3913 physids_or(apic_id_map, apic_id_map, tmp);
3914
3915 if (reg_00.bits.ID != apic_id) {
3916 reg_00.bits.ID = apic_id;
3917
3918 spin_lock_irqsave(&ioapic_lock, flags);
3919 io_apic_write(ioapic, 0, reg_00.raw);
3920 reg_00.raw = io_apic_read(ioapic, 0);
3921 spin_unlock_irqrestore(&ioapic_lock, flags);
3922
3923 /* Sanity check */
3924 if (reg_00.bits.ID != apic_id) {
3925 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3926 return -1;
3927 }
3928 }
3929
3930 apic_printk(APIC_VERBOSE, KERN_INFO
3931 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3932
3933 return apic_id;
3934 }
3935
3936 int __init io_apic_get_version(int ioapic)
3937 {
3938 union IO_APIC_reg_01 reg_01;
3939 unsigned long flags;
3940
3941 spin_lock_irqsave(&ioapic_lock, flags);
3942 reg_01.raw = io_apic_read(ioapic, 1);
3943 spin_unlock_irqrestore(&ioapic_lock, flags);
3944
3945 return reg_01.bits.version;
3946 }
3947 #endif
3948
3949 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3950 {
3951 struct irq_desc *desc;
3952 struct irq_cfg *cfg;
3953 int cpu = boot_cpu_id;
3954
3955 if (!IO_APIC_IRQ(irq)) {
3956 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3957 ioapic);
3958 return -EINVAL;
3959 }
3960
3961 desc = irq_to_desc_alloc_cpu(irq, cpu);
3962 if (!desc) {
3963 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3964 return 0;
3965 }
3966
3967 /*
3968 * IRQs < 16 are already in the irq_2_pin[] map
3969 */
3970 if (irq >= NR_IRQS_LEGACY) {
3971 cfg = desc->chip_data;
3972 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3973 }
3974
3975 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3976
3977 return 0;
3978 }
3979
3980
3981 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3982 {
3983 int i;
3984
3985 if (skip_ioapic_setup)
3986 return -1;
3987
3988 for (i = 0; i < mp_irq_entries; i++)
3989 if (mp_irqs[i].mp_irqtype == mp_INT &&
3990 mp_irqs[i].mp_srcbusirq == bus_irq)
3991 break;
3992 if (i >= mp_irq_entries)
3993 return -1;
3994
3995 *trigger = irq_trigger(i);
3996 *polarity = irq_polarity(i);
3997 return 0;
3998 }
3999
4000 #endif /* CONFIG_ACPI */
4001
4002 /*
4003 * This function currently is only a helper for the i386 smp boot process where
4004 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4005 * so mask in all cases should simply be TARGET_CPUS
4006 */
4007 #ifdef CONFIG_SMP
4008 void __init setup_ioapic_dest(void)
4009 {
4010 int pin, ioapic, irq, irq_entry;
4011 struct irq_desc *desc;
4012 struct irq_cfg *cfg;
4013 const struct cpumask *mask;
4014
4015 if (skip_ioapic_setup == 1)
4016 return;
4017
4018 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4019 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4020 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4021 if (irq_entry == -1)
4022 continue;
4023 irq = pin_2_irq(irq_entry, ioapic, pin);
4024
4025 /* setup_IO_APIC_irqs could fail to get vector for some device
4026 * when you have too many devices, because at that time only boot
4027 * cpu is online.
4028 */
4029 desc = irq_to_desc(irq);
4030 cfg = desc->chip_data;
4031 if (!cfg->vector) {
4032 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4033 irq_trigger(irq_entry),
4034 irq_polarity(irq_entry));
4035 continue;
4036
4037 }
4038
4039 /*
4040 * Honour affinities which have been set in early boot
4041 */
4042 if (desc->status &
4043 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4044 mask = &desc->affinity;
4045 else
4046 mask = TARGET_CPUS;
4047
4048 #ifdef CONFIG_INTR_REMAP
4049 if (intr_remapping_enabled)
4050 set_ir_ioapic_affinity_irq_desc(desc, mask);
4051 else
4052 #endif
4053 set_ioapic_affinity_irq_desc(desc, mask);
4054 }
4055
4056 }
4057 }
4058 #endif
4059
4060 #define IOAPIC_RESOURCE_NAME_SIZE 11
4061
4062 static struct resource *ioapic_resources;
4063
4064 static struct resource * __init ioapic_setup_resources(void)
4065 {
4066 unsigned long n;
4067 struct resource *res;
4068 char *mem;
4069 int i;
4070
4071 if (nr_ioapics <= 0)
4072 return NULL;
4073
4074 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4075 n *= nr_ioapics;
4076
4077 mem = alloc_bootmem(n);
4078 res = (void *)mem;
4079
4080 if (mem != NULL) {
4081 mem += sizeof(struct resource) * nr_ioapics;
4082
4083 for (i = 0; i < nr_ioapics; i++) {
4084 res[i].name = mem;
4085 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4086 sprintf(mem, "IOAPIC %u", i);
4087 mem += IOAPIC_RESOURCE_NAME_SIZE;
4088 }
4089 }
4090
4091 ioapic_resources = res;
4092
4093 return res;
4094 }
4095
4096 void __init ioapic_init_mappings(void)
4097 {
4098 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4099 struct resource *ioapic_res;
4100 int i;
4101
4102 ioapic_res = ioapic_setup_resources();
4103 for (i = 0; i < nr_ioapics; i++) {
4104 if (smp_found_config) {
4105 ioapic_phys = mp_ioapics[i].mp_apicaddr;
4106 #ifdef CONFIG_X86_32
4107 if (!ioapic_phys) {
4108 printk(KERN_ERR
4109 "WARNING: bogus zero IO-APIC "
4110 "address found in MPTABLE, "
4111 "disabling IO/APIC support!\n");
4112 smp_found_config = 0;
4113 skip_ioapic_setup = 1;
4114 goto fake_ioapic_page;
4115 }
4116 #endif
4117 } else {
4118 #ifdef CONFIG_X86_32
4119 fake_ioapic_page:
4120 #endif
4121 ioapic_phys = (unsigned long)
4122 alloc_bootmem_pages(PAGE_SIZE);
4123 ioapic_phys = __pa(ioapic_phys);
4124 }
4125 set_fixmap_nocache(idx, ioapic_phys);
4126 apic_printk(APIC_VERBOSE,
4127 "mapped IOAPIC to %08lx (%08lx)\n",
4128 __fix_to_virt(idx), ioapic_phys);
4129 idx++;
4130
4131 if (ioapic_res != NULL) {
4132 ioapic_res->start = ioapic_phys;
4133 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4134 ioapic_res++;
4135 }
4136 }
4137 }
4138
4139 static int __init ioapic_insert_resources(void)
4140 {
4141 int i;
4142 struct resource *r = ioapic_resources;
4143
4144 if (!r) {
4145 printk(KERN_ERR
4146 "IO APIC resources could be not be allocated.\n");
4147 return -1;
4148 }
4149
4150 for (i = 0; i < nr_ioapics; i++) {
4151 insert_resource(&iomem_resource, r);
4152 r++;
4153 }
4154
4155 return 0;
4156 }
4157
4158 /* Insert the IO APIC resources after PCI initialization has occured to handle
4159 * IO APICS that are mapped in on a BAR in PCI space. */
4160 late_initcall(ioapic_insert_resources);
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