2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
53 atomic_t irq_mis_count
;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock
);
59 static DEFINE_SPINLOCK(vector_lock
);
63 * Is the SiS APIC rmw bug present ?
64 * -1 = don't know, 0 = no, 1 = yes
66 int sis_apic_bug
= -1;
69 * # of IRQ routing registers
71 int nr_ioapic_registers
[MAX_IO_APICS
];
73 /* I/O APIC entries */
74 struct mpc_config_ioapic mp_ioapics
[MAX_IO_APICS
];
77 /* MP IRQ source entries */
78 struct mpc_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
80 /* # of MP IRQ source entries */
83 static int disable_timer_pin_1 __initdata
;
86 * Rough estimation of how many shared IRQs there are, can
89 #define MAX_PLUS_SHARED_IRQS NR_IRQS
90 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
93 * This is performance-critical, we want to do it O(1)
95 * the indexing order of this array favors 1:1 mappings
96 * between pins and IRQs.
99 static struct irq_pin_list
{
101 } irq_2_pin
[PIN_MAP_SIZE
];
105 unsigned int unused
[3];
109 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
111 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
112 + (mp_ioapics
[idx
].mpc_apicaddr
& ~PAGE_MASK
);
115 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
117 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
118 writel(reg
, &io_apic
->index
);
119 return readl(&io_apic
->data
);
122 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
124 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
125 writel(reg
, &io_apic
->index
);
126 writel(value
, &io_apic
->data
);
130 * Re-write a value: to be used for read-modify-write
131 * cycles where the read already set up the index register.
133 * Older SiS APIC requires we rewrite the index register
135 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
137 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
139 writel(reg
, &io_apic
->index
);
140 writel(value
, &io_apic
->data
);
144 struct { u32 w1
, w2
; };
145 struct IO_APIC_route_entry entry
;
148 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
150 union entry_union eu
;
152 spin_lock_irqsave(&ioapic_lock
, flags
);
153 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
154 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
155 spin_unlock_irqrestore(&ioapic_lock
, flags
);
160 * When we write a new IO APIC routing entry, we need to write the high
161 * word first! If the mask bit in the low word is clear, we will enable
162 * the interrupt, and we need to make sure the entry is fully populated
163 * before that happens.
166 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
168 union entry_union eu
;
170 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
171 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
174 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
177 spin_lock_irqsave(&ioapic_lock
, flags
);
178 __ioapic_write_entry(apic
, pin
, e
);
179 spin_unlock_irqrestore(&ioapic_lock
, flags
);
183 * When we mask an IO APIC routing entry, we need to write the low
184 * word first, in order to set the mask bit before we change the
187 static void ioapic_mask_entry(int apic
, int pin
)
190 union entry_union eu
= { .entry
.mask
= 1 };
192 spin_lock_irqsave(&ioapic_lock
, flags
);
193 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
194 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
195 spin_unlock_irqrestore(&ioapic_lock
, flags
);
199 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
200 * shared ISA-space IRQs, so we have to support them. We are super
201 * fast in the common case, and fast for shared ISA-space IRQs.
203 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
205 static int first_free_entry
= NR_IRQS
;
206 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
209 entry
= irq_2_pin
+ entry
->next
;
211 if (entry
->pin
!= -1) {
212 entry
->next
= first_free_entry
;
213 entry
= irq_2_pin
+ entry
->next
;
214 if (++first_free_entry
>= PIN_MAP_SIZE
)
215 panic("io_apic.c: whoops");
222 * Reroute an IRQ to a different pin.
224 static void __init
replace_pin_at_irq(unsigned int irq
,
225 int oldapic
, int oldpin
,
226 int newapic
, int newpin
)
228 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
231 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
232 entry
->apic
= newapic
;
237 entry
= irq_2_pin
+ entry
->next
;
241 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
243 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
244 unsigned int pin
, reg
;
250 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
253 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
256 entry
= irq_2_pin
+ entry
->next
;
261 static void __mask_IO_APIC_irq (unsigned int irq
)
263 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
267 static void __unmask_IO_APIC_irq (unsigned int irq
)
269 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
272 /* mask = 1, trigger = 0 */
273 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
275 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
278 /* mask = 0, trigger = 1 */
279 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
281 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
284 static void mask_IO_APIC_irq (unsigned int irq
)
288 spin_lock_irqsave(&ioapic_lock
, flags
);
289 __mask_IO_APIC_irq(irq
);
290 spin_unlock_irqrestore(&ioapic_lock
, flags
);
293 static void unmask_IO_APIC_irq (unsigned int irq
)
297 spin_lock_irqsave(&ioapic_lock
, flags
);
298 __unmask_IO_APIC_irq(irq
);
299 spin_unlock_irqrestore(&ioapic_lock
, flags
);
302 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
304 struct IO_APIC_route_entry entry
;
306 /* Check delivery_mode to be sure we're not clearing an SMI pin */
307 entry
= ioapic_read_entry(apic
, pin
);
308 if (entry
.delivery_mode
== dest_SMI
)
312 * Disable it in the IO-APIC irq-routing table:
314 ioapic_mask_entry(apic
, pin
);
317 static void clear_IO_APIC (void)
321 for (apic
= 0; apic
< nr_ioapics
; apic
++)
322 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
323 clear_IO_APIC_pin(apic
, pin
);
327 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
331 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
332 unsigned int apicid_value
;
335 cpus_and(tmp
, cpumask
, cpu_online_map
);
339 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
341 apicid_value
= cpu_mask_to_apicid(cpumask
);
342 /* Prepare to do the io_apic_write */
343 apicid_value
= apicid_value
<< 24;
344 spin_lock_irqsave(&ioapic_lock
, flags
);
349 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
352 entry
= irq_2_pin
+ entry
->next
;
354 irq_desc
[irq
].affinity
= cpumask
;
355 spin_unlock_irqrestore(&ioapic_lock
, flags
);
358 #if defined(CONFIG_IRQBALANCE)
359 # include <asm/processor.h> /* kernel_thread() */
360 # include <linux/kernel_stat.h> /* kstat */
361 # include <linux/slab.h> /* kmalloc() */
362 # include <linux/timer.h>
364 #define IRQBALANCE_CHECK_ARCH -999
365 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
366 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
367 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
368 #define BALANCED_IRQ_LESS_DELTA (HZ)
370 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
371 static int physical_balance __read_mostly
;
372 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
374 static struct irq_cpu_info
{
375 unsigned long * last_irq
;
376 unsigned long * irq_delta
;
378 } irq_cpu_data
[NR_CPUS
];
380 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
381 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
382 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
384 #define IDLE_ENOUGH(cpu,now) \
385 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
387 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
389 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
391 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
392 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
395 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
397 balance_irq_affinity
[irq
] = mask
;
400 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
401 unsigned long now
, int direction
)
409 if (unlikely(cpu
== curr_cpu
))
412 if (direction
== 1) {
421 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
422 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
427 static inline void balance_irq(int cpu
, int irq
)
429 unsigned long now
= jiffies
;
430 cpumask_t allowed_mask
;
431 unsigned int new_cpu
;
433 if (irqbalance_disabled
)
436 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
437 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
438 if (cpu
!= new_cpu
) {
439 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
443 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
447 for_each_online_cpu(i
) {
448 for (j
= 0; j
< NR_IRQS
; j
++) {
449 if (!irq_desc
[j
].action
)
451 /* Is it a significant load ? */
452 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
453 useful_load_threshold
)
458 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
459 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
463 static void do_irq_balance(void)
466 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
467 unsigned long move_this_load
= 0;
468 int max_loaded
= 0, min_loaded
= 0;
470 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
472 int tmp_loaded
, first_attempt
= 1;
473 unsigned long tmp_cpu_irq
;
474 unsigned long imbalance
= 0;
475 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
477 for_each_possible_cpu(i
) {
482 package_index
= CPU_TO_PACKAGEINDEX(i
);
483 for (j
= 0; j
< NR_IRQS
; j
++) {
484 unsigned long value_now
, delta
;
485 /* Is this an active IRQ or balancing disabled ? */
486 if (!irq_desc
[j
].action
|| irq_balancing_disabled(j
))
488 if ( package_index
== i
)
489 IRQ_DELTA(package_index
,j
) = 0;
490 /* Determine the total count per processor per IRQ */
491 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
493 /* Determine the activity per processor per IRQ */
494 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
496 /* Update last_cpu_irq[][] for the next time */
497 LAST_CPU_IRQ(i
,j
) = value_now
;
499 /* Ignore IRQs whose rate is less than the clock */
500 if (delta
< useful_load_threshold
)
502 /* update the load for the processor or package total */
503 IRQ_DELTA(package_index
,j
) += delta
;
505 /* Keep track of the higher numbered sibling as well */
506 if (i
!= package_index
)
509 * We have sibling A and sibling B in the package
511 * cpu_irq[A] = load for cpu A + load for cpu B
512 * cpu_irq[B] = load for cpu B
514 CPU_IRQ(package_index
) += delta
;
517 /* Find the least loaded processor package */
518 for_each_online_cpu(i
) {
519 if (i
!= CPU_TO_PACKAGEINDEX(i
))
521 if (min_cpu_irq
> CPU_IRQ(i
)) {
522 min_cpu_irq
= CPU_IRQ(i
);
526 max_cpu_irq
= ULONG_MAX
;
529 /* Look for heaviest loaded processor.
530 * We may come back to get the next heaviest loaded processor.
531 * Skip processors with trivial loads.
535 for_each_online_cpu(i
) {
536 if (i
!= CPU_TO_PACKAGEINDEX(i
))
538 if (max_cpu_irq
<= CPU_IRQ(i
))
540 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
541 tmp_cpu_irq
= CPU_IRQ(i
);
546 if (tmp_loaded
== -1) {
547 /* In the case of small number of heavy interrupt sources,
548 * loading some of the cpus too much. We use Ingo's original
549 * approach to rotate them around.
551 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
552 rotate_irqs_among_cpus(useful_load_threshold
);
555 goto not_worth_the_effort
;
558 first_attempt
= 0; /* heaviest search */
559 max_cpu_irq
= tmp_cpu_irq
; /* load */
560 max_loaded
= tmp_loaded
; /* processor */
561 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
563 /* if imbalance is less than approx 10% of max load, then
564 * observe diminishing returns action. - quit
566 if (imbalance
< (max_cpu_irq
>> 3))
567 goto not_worth_the_effort
;
570 /* if we select an IRQ to move that can't go where we want, then
571 * see if there is another one to try.
575 for (j
= 0; j
< NR_IRQS
; j
++) {
576 /* Is this an active IRQ? */
577 if (!irq_desc
[j
].action
)
579 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
581 /* Try to find the IRQ that is closest to the imbalance
582 * without going over.
584 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
585 move_this_load
= IRQ_DELTA(max_loaded
,j
);
589 if (selected_irq
== -1) {
593 imbalance
= move_this_load
;
595 /* For physical_balance case, we accumulated both load
596 * values in the one of the siblings cpu_irq[],
597 * to use the same code for physical and logical processors
598 * as much as possible.
600 * NOTE: the cpu_irq[] array holds the sum of the load for
601 * sibling A and sibling B in the slot for the lowest numbered
602 * sibling (A), _AND_ the load for sibling B in the slot for
603 * the higher numbered sibling.
605 * We seek the least loaded sibling by making the comparison
608 load
= CPU_IRQ(min_loaded
) >> 1;
609 for_each_cpu_mask(j
, per_cpu(cpu_sibling_map
, min_loaded
)) {
610 if (load
> CPU_IRQ(j
)) {
611 /* This won't change cpu_sibling_map[min_loaded] */
617 cpus_and(allowed_mask
,
619 balance_irq_affinity
[selected_irq
]);
620 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
621 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
623 if (!cpus_empty(tmp
)) {
624 /* mark for change destination */
625 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
627 /* Since we made a change, come back sooner to
628 * check for more variation.
630 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
631 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
636 not_worth_the_effort
:
638 * if we did not find an IRQ to move, then adjust the time interval
641 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
642 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
646 static int balanced_irq(void *unused
)
649 unsigned long prev_balance_time
= jiffies
;
650 long time_remaining
= balanced_irq_interval
;
652 /* push everything to CPU 0 to give us a starting point. */
653 for (i
= 0 ; i
< NR_IRQS
; i
++) {
654 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
655 set_pending_irq(i
, cpumask_of_cpu(0));
660 time_remaining
= schedule_timeout_interruptible(time_remaining
);
662 if (time_after(jiffies
,
663 prev_balance_time
+balanced_irq_interval
)) {
666 prev_balance_time
= jiffies
;
667 time_remaining
= balanced_irq_interval
;
674 static int __init
balanced_irq_init(void)
677 struct cpuinfo_x86
*c
;
680 cpus_shift_right(tmp
, cpu_online_map
, 2);
682 /* When not overwritten by the command line ask subarchitecture. */
683 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
684 irqbalance_disabled
= NO_BALANCE_IRQ
;
685 if (irqbalance_disabled
)
688 /* disable irqbalance completely if there is only one processor online */
689 if (num_online_cpus() < 2) {
690 irqbalance_disabled
= 1;
694 * Enable physical balance only if more than 1 physical processor
697 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
698 physical_balance
= 1;
700 for_each_online_cpu(i
) {
701 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
702 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
703 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
704 printk(KERN_ERR
"balanced_irq_init: out of memory");
707 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
708 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
711 printk(KERN_INFO
"Starting balanced_irq\n");
712 if (!IS_ERR(kthread_run(balanced_irq
, NULL
, "kirqd")))
714 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
716 for_each_possible_cpu(i
) {
717 kfree(irq_cpu_data
[i
].irq_delta
);
718 irq_cpu_data
[i
].irq_delta
= NULL
;
719 kfree(irq_cpu_data
[i
].last_irq
);
720 irq_cpu_data
[i
].last_irq
= NULL
;
725 int __devinit
irqbalance_disable(char *str
)
727 irqbalance_disabled
= 1;
731 __setup("noirqbalance", irqbalance_disable
);
733 late_initcall(balanced_irq_init
);
734 #endif /* CONFIG_IRQBALANCE */
735 #endif /* CONFIG_SMP */
738 void send_IPI_self(int vector
)
745 apic_wait_icr_idle();
746 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
748 * Send the IPI. The write to APIC_ICR fires this off.
750 apic_write_around(APIC_ICR
, cfg
);
752 #endif /* !CONFIG_SMP */
756 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
757 * specific CPU-side IRQs.
761 static int pirq_entries
[MAX_PIRQS
];
762 static int pirqs_enabled
;
763 int skip_ioapic_setup
;
765 static int __init
ioapic_pirq_setup(char *str
)
768 int ints
[MAX_PIRQS
+1];
770 get_options(str
, ARRAY_SIZE(ints
), ints
);
772 for (i
= 0; i
< MAX_PIRQS
; i
++)
773 pirq_entries
[i
] = -1;
776 apic_printk(APIC_VERBOSE
, KERN_INFO
777 "PIRQ redirection, working around broken MP-BIOS.\n");
779 if (ints
[0] < MAX_PIRQS
)
782 for (i
= 0; i
< max
; i
++) {
783 apic_printk(APIC_VERBOSE
, KERN_DEBUG
784 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
786 * PIRQs are mapped upside down, usually.
788 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
793 __setup("pirq=", ioapic_pirq_setup
);
796 * Find the IRQ entry number of a certain pin.
798 static int find_irq_entry(int apic
, int pin
, int type
)
802 for (i
= 0; i
< mp_irq_entries
; i
++)
803 if (mp_irqs
[i
].mpc_irqtype
== type
&&
804 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
805 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
806 mp_irqs
[i
].mpc_dstirq
== pin
)
813 * Find the pin to which IRQ[irq] (ISA) is connected
815 static int __init
find_isa_irq_pin(int irq
, int type
)
819 for (i
= 0; i
< mp_irq_entries
; i
++) {
820 int lbus
= mp_irqs
[i
].mpc_srcbus
;
822 if (test_bit(lbus
, mp_bus_not_pci
) &&
823 (mp_irqs
[i
].mpc_irqtype
== type
) &&
824 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
826 return mp_irqs
[i
].mpc_dstirq
;
831 static int __init
find_isa_irq_apic(int irq
, int type
)
835 for (i
= 0; i
< mp_irq_entries
; i
++) {
836 int lbus
= mp_irqs
[i
].mpc_srcbus
;
838 if (test_bit(lbus
, mp_bus_not_pci
) &&
839 (mp_irqs
[i
].mpc_irqtype
== type
) &&
840 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
843 if (i
< mp_irq_entries
) {
845 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
846 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
855 * Find a specific PCI IRQ entry.
856 * Not an __init, possibly needed by modules
858 static int pin_2_irq(int idx
, int apic
, int pin
);
860 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
862 int apic
, i
, best_guess
= -1;
864 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
865 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
866 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
867 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
870 for (i
= 0; i
< mp_irq_entries
; i
++) {
871 int lbus
= mp_irqs
[i
].mpc_srcbus
;
873 for (apic
= 0; apic
< nr_ioapics
; apic
++)
874 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
875 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
878 if (!test_bit(lbus
, mp_bus_not_pci
) &&
879 !mp_irqs
[i
].mpc_irqtype
&&
881 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
882 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
884 if (!(apic
|| IO_APIC_IRQ(irq
)))
887 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
890 * Use the first all-but-pin matching entry as a
891 * best-guess fuzzy result for broken mptables.
899 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
902 * This function currently is only a helper for the i386 smp boot process where
903 * we need to reprogram the ioredtbls to cater for the cpus which have come online
904 * so mask in all cases should simply be TARGET_CPUS
907 void __init
setup_ioapic_dest(void)
909 int pin
, ioapic
, irq
, irq_entry
;
911 if (skip_ioapic_setup
== 1)
914 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
915 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
916 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
919 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
920 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
927 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
929 * EISA Edge/Level control register, ELCR
931 static int EISA_ELCR(unsigned int irq
)
934 unsigned int port
= 0x4d0 + (irq
>> 3);
935 return (inb(port
) >> (irq
& 7)) & 1;
937 apic_printk(APIC_VERBOSE
, KERN_INFO
938 "Broken MPtable reports ISA irq %d\n", irq
);
943 /* ISA interrupts are always polarity zero edge triggered,
944 * when listed as conforming in the MP table. */
946 #define default_ISA_trigger(idx) (0)
947 #define default_ISA_polarity(idx) (0)
949 /* EISA interrupts are always polarity zero and can be edge or level
950 * trigger depending on the ELCR value. If an interrupt is listed as
951 * EISA conforming in the MP table, that means its trigger type must
952 * be read in from the ELCR */
954 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
955 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
957 /* PCI interrupts are always polarity one level triggered,
958 * when listed as conforming in the MP table. */
960 #define default_PCI_trigger(idx) (1)
961 #define default_PCI_polarity(idx) (1)
963 /* MCA interrupts are always polarity zero level triggered,
964 * when listed as conforming in the MP table. */
966 #define default_MCA_trigger(idx) (1)
967 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
969 static int MPBIOS_polarity(int idx
)
971 int bus
= mp_irqs
[idx
].mpc_srcbus
;
975 * Determine IRQ line polarity (high active or low active):
977 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
979 case 0: /* conforms, ie. bus-type dependent polarity */
981 polarity
= test_bit(bus
, mp_bus_not_pci
)?
982 default_ISA_polarity(idx
):
983 default_PCI_polarity(idx
);
986 case 1: /* high active */
991 case 2: /* reserved */
993 printk(KERN_WARNING
"broken BIOS!!\n");
997 case 3: /* low active */
1002 default: /* invalid */
1004 printk(KERN_WARNING
"broken BIOS!!\n");
1012 static int MPBIOS_trigger(int idx
)
1014 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1018 * Determine IRQ trigger mode (edge or level sensitive):
1020 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
1022 case 0: /* conforms, ie. bus-type dependent */
1024 trigger
= test_bit(bus
, mp_bus_not_pci
)?
1025 default_ISA_trigger(idx
):
1026 default_PCI_trigger(idx
);
1027 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1028 switch (mp_bus_id_to_type
[bus
])
1030 case MP_BUS_ISA
: /* ISA pin */
1032 /* set before the switch */
1035 case MP_BUS_EISA
: /* EISA pin */
1037 trigger
= default_EISA_trigger(idx
);
1040 case MP_BUS_PCI
: /* PCI pin */
1042 /* set before the switch */
1045 case MP_BUS_MCA
: /* MCA pin */
1047 trigger
= default_MCA_trigger(idx
);
1052 printk(KERN_WARNING
"broken BIOS!!\n");
1065 case 2: /* reserved */
1067 printk(KERN_WARNING
"broken BIOS!!\n");
1076 default: /* invalid */
1078 printk(KERN_WARNING
"broken BIOS!!\n");
1086 static inline int irq_polarity(int idx
)
1088 return MPBIOS_polarity(idx
);
1091 static inline int irq_trigger(int idx
)
1093 return MPBIOS_trigger(idx
);
1096 static int pin_2_irq(int idx
, int apic
, int pin
)
1099 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1102 * Debugging check, we are in big trouble if this message pops up!
1104 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1105 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1107 if (test_bit(bus
, mp_bus_not_pci
))
1108 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1111 * PCI IRQs are mapped in order
1115 irq
+= nr_ioapic_registers
[i
++];
1119 * For MPS mode, so far only needed by ES7000 platform
1121 if (ioapic_renumber_irq
)
1122 irq
= ioapic_renumber_irq(apic
, irq
);
1126 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1128 if ((pin
>= 16) && (pin
<= 23)) {
1129 if (pirq_entries
[pin
-16] != -1) {
1130 if (!pirq_entries
[pin
-16]) {
1131 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1132 "disabling PIRQ%d\n", pin
-16);
1134 irq
= pirq_entries
[pin
-16];
1135 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1136 "using PIRQ%d -> IRQ %d\n",
1144 static inline int IO_APIC_irq_trigger(int irq
)
1148 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1149 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1150 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1151 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1152 return irq_trigger(idx
);
1156 * nonexistent IRQs are edge default
1161 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1162 static u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1164 static int __assign_irq_vector(int irq
)
1166 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1169 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1171 if (irq_vector
[irq
] > 0)
1172 return irq_vector
[irq
];
1174 vector
= current_vector
;
1175 offset
= current_offset
;
1178 if (vector
>= FIRST_SYSTEM_VECTOR
) {
1179 offset
= (offset
+ 1) % 8;
1180 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1182 if (vector
== current_vector
)
1184 if (test_and_set_bit(vector
, used_vectors
))
1187 current_vector
= vector
;
1188 current_offset
= offset
;
1189 irq_vector
[irq
] = vector
;
1194 static int assign_irq_vector(int irq
)
1196 unsigned long flags
;
1199 spin_lock_irqsave(&vector_lock
, flags
);
1200 vector
= __assign_irq_vector(irq
);
1201 spin_unlock_irqrestore(&vector_lock
, flags
);
1205 static struct irq_chip ioapic_chip
;
1207 #define IOAPIC_AUTO -1
1208 #define IOAPIC_EDGE 0
1209 #define IOAPIC_LEVEL 1
1211 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1213 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1214 trigger
== IOAPIC_LEVEL
) {
1215 irq_desc
[irq
].status
|= IRQ_LEVEL
;
1216 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1217 handle_fasteoi_irq
, "fasteoi");
1219 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1220 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1221 handle_edge_irq
, "edge");
1223 set_intr_gate(vector
, interrupt
[irq
]);
1226 static void __init
setup_IO_APIC_irqs(void)
1228 struct IO_APIC_route_entry entry
;
1229 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1231 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1233 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1234 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1237 * add it to the IO-APIC irq-routing table:
1239 memset(&entry
,0,sizeof(entry
));
1241 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1242 entry
.dest_mode
= INT_DEST_MODE
;
1243 entry
.mask
= 0; /* enable IRQ */
1244 entry
.dest
.logical
.logical_dest
=
1245 cpu_mask_to_apicid(TARGET_CPUS
);
1247 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1250 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1251 " IO-APIC (apicid-pin) %d-%d",
1252 mp_ioapics
[apic
].mpc_apicid
,
1256 apic_printk(APIC_VERBOSE
, ", %d-%d",
1257 mp_ioapics
[apic
].mpc_apicid
, pin
);
1261 if (!first_notcon
) {
1262 apic_printk(APIC_VERBOSE
, " not connected.\n");
1266 entry
.trigger
= irq_trigger(idx
);
1267 entry
.polarity
= irq_polarity(idx
);
1269 if (irq_trigger(idx
)) {
1274 irq
= pin_2_irq(idx
, apic
, pin
);
1276 * skip adding the timer int on secondary nodes, which causes
1277 * a small but painful rift in the time-space continuum
1279 if (multi_timer_check(apic
, irq
))
1282 add_pin_to_irq(irq
, apic
, pin
);
1284 if (!apic
&& !IO_APIC_IRQ(irq
))
1287 if (IO_APIC_IRQ(irq
)) {
1288 vector
= assign_irq_vector(irq
);
1289 entry
.vector
= vector
;
1290 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1292 if (!apic
&& (irq
< 16))
1293 disable_8259A_irq(irq
);
1295 ioapic_write_entry(apic
, pin
, entry
);
1300 apic_printk(APIC_VERBOSE
, " not connected.\n");
1304 * Set up the 8259A-master output pin:
1306 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1308 struct IO_APIC_route_entry entry
;
1310 memset(&entry
,0,sizeof(entry
));
1312 disable_8259A_irq(0);
1315 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1318 * We use logical delivery to get the timer IRQ
1321 entry
.dest_mode
= INT_DEST_MODE
;
1322 entry
.mask
= 0; /* unmask IRQ now */
1323 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1324 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1327 entry
.vector
= vector
;
1330 * The timer IRQ doesn't have to know that behind the
1331 * scene we have a 8259A-master in AEOI mode ...
1333 irq_desc
[0].chip
= &ioapic_chip
;
1334 set_irq_handler(0, handle_edge_irq
);
1337 * Add it to the IO-APIC irq-routing table:
1339 ioapic_write_entry(apic
, pin
, entry
);
1341 enable_8259A_irq(0);
1344 void __init
print_IO_APIC(void)
1347 union IO_APIC_reg_00 reg_00
;
1348 union IO_APIC_reg_01 reg_01
;
1349 union IO_APIC_reg_02 reg_02
;
1350 union IO_APIC_reg_03 reg_03
;
1351 unsigned long flags
;
1353 if (apic_verbosity
== APIC_QUIET
)
1356 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1357 for (i
= 0; i
< nr_ioapics
; i
++)
1358 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1359 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1362 * We are a bit conservative about what we expect. We have to
1363 * know about every hardware change ASAP.
1365 printk(KERN_INFO
"testing the IO APIC.......................\n");
1367 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1369 spin_lock_irqsave(&ioapic_lock
, flags
);
1370 reg_00
.raw
= io_apic_read(apic
, 0);
1371 reg_01
.raw
= io_apic_read(apic
, 1);
1372 if (reg_01
.bits
.version
>= 0x10)
1373 reg_02
.raw
= io_apic_read(apic
, 2);
1374 if (reg_01
.bits
.version
>= 0x20)
1375 reg_03
.raw
= io_apic_read(apic
, 3);
1376 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1378 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1379 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1380 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1381 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1382 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1384 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1385 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1387 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1388 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1391 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1392 * but the value of reg_02 is read as the previous read register
1393 * value, so ignore it if reg_02 == reg_01.
1395 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1396 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1397 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1401 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1402 * or reg_03, but the value of reg_0[23] is read as the previous read
1403 * register value, so ignore it if reg_03 == reg_0[12].
1405 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1406 reg_03
.raw
!= reg_01
.raw
) {
1407 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1408 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1411 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1413 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1414 " Stat Dest Deli Vect: \n");
1416 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1417 struct IO_APIC_route_entry entry
;
1419 entry
= ioapic_read_entry(apic
, i
);
1421 printk(KERN_DEBUG
" %02x %03X %02X ",
1423 entry
.dest
.logical
.logical_dest
,
1424 entry
.dest
.physical
.physical_dest
1427 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1432 entry
.delivery_status
,
1434 entry
.delivery_mode
,
1439 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1440 for (i
= 0; i
< NR_IRQS
; i
++) {
1441 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1444 printk(KERN_DEBUG
"IRQ%d ", i
);
1446 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1449 entry
= irq_2_pin
+ entry
->next
;
1454 printk(KERN_INFO
".................................... done.\n");
1461 static void print_APIC_bitfield (int base
)
1466 if (apic_verbosity
== APIC_QUIET
)
1469 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1470 for (i
= 0; i
< 8; i
++) {
1471 v
= apic_read(base
+ i
*0x10);
1472 for (j
= 0; j
< 32; j
++) {
1482 void /*__init*/ print_local_APIC(void * dummy
)
1484 unsigned int v
, ver
, maxlvt
;
1486 if (apic_verbosity
== APIC_QUIET
)
1489 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1490 smp_processor_id(), hard_smp_processor_id());
1491 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1492 GET_APIC_ID(read_apic_id()));
1493 v
= apic_read(APIC_LVR
);
1494 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1495 ver
= GET_APIC_VERSION(v
);
1496 maxlvt
= lapic_get_maxlvt();
1498 v
= apic_read(APIC_TASKPRI
);
1499 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1501 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1502 v
= apic_read(APIC_ARBPRI
);
1503 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1504 v
& APIC_ARBPRI_MASK
);
1505 v
= apic_read(APIC_PROCPRI
);
1506 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1509 v
= apic_read(APIC_EOI
);
1510 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1511 v
= apic_read(APIC_RRR
);
1512 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1513 v
= apic_read(APIC_LDR
);
1514 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1515 v
= apic_read(APIC_DFR
);
1516 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1517 v
= apic_read(APIC_SPIV
);
1518 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1520 printk(KERN_DEBUG
"... APIC ISR field:\n");
1521 print_APIC_bitfield(APIC_ISR
);
1522 printk(KERN_DEBUG
"... APIC TMR field:\n");
1523 print_APIC_bitfield(APIC_TMR
);
1524 printk(KERN_DEBUG
"... APIC IRR field:\n");
1525 print_APIC_bitfield(APIC_IRR
);
1527 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1528 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1529 apic_write(APIC_ESR
, 0);
1530 v
= apic_read(APIC_ESR
);
1531 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1534 v
= apic_read(APIC_ICR
);
1535 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1536 v
= apic_read(APIC_ICR2
);
1537 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1539 v
= apic_read(APIC_LVTT
);
1540 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1542 if (maxlvt
> 3) { /* PC is LVT#4. */
1543 v
= apic_read(APIC_LVTPC
);
1544 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1546 v
= apic_read(APIC_LVT0
);
1547 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1548 v
= apic_read(APIC_LVT1
);
1549 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1551 if (maxlvt
> 2) { /* ERR is LVT#3. */
1552 v
= apic_read(APIC_LVTERR
);
1553 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1556 v
= apic_read(APIC_TMICT
);
1557 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1558 v
= apic_read(APIC_TMCCT
);
1559 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1560 v
= apic_read(APIC_TDCR
);
1561 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1565 void print_all_local_APICs (void)
1567 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1570 void /*__init*/ print_PIC(void)
1573 unsigned long flags
;
1575 if (apic_verbosity
== APIC_QUIET
)
1578 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1580 spin_lock_irqsave(&i8259A_lock
, flags
);
1582 v
= inb(0xa1) << 8 | inb(0x21);
1583 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1585 v
= inb(0xa0) << 8 | inb(0x20);
1586 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1590 v
= inb(0xa0) << 8 | inb(0x20);
1594 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1596 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1598 v
= inb(0x4d1) << 8 | inb(0x4d0);
1599 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1604 static void __init
enable_IO_APIC(void)
1606 union IO_APIC_reg_01 reg_01
;
1607 int i8259_apic
, i8259_pin
;
1609 unsigned long flags
;
1611 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1612 irq_2_pin
[i
].pin
= -1;
1613 irq_2_pin
[i
].next
= 0;
1616 for (i
= 0; i
< MAX_PIRQS
; i
++)
1617 pirq_entries
[i
] = -1;
1620 * The number of IO-APIC IRQ registers (== #pins):
1622 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1623 spin_lock_irqsave(&ioapic_lock
, flags
);
1624 reg_01
.raw
= io_apic_read(apic
, 1);
1625 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1626 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1628 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1630 /* See if any of the pins is in ExtINT mode */
1631 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1632 struct IO_APIC_route_entry entry
;
1633 entry
= ioapic_read_entry(apic
, pin
);
1636 /* If the interrupt line is enabled and in ExtInt mode
1637 * I have found the pin where the i8259 is connected.
1639 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1640 ioapic_i8259
.apic
= apic
;
1641 ioapic_i8259
.pin
= pin
;
1647 /* Look to see what if the MP table has reported the ExtINT */
1648 /* If we could not find the appropriate pin by looking at the ioapic
1649 * the i8259 probably is not connected the ioapic but give the
1650 * mptable a chance anyway.
1652 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1653 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1654 /* Trust the MP table if nothing is setup in the hardware */
1655 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1656 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1657 ioapic_i8259
.pin
= i8259_pin
;
1658 ioapic_i8259
.apic
= i8259_apic
;
1660 /* Complain if the MP table and the hardware disagree */
1661 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1662 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1664 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1668 * Do not trust the IO-APIC being empty at bootup
1674 * Not an __init, needed by the reboot code
1676 void disable_IO_APIC(void)
1679 * Clear the IO-APIC before rebooting:
1684 * If the i8259 is routed through an IOAPIC
1685 * Put that IOAPIC in virtual wire mode
1686 * so legacy interrupts can be delivered.
1688 if (ioapic_i8259
.pin
!= -1) {
1689 struct IO_APIC_route_entry entry
;
1691 memset(&entry
, 0, sizeof(entry
));
1692 entry
.mask
= 0; /* Enabled */
1693 entry
.trigger
= 0; /* Edge */
1695 entry
.polarity
= 0; /* High */
1696 entry
.delivery_status
= 0;
1697 entry
.dest_mode
= 0; /* Physical */
1698 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1700 entry
.dest
.physical
.physical_dest
=
1701 GET_APIC_ID(read_apic_id());
1704 * Add it to the IO-APIC irq-routing table:
1706 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1708 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1712 * function to set the IO-APIC physical IDs based on the
1713 * values stored in the MPC table.
1715 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1718 #ifndef CONFIG_X86_NUMAQ
1719 static void __init
setup_ioapic_ids_from_mpc(void)
1721 union IO_APIC_reg_00 reg_00
;
1722 physid_mask_t phys_id_present_map
;
1725 unsigned char old_id
;
1726 unsigned long flags
;
1729 * Don't check I/O APIC IDs for xAPIC systems. They have
1730 * no meaning without the serial APIC bus.
1732 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1733 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1736 * This is broken; anything with a real cpu count has to
1737 * circumvent this idiocy regardless.
1739 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1742 * Set the IOAPIC ID to the value stored in the MPC table.
1744 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1746 /* Read the register 0 value */
1747 spin_lock_irqsave(&ioapic_lock
, flags
);
1748 reg_00
.raw
= io_apic_read(apic
, 0);
1749 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1751 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1753 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1754 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1755 apic
, mp_ioapics
[apic
].mpc_apicid
);
1756 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1758 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1762 * Sanity check, is the ID really free? Every APIC in a
1763 * system must have a unique ID or we get lots of nice
1764 * 'stuck on smp_invalidate_needed IPI wait' messages.
1766 if (check_apicid_used(phys_id_present_map
,
1767 mp_ioapics
[apic
].mpc_apicid
)) {
1768 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1769 apic
, mp_ioapics
[apic
].mpc_apicid
);
1770 for (i
= 0; i
< get_physical_broadcast(); i
++)
1771 if (!physid_isset(i
, phys_id_present_map
))
1773 if (i
>= get_physical_broadcast())
1774 panic("Max APIC ID exceeded!\n");
1775 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1777 physid_set(i
, phys_id_present_map
);
1778 mp_ioapics
[apic
].mpc_apicid
= i
;
1781 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1782 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1783 "phys_id_present_map\n",
1784 mp_ioapics
[apic
].mpc_apicid
);
1785 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1790 * We need to adjust the IRQ routing table
1791 * if the ID changed.
1793 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1794 for (i
= 0; i
< mp_irq_entries
; i
++)
1795 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1796 mp_irqs
[i
].mpc_dstapic
1797 = mp_ioapics
[apic
].mpc_apicid
;
1800 * Read the right value from the MPC table and
1801 * write it into the ID register.
1803 apic_printk(APIC_VERBOSE
, KERN_INFO
1804 "...changing IO-APIC physical APIC ID to %d ...",
1805 mp_ioapics
[apic
].mpc_apicid
);
1807 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1808 spin_lock_irqsave(&ioapic_lock
, flags
);
1809 io_apic_write(apic
, 0, reg_00
.raw
);
1810 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1815 spin_lock_irqsave(&ioapic_lock
, flags
);
1816 reg_00
.raw
= io_apic_read(apic
, 0);
1817 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1818 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1819 printk("could not set ID!\n");
1821 apic_printk(APIC_VERBOSE
, " ok.\n");
1825 static void __init
setup_ioapic_ids_from_mpc(void) { }
1828 int no_timer_check __initdata
;
1830 static int __init
notimercheck(char *s
)
1835 __setup("no_timer_check", notimercheck
);
1838 * There is a nasty bug in some older SMP boards, their mptable lies
1839 * about the timer IRQ. We do the following to work around the situation:
1841 * - timer IRQ defaults to IO-APIC IRQ
1842 * - if this function detects that timer IRQs are defunct, then we fall
1843 * back to ISA timer IRQs
1845 static int __init
timer_irq_works(void)
1847 unsigned long t1
= jiffies
;
1848 unsigned long flags
;
1853 local_save_flags(flags
);
1855 /* Let ten ticks pass... */
1856 mdelay((10 * 1000) / HZ
);
1857 local_irq_restore(flags
);
1860 * Expect a few ticks at least, to be sure some possible
1861 * glue logic does not lock up after one or two first
1862 * ticks in a non-ExtINT mode. Also the local APIC
1863 * might have cached one ExtINT interrupt. Finally, at
1864 * least one tick may be lost due to delays.
1866 if (time_after(jiffies
, t1
+ 4))
1873 * In the SMP+IOAPIC case it might happen that there are an unspecified
1874 * number of pending IRQ events unhandled. These cases are very rare,
1875 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1876 * better to do it this way as thus we do not have to be aware of
1877 * 'pending' interrupts in the IRQ path, except at this point.
1880 * Edge triggered needs to resend any interrupt
1881 * that was delayed but this is now handled in the device
1888 * Starting up a edge-triggered IO-APIC interrupt is
1889 * nasty - we need to make sure that we get the edge.
1890 * If it is already asserted for some reason, we need
1891 * return 1 to indicate that is was pending.
1893 * This is not complete - we should be able to fake
1894 * an edge even if it isn't on the 8259A...
1896 * (We do this for level-triggered IRQs too - it cannot hurt.)
1898 static unsigned int startup_ioapic_irq(unsigned int irq
)
1900 int was_pending
= 0;
1901 unsigned long flags
;
1903 spin_lock_irqsave(&ioapic_lock
, flags
);
1905 disable_8259A_irq(irq
);
1906 if (i8259A_irq_pending(irq
))
1909 __unmask_IO_APIC_irq(irq
);
1910 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1915 static void ack_ioapic_irq(unsigned int irq
)
1917 move_native_irq(irq
);
1921 static void ack_ioapic_quirk_irq(unsigned int irq
)
1926 move_native_irq(irq
);
1928 * It appears there is an erratum which affects at least version 0x11
1929 * of I/O APIC (that's the 82093AA and cores integrated into various
1930 * chipsets). Under certain conditions a level-triggered interrupt is
1931 * erroneously delivered as edge-triggered one but the respective IRR
1932 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1933 * message but it will never arrive and further interrupts are blocked
1934 * from the source. The exact reason is so far unknown, but the
1935 * phenomenon was observed when two consecutive interrupt requests
1936 * from a given source get delivered to the same CPU and the source is
1937 * temporarily disabled in between.
1939 * A workaround is to simulate an EOI message manually. We achieve it
1940 * by setting the trigger mode to edge and then to level when the edge
1941 * trigger mode gets detected in the TMR of a local APIC for a
1942 * level-triggered interrupt. We mask the source for the time of the
1943 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1944 * The idea is from Manfred Spraul. --macro
1946 i
= irq_vector
[irq
];
1948 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1952 if (!(v
& (1 << (i
& 0x1f)))) {
1953 atomic_inc(&irq_mis_count
);
1954 spin_lock(&ioapic_lock
);
1955 __mask_and_edge_IO_APIC_irq(irq
);
1956 __unmask_and_level_IO_APIC_irq(irq
);
1957 spin_unlock(&ioapic_lock
);
1961 static int ioapic_retrigger_irq(unsigned int irq
)
1963 send_IPI_self(irq_vector
[irq
]);
1968 static struct irq_chip ioapic_chip __read_mostly
= {
1970 .startup
= startup_ioapic_irq
,
1971 .mask
= mask_IO_APIC_irq
,
1972 .unmask
= unmask_IO_APIC_irq
,
1973 .ack
= ack_ioapic_irq
,
1974 .eoi
= ack_ioapic_quirk_irq
,
1976 .set_affinity
= set_ioapic_affinity_irq
,
1978 .retrigger
= ioapic_retrigger_irq
,
1982 static inline void init_IO_APIC_traps(void)
1987 * NOTE! The local APIC isn't very good at handling
1988 * multiple interrupts at the same interrupt level.
1989 * As the interrupt level is determined by taking the
1990 * vector number and shifting that right by 4, we
1991 * want to spread these out a bit so that they don't
1992 * all fall in the same interrupt level.
1994 * Also, we've got to be careful not to trash gate
1995 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1997 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1998 if (IO_APIC_IRQ(irq
) && !irq_vector
[irq
]) {
2000 * Hmm.. We don't have an entry for this,
2001 * so default to an old-fashioned 8259
2002 * interrupt if we can..
2005 make_8259A_irq(irq
);
2007 /* Strange. Oh, well.. */
2008 irq_desc
[irq
].chip
= &no_irq_chip
;
2014 * The local APIC irq-chip implementation:
2017 static void ack_apic(unsigned int irq
)
2022 static void mask_lapic_irq (unsigned int irq
)
2026 v
= apic_read(APIC_LVT0
);
2027 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2030 static void unmask_lapic_irq (unsigned int irq
)
2034 v
= apic_read(APIC_LVT0
);
2035 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2038 static struct irq_chip lapic_chip __read_mostly
= {
2039 .name
= "local-APIC-edge",
2040 .mask
= mask_lapic_irq
,
2041 .unmask
= unmask_lapic_irq
,
2045 static void __init
setup_nmi(void)
2048 * Dirty trick to enable the NMI watchdog ...
2049 * We put the 8259A master into AEOI mode and
2050 * unmask on all local APICs LVT0 as NMI.
2052 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2053 * is from Maciej W. Rozycki - so we do not have to EOI from
2054 * the NMI handler or the timer interrupt.
2056 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2058 enable_NMI_through_LVT0();
2060 apic_printk(APIC_VERBOSE
, " done.\n");
2064 * This looks a bit hackish but it's about the only one way of sending
2065 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2066 * not support the ExtINT mode, unfortunately. We need to send these
2067 * cycles as some i82489DX-based boards have glue logic that keeps the
2068 * 8259A interrupt line asserted until INTA. --macro
2070 static inline void __init
unlock_ExtINT_logic(void)
2073 struct IO_APIC_route_entry entry0
, entry1
;
2074 unsigned char save_control
, save_freq_select
;
2076 pin
= find_isa_irq_pin(8, mp_INT
);
2081 apic
= find_isa_irq_apic(8, mp_INT
);
2087 entry0
= ioapic_read_entry(apic
, pin
);
2088 clear_IO_APIC_pin(apic
, pin
);
2090 memset(&entry1
, 0, sizeof(entry1
));
2092 entry1
.dest_mode
= 0; /* physical delivery */
2093 entry1
.mask
= 0; /* unmask IRQ now */
2094 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2095 entry1
.delivery_mode
= dest_ExtINT
;
2096 entry1
.polarity
= entry0
.polarity
;
2100 ioapic_write_entry(apic
, pin
, entry1
);
2102 save_control
= CMOS_READ(RTC_CONTROL
);
2103 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2104 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2106 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2111 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2115 CMOS_WRITE(save_control
, RTC_CONTROL
);
2116 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2117 clear_IO_APIC_pin(apic
, pin
);
2119 ioapic_write_entry(apic
, pin
, entry0
);
2123 * This code may look a bit paranoid, but it's supposed to cooperate with
2124 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2125 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2126 * fanatically on his truly buggy board.
2128 static inline void __init
check_timer(void)
2130 int apic1
, pin1
, apic2
, pin2
;
2133 unsigned long flags
;
2135 local_irq_save(flags
);
2137 ver
= apic_read(APIC_LVR
);
2138 ver
= GET_APIC_VERSION(ver
);
2141 * get/set the timer IRQ vector:
2143 disable_8259A_irq(0);
2144 vector
= assign_irq_vector(0);
2145 set_intr_gate(vector
, interrupt
[0]);
2148 * As IRQ0 is to be enabled in the 8259A, the virtual
2149 * wire has to be disabled in the local APIC. Also
2150 * timer interrupts need to be acknowledged manually in
2151 * the 8259A for the i82489DX when using the NMI
2152 * watchdog as that APIC treats NMIs as level-triggered.
2153 * The AEOI mode will finish them in the 8259A
2156 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2158 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2160 pin1
= find_isa_irq_pin(0, mp_INT
);
2161 apic1
= find_isa_irq_apic(0, mp_INT
);
2162 pin2
= ioapic_i8259
.pin
;
2163 apic2
= ioapic_i8259
.apic
;
2165 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2166 vector
, apic1
, pin1
, apic2
, pin2
);
2170 * Ok, does IRQ0 through the IOAPIC work?
2172 unmask_IO_APIC_irq(0);
2173 if (timer_irq_works()) {
2174 if (nmi_watchdog
== NMI_IO_APIC
) {
2176 enable_8259A_irq(0);
2178 if (disable_timer_pin_1
> 0)
2179 clear_IO_APIC_pin(0, pin1
);
2182 clear_IO_APIC_pin(apic1
, pin1
);
2183 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2187 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2189 printk("\n..... (found pin %d) ...", pin2
);
2191 * legacy devices should be connected to IO APIC #0
2193 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2194 enable_8259A_irq(0);
2195 if (timer_irq_works()) {
2198 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2200 add_pin_to_irq(0, apic2
, pin2
);
2201 if (nmi_watchdog
== NMI_IO_APIC
) {
2202 disable_8259A_irq(0);
2204 enable_8259A_irq(0);
2209 * Cleanup, just in case ...
2211 disable_8259A_irq(0);
2212 clear_IO_APIC_pin(apic2
, pin2
);
2214 printk(" failed.\n");
2216 if (nmi_watchdog
== NMI_IO_APIC
) {
2217 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2222 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2224 set_irq_chip_and_handler_name(0, &lapic_chip
, handle_fasteoi_irq
,
2226 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2227 enable_8259A_irq(0);
2229 if (timer_irq_works()) {
2230 printk(" works.\n");
2233 disable_8259A_irq(0);
2234 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2235 printk(" failed.\n");
2237 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2241 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2243 unlock_ExtINT_logic();
2245 if (timer_irq_works()) {
2246 printk(" works.\n");
2249 printk(" failed :(.\n");
2250 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2251 "report. Then try booting with the 'noapic' option");
2253 local_irq_restore(flags
);
2258 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2259 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2260 * Linux doesn't really care, as it's not actually used
2261 * for any interrupt handling anyway.
2263 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2265 void __init
setup_IO_APIC(void)
2269 /* Reserve all the system vectors. */
2270 for (i
= FIRST_SYSTEM_VECTOR
; i
< NR_VECTORS
; i
++)
2271 set_bit(i
, used_vectors
);
2276 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2278 io_apic_irqs
= ~PIC_IRQS
;
2280 printk("ENABLING IO-APIC IRQs\n");
2283 * Set up IO-APIC IRQ routing.
2286 setup_ioapic_ids_from_mpc();
2288 setup_IO_APIC_irqs();
2289 init_IO_APIC_traps();
2296 * Called after all the initialization is done. If we didnt find any
2297 * APIC bugs then we can allow the modify fast path
2300 static int __init
io_apic_bug_finalize(void)
2302 if(sis_apic_bug
== -1)
2307 late_initcall(io_apic_bug_finalize
);
2309 struct sysfs_ioapic_data
{
2310 struct sys_device dev
;
2311 struct IO_APIC_route_entry entry
[0];
2313 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2315 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2317 struct IO_APIC_route_entry
*entry
;
2318 struct sysfs_ioapic_data
*data
;
2321 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2322 entry
= data
->entry
;
2323 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2324 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2329 static int ioapic_resume(struct sys_device
*dev
)
2331 struct IO_APIC_route_entry
*entry
;
2332 struct sysfs_ioapic_data
*data
;
2333 unsigned long flags
;
2334 union IO_APIC_reg_00 reg_00
;
2337 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2338 entry
= data
->entry
;
2340 spin_lock_irqsave(&ioapic_lock
, flags
);
2341 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2342 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2343 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2344 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2346 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2347 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2348 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2353 static struct sysdev_class ioapic_sysdev_class
= {
2355 .suspend
= ioapic_suspend
,
2356 .resume
= ioapic_resume
,
2359 static int __init
ioapic_init_sysfs(void)
2361 struct sys_device
* dev
;
2362 int i
, size
, error
= 0;
2364 error
= sysdev_class_register(&ioapic_sysdev_class
);
2368 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2369 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2370 * sizeof(struct IO_APIC_route_entry
);
2371 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2372 if (!mp_ioapic_data
[i
]) {
2373 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2376 memset(mp_ioapic_data
[i
], 0, size
);
2377 dev
= &mp_ioapic_data
[i
]->dev
;
2379 dev
->cls
= &ioapic_sysdev_class
;
2380 error
= sysdev_register(dev
);
2382 kfree(mp_ioapic_data
[i
]);
2383 mp_ioapic_data
[i
] = NULL
;
2384 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2392 device_initcall(ioapic_init_sysfs
);
2395 * Dynamic irq allocate and deallocation
2397 int create_irq(void)
2399 /* Allocate an unused irq */
2400 int irq
, new, vector
= 0;
2401 unsigned long flags
;
2404 spin_lock_irqsave(&vector_lock
, flags
);
2405 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2406 if (platform_legacy_irq(new))
2408 if (irq_vector
[new] != 0)
2410 vector
= __assign_irq_vector(new);
2411 if (likely(vector
> 0))
2415 spin_unlock_irqrestore(&vector_lock
, flags
);
2418 set_intr_gate(vector
, interrupt
[irq
]);
2419 dynamic_irq_init(irq
);
2424 void destroy_irq(unsigned int irq
)
2426 unsigned long flags
;
2428 dynamic_irq_cleanup(irq
);
2430 spin_lock_irqsave(&vector_lock
, flags
);
2431 clear_bit(irq_vector
[irq
], used_vectors
);
2432 irq_vector
[irq
] = 0;
2433 spin_unlock_irqrestore(&vector_lock
, flags
);
2437 * MSI message composition
2439 #ifdef CONFIG_PCI_MSI
2440 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2445 vector
= assign_irq_vector(irq
);
2447 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2449 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2452 ((INT_DEST_MODE
== 0) ?
2453 MSI_ADDR_DEST_MODE_PHYSICAL
:
2454 MSI_ADDR_DEST_MODE_LOGICAL
) |
2455 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2456 MSI_ADDR_REDIRECTION_CPU
:
2457 MSI_ADDR_REDIRECTION_LOWPRI
) |
2458 MSI_ADDR_DEST_ID(dest
);
2461 MSI_DATA_TRIGGER_EDGE
|
2462 MSI_DATA_LEVEL_ASSERT
|
2463 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2464 MSI_DATA_DELIVERY_FIXED
:
2465 MSI_DATA_DELIVERY_LOWPRI
) |
2466 MSI_DATA_VECTOR(vector
);
2472 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2479 cpus_and(tmp
, mask
, cpu_online_map
);
2480 if (cpus_empty(tmp
))
2483 vector
= assign_irq_vector(irq
);
2487 dest
= cpu_mask_to_apicid(mask
);
2489 read_msi_msg(irq
, &msg
);
2491 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2492 msg
.data
|= MSI_DATA_VECTOR(vector
);
2493 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2494 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2496 write_msi_msg(irq
, &msg
);
2497 irq_desc
[irq
].affinity
= mask
;
2499 #endif /* CONFIG_SMP */
2502 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2503 * which implement the MSI or MSI-X Capability Structure.
2505 static struct irq_chip msi_chip
= {
2507 .unmask
= unmask_msi_irq
,
2508 .mask
= mask_msi_irq
,
2509 .ack
= ack_ioapic_irq
,
2511 .set_affinity
= set_msi_irq_affinity
,
2513 .retrigger
= ioapic_retrigger_irq
,
2516 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2524 ret
= msi_compose_msg(dev
, irq
, &msg
);
2530 set_irq_msi(irq
, desc
);
2531 write_msi_msg(irq
, &msg
);
2533 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2539 void arch_teardown_msi_irq(unsigned int irq
)
2544 #endif /* CONFIG_PCI_MSI */
2547 * Hypertransport interrupt support
2549 #ifdef CONFIG_HT_IRQ
2553 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2555 struct ht_irq_msg msg
;
2556 fetch_ht_irq_msg(irq
, &msg
);
2558 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2559 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2561 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2562 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2564 write_ht_irq_msg(irq
, &msg
);
2567 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2572 cpus_and(tmp
, mask
, cpu_online_map
);
2573 if (cpus_empty(tmp
))
2576 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2578 dest
= cpu_mask_to_apicid(mask
);
2580 target_ht_irq(irq
, dest
);
2581 irq_desc
[irq
].affinity
= mask
;
2585 static struct irq_chip ht_irq_chip
= {
2587 .mask
= mask_ht_irq
,
2588 .unmask
= unmask_ht_irq
,
2589 .ack
= ack_ioapic_irq
,
2591 .set_affinity
= set_ht_irq_affinity
,
2593 .retrigger
= ioapic_retrigger_irq
,
2596 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2600 vector
= assign_irq_vector(irq
);
2602 struct ht_irq_msg msg
;
2607 cpu_set(vector
>> 8, tmp
);
2608 dest
= cpu_mask_to_apicid(tmp
);
2610 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2614 HT_IRQ_LOW_DEST_ID(dest
) |
2615 HT_IRQ_LOW_VECTOR(vector
) |
2616 ((INT_DEST_MODE
== 0) ?
2617 HT_IRQ_LOW_DM_PHYSICAL
:
2618 HT_IRQ_LOW_DM_LOGICAL
) |
2619 HT_IRQ_LOW_RQEOI_EDGE
|
2620 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2621 HT_IRQ_LOW_MT_FIXED
:
2622 HT_IRQ_LOW_MT_ARBITRATED
) |
2623 HT_IRQ_LOW_IRQ_MASKED
;
2625 write_ht_irq_msg(irq
, &msg
);
2627 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2628 handle_edge_irq
, "edge");
2632 #endif /* CONFIG_HT_IRQ */
2634 /* --------------------------------------------------------------------------
2635 ACPI-based IOAPIC Configuration
2636 -------------------------------------------------------------------------- */
2640 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2642 union IO_APIC_reg_00 reg_00
;
2643 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2645 unsigned long flags
;
2649 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2650 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2651 * supports up to 16 on one shared APIC bus.
2653 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2654 * advantage of new APIC bus architecture.
2657 if (physids_empty(apic_id_map
))
2658 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2660 spin_lock_irqsave(&ioapic_lock
, flags
);
2661 reg_00
.raw
= io_apic_read(ioapic
, 0);
2662 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2664 if (apic_id
>= get_physical_broadcast()) {
2665 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2666 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2667 apic_id
= reg_00
.bits
.ID
;
2671 * Every APIC in a system must have a unique ID or we get lots of nice
2672 * 'stuck on smp_invalidate_needed IPI wait' messages.
2674 if (check_apicid_used(apic_id_map
, apic_id
)) {
2676 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2677 if (!check_apicid_used(apic_id_map
, i
))
2681 if (i
== get_physical_broadcast())
2682 panic("Max apic_id exceeded!\n");
2684 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2685 "trying %d\n", ioapic
, apic_id
, i
);
2690 tmp
= apicid_to_cpu_present(apic_id
);
2691 physids_or(apic_id_map
, apic_id_map
, tmp
);
2693 if (reg_00
.bits
.ID
!= apic_id
) {
2694 reg_00
.bits
.ID
= apic_id
;
2696 spin_lock_irqsave(&ioapic_lock
, flags
);
2697 io_apic_write(ioapic
, 0, reg_00
.raw
);
2698 reg_00
.raw
= io_apic_read(ioapic
, 0);
2699 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2702 if (reg_00
.bits
.ID
!= apic_id
) {
2703 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2708 apic_printk(APIC_VERBOSE
, KERN_INFO
2709 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2715 int __init
io_apic_get_version (int ioapic
)
2717 union IO_APIC_reg_01 reg_01
;
2718 unsigned long flags
;
2720 spin_lock_irqsave(&ioapic_lock
, flags
);
2721 reg_01
.raw
= io_apic_read(ioapic
, 1);
2722 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2724 return reg_01
.bits
.version
;
2728 int __init
io_apic_get_redir_entries (int ioapic
)
2730 union IO_APIC_reg_01 reg_01
;
2731 unsigned long flags
;
2733 spin_lock_irqsave(&ioapic_lock
, flags
);
2734 reg_01
.raw
= io_apic_read(ioapic
, 1);
2735 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2737 return reg_01
.bits
.entries
;
2741 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2743 struct IO_APIC_route_entry entry
;
2745 if (!IO_APIC_IRQ(irq
)) {
2746 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2752 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2753 * Note that we mask (disable) IRQs now -- these get enabled when the
2754 * corresponding device driver registers for this IRQ.
2757 memset(&entry
,0,sizeof(entry
));
2759 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2760 entry
.dest_mode
= INT_DEST_MODE
;
2761 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2762 entry
.trigger
= edge_level
;
2763 entry
.polarity
= active_high_low
;
2767 * IRQs < 16 are already in the irq_2_pin[] map
2770 add_pin_to_irq(irq
, ioapic
, pin
);
2772 entry
.vector
= assign_irq_vector(irq
);
2774 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2775 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2776 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2777 edge_level
, active_high_low
);
2779 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2781 if (!ioapic
&& (irq
< 16))
2782 disable_8259A_irq(irq
);
2784 ioapic_write_entry(ioapic
, pin
, entry
);
2789 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2793 if (skip_ioapic_setup
)
2796 for (i
= 0; i
< mp_irq_entries
; i
++)
2797 if (mp_irqs
[i
].mpc_irqtype
== mp_INT
&&
2798 mp_irqs
[i
].mpc_srcbusirq
== bus_irq
)
2800 if (i
>= mp_irq_entries
)
2803 *trigger
= irq_trigger(i
);
2804 *polarity
= irq_polarity(i
);
2808 #endif /* CONFIG_ACPI */
2810 static int __init
parse_disable_timer_pin_1(char *arg
)
2812 disable_timer_pin_1
= 1;
2815 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2817 static int __init
parse_enable_timer_pin_1(char *arg
)
2819 disable_timer_pin_1
= -1;
2822 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2824 static int __init
parse_noapic(char *arg
)
2826 /* disable IO-APIC */
2827 disable_ioapic_setup();
2830 early_param("noapic", parse_noapic
);