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1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/nmi.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
51
52 #include <mach_ipi.h>
53 #include <mach_apic.h>
54
55 struct irq_cfg {
56 cpumask_t domain;
57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
59 u8 vector;
60 u8 move_in_progress : 1;
61 };
62
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
81 };
82
83 static int assign_irq_vector(int irq, cpumask_t mask);
84
85 #define __apicdebuginit __init
86
87 int sis_apic_bug; /* not actually supported, dummy for compile */
88
89 static int no_timer_check;
90
91 static int disable_timer_pin_1 __initdata;
92
93 int timer_over_8254 __initdata = 1;
94
95 /* Where if anywhere is the i8259 connect in external int mode */
96 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
97
98 static DEFINE_SPINLOCK(ioapic_lock);
99 DEFINE_SPINLOCK(vector_lock);
100
101 /*
102 * # of IRQ routing registers
103 */
104 int nr_ioapic_registers[MAX_IO_APICS];
105
106 /*
107 * Rough estimation of how many shared IRQs there are, can
108 * be changed anytime.
109 */
110 #define MAX_PLUS_SHARED_IRQS NR_IRQS
111 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
112
113 /*
114 * This is performance-critical, we want to do it O(1)
115 *
116 * the indexing order of this array favors 1:1 mappings
117 * between pins and IRQs.
118 */
119
120 static struct irq_pin_list {
121 short apic, pin, next;
122 } irq_2_pin[PIN_MAP_SIZE];
123
124 struct io_apic {
125 unsigned int index;
126 unsigned int unused[3];
127 unsigned int data;
128 };
129
130 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
131 {
132 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
133 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
134 }
135
136 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
137 {
138 struct io_apic __iomem *io_apic = io_apic_base(apic);
139 writel(reg, &io_apic->index);
140 return readl(&io_apic->data);
141 }
142
143 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
144 {
145 struct io_apic __iomem *io_apic = io_apic_base(apic);
146 writel(reg, &io_apic->index);
147 writel(value, &io_apic->data);
148 }
149
150 /*
151 * Re-write a value: to be used for read-modify-write
152 * cycles where the read already set up the index register.
153 */
154 static inline void io_apic_modify(unsigned int apic, unsigned int value)
155 {
156 struct io_apic __iomem *io_apic = io_apic_base(apic);
157 writel(value, &io_apic->data);
158 }
159
160 static int io_apic_level_ack_pending(unsigned int irq)
161 {
162 struct irq_pin_list *entry;
163 unsigned long flags;
164 int pending = 0;
165
166 spin_lock_irqsave(&ioapic_lock, flags);
167 entry = irq_2_pin + irq;
168 for (;;) {
169 unsigned int reg;
170 int pin;
171
172 pin = entry->pin;
173 if (pin == -1)
174 break;
175 reg = io_apic_read(entry->apic, 0x10 + pin*2);
176 /* Is the remote IRR bit set? */
177 pending |= (reg >> 14) & 1;
178 if (!entry->next)
179 break;
180 entry = irq_2_pin + entry->next;
181 }
182 spin_unlock_irqrestore(&ioapic_lock, flags);
183 return pending;
184 }
185
186 /*
187 * Synchronize the IO-APIC and the CPU by doing
188 * a dummy read from the IO-APIC
189 */
190 static inline void io_apic_sync(unsigned int apic)
191 {
192 struct io_apic __iomem *io_apic = io_apic_base(apic);
193 readl(&io_apic->data);
194 }
195
196 #define __DO_ACTION(R, ACTION, FINAL) \
197 \
198 { \
199 int pin; \
200 struct irq_pin_list *entry = irq_2_pin + irq; \
201 \
202 BUG_ON(irq >= NR_IRQS); \
203 for (;;) { \
204 unsigned int reg; \
205 pin = entry->pin; \
206 if (pin == -1) \
207 break; \
208 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
209 reg ACTION; \
210 io_apic_modify(entry->apic, reg); \
211 FINAL; \
212 if (!entry->next) \
213 break; \
214 entry = irq_2_pin + entry->next; \
215 } \
216 }
217
218 union entry_union {
219 struct { u32 w1, w2; };
220 struct IO_APIC_route_entry entry;
221 };
222
223 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
224 {
225 union entry_union eu;
226 unsigned long flags;
227 spin_lock_irqsave(&ioapic_lock, flags);
228 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
229 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
230 spin_unlock_irqrestore(&ioapic_lock, flags);
231 return eu.entry;
232 }
233
234 /*
235 * When we write a new IO APIC routing entry, we need to write the high
236 * word first! If the mask bit in the low word is clear, we will enable
237 * the interrupt, and we need to make sure the entry is fully populated
238 * before that happens.
239 */
240 static void
241 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
242 {
243 union entry_union eu;
244 eu.entry = e;
245 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
246 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
247 }
248
249 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
250 {
251 unsigned long flags;
252 spin_lock_irqsave(&ioapic_lock, flags);
253 __ioapic_write_entry(apic, pin, e);
254 spin_unlock_irqrestore(&ioapic_lock, flags);
255 }
256
257 /*
258 * When we mask an IO APIC routing entry, we need to write the low
259 * word first, in order to set the mask bit before we change the
260 * high bits!
261 */
262 static void ioapic_mask_entry(int apic, int pin)
263 {
264 unsigned long flags;
265 union entry_union eu = { .entry.mask = 1 };
266
267 spin_lock_irqsave(&ioapic_lock, flags);
268 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
269 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
270 spin_unlock_irqrestore(&ioapic_lock, flags);
271 }
272
273 #ifdef CONFIG_SMP
274 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
275 {
276 int apic, pin;
277 struct irq_pin_list *entry = irq_2_pin + irq;
278
279 BUG_ON(irq >= NR_IRQS);
280 for (;;) {
281 unsigned int reg;
282 apic = entry->apic;
283 pin = entry->pin;
284 if (pin == -1)
285 break;
286 io_apic_write(apic, 0x11 + pin*2, dest);
287 reg = io_apic_read(apic, 0x10 + pin*2);
288 reg &= ~0x000000ff;
289 reg |= vector;
290 io_apic_modify(apic, reg);
291 if (!entry->next)
292 break;
293 entry = irq_2_pin + entry->next;
294 }
295 }
296
297 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
298 {
299 struct irq_cfg *cfg = irq_cfg + irq;
300 unsigned long flags;
301 unsigned int dest;
302 cpumask_t tmp;
303
304 cpus_and(tmp, mask, cpu_online_map);
305 if (cpus_empty(tmp))
306 return;
307
308 if (assign_irq_vector(irq, mask))
309 return;
310
311 cpus_and(tmp, cfg->domain, mask);
312 dest = cpu_mask_to_apicid(tmp);
313
314 /*
315 * Only the high 8 bits are valid.
316 */
317 dest = SET_APIC_LOGICAL_ID(dest);
318
319 spin_lock_irqsave(&ioapic_lock, flags);
320 __target_IO_APIC_irq(irq, dest, cfg->vector);
321 irq_desc[irq].affinity = mask;
322 spin_unlock_irqrestore(&ioapic_lock, flags);
323 }
324 #endif
325
326 /*
327 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
328 * shared ISA-space IRQs, so we have to support them. We are super
329 * fast in the common case, and fast for shared ISA-space IRQs.
330 */
331 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
332 {
333 static int first_free_entry = NR_IRQS;
334 struct irq_pin_list *entry = irq_2_pin + irq;
335
336 BUG_ON(irq >= NR_IRQS);
337 while (entry->next)
338 entry = irq_2_pin + entry->next;
339
340 if (entry->pin != -1) {
341 entry->next = first_free_entry;
342 entry = irq_2_pin + entry->next;
343 if (++first_free_entry >= PIN_MAP_SIZE)
344 panic("io_apic.c: ran out of irq_2_pin entries!");
345 }
346 entry->apic = apic;
347 entry->pin = pin;
348 }
349
350
351 #define DO_ACTION(name,R,ACTION, FINAL) \
352 \
353 static void name##_IO_APIC_irq (unsigned int irq) \
354 __DO_ACTION(R, ACTION, FINAL)
355
356 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
357 /* mask = 1 */
358 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
359 /* mask = 0 */
360
361 static void mask_IO_APIC_irq (unsigned int irq)
362 {
363 unsigned long flags;
364
365 spin_lock_irqsave(&ioapic_lock, flags);
366 __mask_IO_APIC_irq(irq);
367 spin_unlock_irqrestore(&ioapic_lock, flags);
368 }
369
370 static void unmask_IO_APIC_irq (unsigned int irq)
371 {
372 unsigned long flags;
373
374 spin_lock_irqsave(&ioapic_lock, flags);
375 __unmask_IO_APIC_irq(irq);
376 spin_unlock_irqrestore(&ioapic_lock, flags);
377 }
378
379 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
380 {
381 struct IO_APIC_route_entry entry;
382
383 /* Check delivery_mode to be sure we're not clearing an SMI pin */
384 entry = ioapic_read_entry(apic, pin);
385 if (entry.delivery_mode == dest_SMI)
386 return;
387 /*
388 * Disable it in the IO-APIC irq-routing table:
389 */
390 ioapic_mask_entry(apic, pin);
391 }
392
393 static void clear_IO_APIC (void)
394 {
395 int apic, pin;
396
397 for (apic = 0; apic < nr_ioapics; apic++)
398 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
399 clear_IO_APIC_pin(apic, pin);
400 }
401
402 int skip_ioapic_setup;
403 int ioapic_force;
404
405 static int __init parse_noapic(char *str)
406 {
407 disable_ioapic_setup();
408 return 0;
409 }
410 early_param("noapic", parse_noapic);
411
412 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
413 static int __init disable_timer_pin_setup(char *arg)
414 {
415 disable_timer_pin_1 = 1;
416 return 1;
417 }
418 __setup("disable_timer_pin_1", disable_timer_pin_setup);
419
420 static int __init setup_disable_8254_timer(char *s)
421 {
422 timer_over_8254 = -1;
423 return 1;
424 }
425 static int __init setup_enable_8254_timer(char *s)
426 {
427 timer_over_8254 = 2;
428 return 1;
429 }
430
431 __setup("disable_8254_timer", setup_disable_8254_timer);
432 __setup("enable_8254_timer", setup_enable_8254_timer);
433
434
435 /*
436 * Find the IRQ entry number of a certain pin.
437 */
438 static int find_irq_entry(int apic, int pin, int type)
439 {
440 int i;
441
442 for (i = 0; i < mp_irq_entries; i++)
443 if (mp_irqs[i].mpc_irqtype == type &&
444 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
445 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
446 mp_irqs[i].mpc_dstirq == pin)
447 return i;
448
449 return -1;
450 }
451
452 /*
453 * Find the pin to which IRQ[irq] (ISA) is connected
454 */
455 static int __init find_isa_irq_pin(int irq, int type)
456 {
457 int i;
458
459 for (i = 0; i < mp_irq_entries; i++) {
460 int lbus = mp_irqs[i].mpc_srcbus;
461
462 if (test_bit(lbus, mp_bus_not_pci) &&
463 (mp_irqs[i].mpc_irqtype == type) &&
464 (mp_irqs[i].mpc_srcbusirq == irq))
465
466 return mp_irqs[i].mpc_dstirq;
467 }
468 return -1;
469 }
470
471 static int __init find_isa_irq_apic(int irq, int type)
472 {
473 int i;
474
475 for (i = 0; i < mp_irq_entries; i++) {
476 int lbus = mp_irqs[i].mpc_srcbus;
477
478 if (test_bit(lbus, mp_bus_not_pci) &&
479 (mp_irqs[i].mpc_irqtype == type) &&
480 (mp_irqs[i].mpc_srcbusirq == irq))
481 break;
482 }
483 if (i < mp_irq_entries) {
484 int apic;
485 for(apic = 0; apic < nr_ioapics; apic++) {
486 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
487 return apic;
488 }
489 }
490
491 return -1;
492 }
493
494 /*
495 * Find a specific PCI IRQ entry.
496 * Not an __init, possibly needed by modules
497 */
498 static int pin_2_irq(int idx, int apic, int pin);
499
500 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
501 {
502 int apic, i, best_guess = -1;
503
504 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
505 bus, slot, pin);
506 if (mp_bus_id_to_pci_bus[bus] == -1) {
507 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
508 return -1;
509 }
510 for (i = 0; i < mp_irq_entries; i++) {
511 int lbus = mp_irqs[i].mpc_srcbus;
512
513 for (apic = 0; apic < nr_ioapics; apic++)
514 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
515 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
516 break;
517
518 if (!test_bit(lbus, mp_bus_not_pci) &&
519 !mp_irqs[i].mpc_irqtype &&
520 (bus == lbus) &&
521 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
522 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
523
524 if (!(apic || IO_APIC_IRQ(irq)))
525 continue;
526
527 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
528 return irq;
529 /*
530 * Use the first all-but-pin matching entry as a
531 * best-guess fuzzy result for broken mptables.
532 */
533 if (best_guess < 0)
534 best_guess = irq;
535 }
536 }
537 BUG_ON(best_guess >= NR_IRQS);
538 return best_guess;
539 }
540
541 /* ISA interrupts are always polarity zero edge triggered,
542 * when listed as conforming in the MP table. */
543
544 #define default_ISA_trigger(idx) (0)
545 #define default_ISA_polarity(idx) (0)
546
547 /* PCI interrupts are always polarity one level triggered,
548 * when listed as conforming in the MP table. */
549
550 #define default_PCI_trigger(idx) (1)
551 #define default_PCI_polarity(idx) (1)
552
553 static int MPBIOS_polarity(int idx)
554 {
555 int bus = mp_irqs[idx].mpc_srcbus;
556 int polarity;
557
558 /*
559 * Determine IRQ line polarity (high active or low active):
560 */
561 switch (mp_irqs[idx].mpc_irqflag & 3)
562 {
563 case 0: /* conforms, ie. bus-type dependent polarity */
564 if (test_bit(bus, mp_bus_not_pci))
565 polarity = default_ISA_polarity(idx);
566 else
567 polarity = default_PCI_polarity(idx);
568 break;
569 case 1: /* high active */
570 {
571 polarity = 0;
572 break;
573 }
574 case 2: /* reserved */
575 {
576 printk(KERN_WARNING "broken BIOS!!\n");
577 polarity = 1;
578 break;
579 }
580 case 3: /* low active */
581 {
582 polarity = 1;
583 break;
584 }
585 default: /* invalid */
586 {
587 printk(KERN_WARNING "broken BIOS!!\n");
588 polarity = 1;
589 break;
590 }
591 }
592 return polarity;
593 }
594
595 static int MPBIOS_trigger(int idx)
596 {
597 int bus = mp_irqs[idx].mpc_srcbus;
598 int trigger;
599
600 /*
601 * Determine IRQ trigger mode (edge or level sensitive):
602 */
603 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
604 {
605 case 0: /* conforms, ie. bus-type dependent */
606 if (test_bit(bus, mp_bus_not_pci))
607 trigger = default_ISA_trigger(idx);
608 else
609 trigger = default_PCI_trigger(idx);
610 break;
611 case 1: /* edge */
612 {
613 trigger = 0;
614 break;
615 }
616 case 2: /* reserved */
617 {
618 printk(KERN_WARNING "broken BIOS!!\n");
619 trigger = 1;
620 break;
621 }
622 case 3: /* level */
623 {
624 trigger = 1;
625 break;
626 }
627 default: /* invalid */
628 {
629 printk(KERN_WARNING "broken BIOS!!\n");
630 trigger = 0;
631 break;
632 }
633 }
634 return trigger;
635 }
636
637 static inline int irq_polarity(int idx)
638 {
639 return MPBIOS_polarity(idx);
640 }
641
642 static inline int irq_trigger(int idx)
643 {
644 return MPBIOS_trigger(idx);
645 }
646
647 static int pin_2_irq(int idx, int apic, int pin)
648 {
649 int irq, i;
650 int bus = mp_irqs[idx].mpc_srcbus;
651
652 /*
653 * Debugging check, we are in big trouble if this message pops up!
654 */
655 if (mp_irqs[idx].mpc_dstirq != pin)
656 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
657
658 if (test_bit(bus, mp_bus_not_pci)) {
659 irq = mp_irqs[idx].mpc_srcbusirq;
660 } else {
661 /*
662 * PCI IRQs are mapped in order
663 */
664 i = irq = 0;
665 while (i < apic)
666 irq += nr_ioapic_registers[i++];
667 irq += pin;
668 }
669 BUG_ON(irq >= NR_IRQS);
670 return irq;
671 }
672
673 static int __assign_irq_vector(int irq, cpumask_t mask)
674 {
675 /*
676 * NOTE! The local APIC isn't very good at handling
677 * multiple interrupts at the same interrupt level.
678 * As the interrupt level is determined by taking the
679 * vector number and shifting that right by 4, we
680 * want to spread these out a bit so that they don't
681 * all fall in the same interrupt level.
682 *
683 * Also, we've got to be careful not to trash gate
684 * 0x80, because int 0x80 is hm, kind of importantish. ;)
685 */
686 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
687 unsigned int old_vector;
688 int cpu;
689 struct irq_cfg *cfg;
690
691 BUG_ON((unsigned)irq >= NR_IRQS);
692 cfg = &irq_cfg[irq];
693
694 /* Only try and allocate irqs on cpus that are present */
695 cpus_and(mask, mask, cpu_online_map);
696
697 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
698 return -EBUSY;
699
700 old_vector = cfg->vector;
701 if (old_vector) {
702 cpumask_t tmp;
703 cpus_and(tmp, cfg->domain, mask);
704 if (!cpus_empty(tmp))
705 return 0;
706 }
707
708 for_each_cpu_mask(cpu, mask) {
709 cpumask_t domain, new_mask;
710 int new_cpu;
711 int vector, offset;
712
713 domain = vector_allocation_domain(cpu);
714 cpus_and(new_mask, domain, cpu_online_map);
715
716 vector = current_vector;
717 offset = current_offset;
718 next:
719 vector += 8;
720 if (vector >= FIRST_SYSTEM_VECTOR) {
721 /* If we run out of vectors on large boxen, must share them. */
722 offset = (offset + 1) % 8;
723 vector = FIRST_DEVICE_VECTOR + offset;
724 }
725 if (unlikely(current_vector == vector))
726 continue;
727 if (vector == IA32_SYSCALL_VECTOR)
728 goto next;
729 for_each_cpu_mask(new_cpu, new_mask)
730 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
731 goto next;
732 /* Found one! */
733 current_vector = vector;
734 current_offset = offset;
735 if (old_vector) {
736 cfg->move_in_progress = 1;
737 cfg->old_domain = cfg->domain;
738 }
739 for_each_cpu_mask(new_cpu, new_mask)
740 per_cpu(vector_irq, new_cpu)[vector] = irq;
741 cfg->vector = vector;
742 cfg->domain = domain;
743 return 0;
744 }
745 return -ENOSPC;
746 }
747
748 static int assign_irq_vector(int irq, cpumask_t mask)
749 {
750 int err;
751 unsigned long flags;
752
753 spin_lock_irqsave(&vector_lock, flags);
754 err = __assign_irq_vector(irq, mask);
755 spin_unlock_irqrestore(&vector_lock, flags);
756 return err;
757 }
758
759 static void __clear_irq_vector(int irq)
760 {
761 struct irq_cfg *cfg;
762 cpumask_t mask;
763 int cpu, vector;
764
765 BUG_ON((unsigned)irq >= NR_IRQS);
766 cfg = &irq_cfg[irq];
767 BUG_ON(!cfg->vector);
768
769 vector = cfg->vector;
770 cpus_and(mask, cfg->domain, cpu_online_map);
771 for_each_cpu_mask(cpu, mask)
772 per_cpu(vector_irq, cpu)[vector] = -1;
773
774 cfg->vector = 0;
775 cfg->domain = CPU_MASK_NONE;
776 }
777
778 void __setup_vector_irq(int cpu)
779 {
780 /* Initialize vector_irq on a new cpu */
781 /* This function must be called with vector_lock held */
782 int irq, vector;
783
784 /* Mark the inuse vectors */
785 for (irq = 0; irq < NR_IRQS; ++irq) {
786 if (!cpu_isset(cpu, irq_cfg[irq].domain))
787 continue;
788 vector = irq_cfg[irq].vector;
789 per_cpu(vector_irq, cpu)[vector] = irq;
790 }
791 /* Mark the free vectors */
792 for (vector = 0; vector < NR_VECTORS; ++vector) {
793 irq = per_cpu(vector_irq, cpu)[vector];
794 if (irq < 0)
795 continue;
796 if (!cpu_isset(cpu, irq_cfg[irq].domain))
797 per_cpu(vector_irq, cpu)[vector] = -1;
798 }
799 }
800
801
802 static struct irq_chip ioapic_chip;
803
804 static void ioapic_register_intr(int irq, unsigned long trigger)
805 {
806 if (trigger) {
807 irq_desc[irq].status |= IRQ_LEVEL;
808 set_irq_chip_and_handler_name(irq, &ioapic_chip,
809 handle_fasteoi_irq, "fasteoi");
810 } else {
811 irq_desc[irq].status &= ~IRQ_LEVEL;
812 set_irq_chip_and_handler_name(irq, &ioapic_chip,
813 handle_edge_irq, "edge");
814 }
815 }
816
817 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
818 int trigger, int polarity)
819 {
820 struct irq_cfg *cfg = irq_cfg + irq;
821 struct IO_APIC_route_entry entry;
822 cpumask_t mask;
823
824 if (!IO_APIC_IRQ(irq))
825 return;
826
827 mask = TARGET_CPUS;
828 if (assign_irq_vector(irq, mask))
829 return;
830
831 cpus_and(mask, cfg->domain, mask);
832
833 apic_printk(APIC_VERBOSE,KERN_DEBUG
834 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
835 "IRQ %d Mode:%i Active:%i)\n",
836 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
837 irq, trigger, polarity);
838
839 /*
840 * add it to the IO-APIC irq-routing table:
841 */
842 memset(&entry,0,sizeof(entry));
843
844 entry.delivery_mode = INT_DELIVERY_MODE;
845 entry.dest_mode = INT_DEST_MODE;
846 entry.dest = cpu_mask_to_apicid(mask);
847 entry.mask = 0; /* enable IRQ */
848 entry.trigger = trigger;
849 entry.polarity = polarity;
850 entry.vector = cfg->vector;
851
852 /* Mask level triggered irqs.
853 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
854 */
855 if (trigger)
856 entry.mask = 1;
857
858 ioapic_register_intr(irq, trigger);
859 if (irq < 16)
860 disable_8259A_irq(irq);
861
862 ioapic_write_entry(apic, pin, entry);
863 }
864
865 static void __init setup_IO_APIC_irqs(void)
866 {
867 int apic, pin, idx, irq, first_notcon = 1;
868
869 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
870
871 for (apic = 0; apic < nr_ioapics; apic++) {
872 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
873
874 idx = find_irq_entry(apic,pin,mp_INT);
875 if (idx == -1) {
876 if (first_notcon) {
877 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
878 first_notcon = 0;
879 } else
880 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
881 continue;
882 }
883 if (!first_notcon) {
884 apic_printk(APIC_VERBOSE, " not connected.\n");
885 first_notcon = 1;
886 }
887
888 irq = pin_2_irq(idx, apic, pin);
889 add_pin_to_irq(irq, apic, pin);
890
891 setup_IO_APIC_irq(apic, pin, irq,
892 irq_trigger(idx), irq_polarity(idx));
893 }
894 }
895
896 if (!first_notcon)
897 apic_printk(APIC_VERBOSE, " not connected.\n");
898 }
899
900 /*
901 * Set up the 8259A-master output pin as broadcast to all
902 * CPUs.
903 */
904 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
905 {
906 struct IO_APIC_route_entry entry;
907 unsigned long flags;
908
909 memset(&entry,0,sizeof(entry));
910
911 disable_8259A_irq(0);
912
913 /* mask LVT0 */
914 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
915
916 /*
917 * We use logical delivery to get the timer IRQ
918 * to the first CPU.
919 */
920 entry.dest_mode = INT_DEST_MODE;
921 entry.mask = 0; /* unmask IRQ now */
922 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
923 entry.delivery_mode = INT_DELIVERY_MODE;
924 entry.polarity = 0;
925 entry.trigger = 0;
926 entry.vector = vector;
927
928 /*
929 * The timer IRQ doesn't have to know that behind the
930 * scene we have a 8259A-master in AEOI mode ...
931 */
932 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
933
934 /*
935 * Add it to the IO-APIC irq-routing table:
936 */
937 spin_lock_irqsave(&ioapic_lock, flags);
938 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
939 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
940 spin_unlock_irqrestore(&ioapic_lock, flags);
941
942 enable_8259A_irq(0);
943 }
944
945 void __apicdebuginit print_IO_APIC(void)
946 {
947 int apic, i;
948 union IO_APIC_reg_00 reg_00;
949 union IO_APIC_reg_01 reg_01;
950 union IO_APIC_reg_02 reg_02;
951 unsigned long flags;
952
953 if (apic_verbosity == APIC_QUIET)
954 return;
955
956 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
957 for (i = 0; i < nr_ioapics; i++)
958 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
959 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
960
961 /*
962 * We are a bit conservative about what we expect. We have to
963 * know about every hardware change ASAP.
964 */
965 printk(KERN_INFO "testing the IO APIC.......................\n");
966
967 for (apic = 0; apic < nr_ioapics; apic++) {
968
969 spin_lock_irqsave(&ioapic_lock, flags);
970 reg_00.raw = io_apic_read(apic, 0);
971 reg_01.raw = io_apic_read(apic, 1);
972 if (reg_01.bits.version >= 0x10)
973 reg_02.raw = io_apic_read(apic, 2);
974 spin_unlock_irqrestore(&ioapic_lock, flags);
975
976 printk("\n");
977 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
978 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
979 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
980
981 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
982 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
983
984 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
985 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
986
987 if (reg_01.bits.version >= 0x10) {
988 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
989 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
990 }
991
992 printk(KERN_DEBUG ".... IRQ redirection table:\n");
993
994 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
995 " Stat Dmod Deli Vect: \n");
996
997 for (i = 0; i <= reg_01.bits.entries; i++) {
998 struct IO_APIC_route_entry entry;
999
1000 entry = ioapic_read_entry(apic, i);
1001
1002 printk(KERN_DEBUG " %02x %03X ",
1003 i,
1004 entry.dest
1005 );
1006
1007 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1008 entry.mask,
1009 entry.trigger,
1010 entry.irr,
1011 entry.polarity,
1012 entry.delivery_status,
1013 entry.dest_mode,
1014 entry.delivery_mode,
1015 entry.vector
1016 );
1017 }
1018 }
1019 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1020 for (i = 0; i < NR_IRQS; i++) {
1021 struct irq_pin_list *entry = irq_2_pin + i;
1022 if (entry->pin < 0)
1023 continue;
1024 printk(KERN_DEBUG "IRQ%d ", i);
1025 for (;;) {
1026 printk("-> %d:%d", entry->apic, entry->pin);
1027 if (!entry->next)
1028 break;
1029 entry = irq_2_pin + entry->next;
1030 }
1031 printk("\n");
1032 }
1033
1034 printk(KERN_INFO ".................................... done.\n");
1035
1036 return;
1037 }
1038
1039 #if 0
1040
1041 static __apicdebuginit void print_APIC_bitfield (int base)
1042 {
1043 unsigned int v;
1044 int i, j;
1045
1046 if (apic_verbosity == APIC_QUIET)
1047 return;
1048
1049 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1050 for (i = 0; i < 8; i++) {
1051 v = apic_read(base + i*0x10);
1052 for (j = 0; j < 32; j++) {
1053 if (v & (1<<j))
1054 printk("1");
1055 else
1056 printk("0");
1057 }
1058 printk("\n");
1059 }
1060 }
1061
1062 void __apicdebuginit print_local_APIC(void * dummy)
1063 {
1064 unsigned int v, ver, maxlvt;
1065
1066 if (apic_verbosity == APIC_QUIET)
1067 return;
1068
1069 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1070 smp_processor_id(), hard_smp_processor_id());
1071 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1072 v = apic_read(APIC_LVR);
1073 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1074 ver = GET_APIC_VERSION(v);
1075 maxlvt = lapic_get_maxlvt();
1076
1077 v = apic_read(APIC_TASKPRI);
1078 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1079
1080 v = apic_read(APIC_ARBPRI);
1081 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1082 v & APIC_ARBPRI_MASK);
1083 v = apic_read(APIC_PROCPRI);
1084 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1085
1086 v = apic_read(APIC_EOI);
1087 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1088 v = apic_read(APIC_RRR);
1089 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1090 v = apic_read(APIC_LDR);
1091 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1092 v = apic_read(APIC_DFR);
1093 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1094 v = apic_read(APIC_SPIV);
1095 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1096
1097 printk(KERN_DEBUG "... APIC ISR field:\n");
1098 print_APIC_bitfield(APIC_ISR);
1099 printk(KERN_DEBUG "... APIC TMR field:\n");
1100 print_APIC_bitfield(APIC_TMR);
1101 printk(KERN_DEBUG "... APIC IRR field:\n");
1102 print_APIC_bitfield(APIC_IRR);
1103
1104 v = apic_read(APIC_ESR);
1105 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1106
1107 v = apic_read(APIC_ICR);
1108 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1109 v = apic_read(APIC_ICR2);
1110 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1111
1112 v = apic_read(APIC_LVTT);
1113 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1114
1115 if (maxlvt > 3) { /* PC is LVT#4. */
1116 v = apic_read(APIC_LVTPC);
1117 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1118 }
1119 v = apic_read(APIC_LVT0);
1120 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1121 v = apic_read(APIC_LVT1);
1122 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1123
1124 if (maxlvt > 2) { /* ERR is LVT#3. */
1125 v = apic_read(APIC_LVTERR);
1126 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1127 }
1128
1129 v = apic_read(APIC_TMICT);
1130 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1131 v = apic_read(APIC_TMCCT);
1132 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1133 v = apic_read(APIC_TDCR);
1134 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1135 printk("\n");
1136 }
1137
1138 void print_all_local_APICs (void)
1139 {
1140 on_each_cpu(print_local_APIC, NULL, 1, 1);
1141 }
1142
1143 void __apicdebuginit print_PIC(void)
1144 {
1145 unsigned int v;
1146 unsigned long flags;
1147
1148 if (apic_verbosity == APIC_QUIET)
1149 return;
1150
1151 printk(KERN_DEBUG "\nprinting PIC contents\n");
1152
1153 spin_lock_irqsave(&i8259A_lock, flags);
1154
1155 v = inb(0xa1) << 8 | inb(0x21);
1156 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1157
1158 v = inb(0xa0) << 8 | inb(0x20);
1159 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1160
1161 outb(0x0b,0xa0);
1162 outb(0x0b,0x20);
1163 v = inb(0xa0) << 8 | inb(0x20);
1164 outb(0x0a,0xa0);
1165 outb(0x0a,0x20);
1166
1167 spin_unlock_irqrestore(&i8259A_lock, flags);
1168
1169 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1170
1171 v = inb(0x4d1) << 8 | inb(0x4d0);
1172 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1173 }
1174
1175 #endif /* 0 */
1176
1177 void __init enable_IO_APIC(void)
1178 {
1179 union IO_APIC_reg_01 reg_01;
1180 int i8259_apic, i8259_pin;
1181 int i, apic;
1182 unsigned long flags;
1183
1184 for (i = 0; i < PIN_MAP_SIZE; i++) {
1185 irq_2_pin[i].pin = -1;
1186 irq_2_pin[i].next = 0;
1187 }
1188
1189 /*
1190 * The number of IO-APIC IRQ registers (== #pins):
1191 */
1192 for (apic = 0; apic < nr_ioapics; apic++) {
1193 spin_lock_irqsave(&ioapic_lock, flags);
1194 reg_01.raw = io_apic_read(apic, 1);
1195 spin_unlock_irqrestore(&ioapic_lock, flags);
1196 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1197 }
1198 for(apic = 0; apic < nr_ioapics; apic++) {
1199 int pin;
1200 /* See if any of the pins is in ExtINT mode */
1201 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1202 struct IO_APIC_route_entry entry;
1203 entry = ioapic_read_entry(apic, pin);
1204
1205 /* If the interrupt line is enabled and in ExtInt mode
1206 * I have found the pin where the i8259 is connected.
1207 */
1208 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1209 ioapic_i8259.apic = apic;
1210 ioapic_i8259.pin = pin;
1211 goto found_i8259;
1212 }
1213 }
1214 }
1215 found_i8259:
1216 /* Look to see what if the MP table has reported the ExtINT */
1217 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1218 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1219 /* Trust the MP table if nothing is setup in the hardware */
1220 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1221 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1222 ioapic_i8259.pin = i8259_pin;
1223 ioapic_i8259.apic = i8259_apic;
1224 }
1225 /* Complain if the MP table and the hardware disagree */
1226 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1227 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1228 {
1229 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1230 }
1231
1232 /*
1233 * Do not trust the IO-APIC being empty at bootup
1234 */
1235 clear_IO_APIC();
1236 }
1237
1238 /*
1239 * Not an __init, needed by the reboot code
1240 */
1241 void disable_IO_APIC(void)
1242 {
1243 /*
1244 * Clear the IO-APIC before rebooting:
1245 */
1246 clear_IO_APIC();
1247
1248 /*
1249 * If the i8259 is routed through an IOAPIC
1250 * Put that IOAPIC in virtual wire mode
1251 * so legacy interrupts can be delivered.
1252 */
1253 if (ioapic_i8259.pin != -1) {
1254 struct IO_APIC_route_entry entry;
1255
1256 memset(&entry, 0, sizeof(entry));
1257 entry.mask = 0; /* Enabled */
1258 entry.trigger = 0; /* Edge */
1259 entry.irr = 0;
1260 entry.polarity = 0; /* High */
1261 entry.delivery_status = 0;
1262 entry.dest_mode = 0; /* Physical */
1263 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1264 entry.vector = 0;
1265 entry.dest = GET_APIC_ID(read_apic_id());
1266
1267 /*
1268 * Add it to the IO-APIC irq-routing table:
1269 */
1270 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1271 }
1272
1273 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1274 }
1275
1276 /*
1277 * There is a nasty bug in some older SMP boards, their mptable lies
1278 * about the timer IRQ. We do the following to work around the situation:
1279 *
1280 * - timer IRQ defaults to IO-APIC IRQ
1281 * - if this function detects that timer IRQs are defunct, then we fall
1282 * back to ISA timer IRQs
1283 */
1284 static int __init timer_irq_works(void)
1285 {
1286 unsigned long t1 = jiffies;
1287 unsigned long flags;
1288
1289 local_save_flags(flags);
1290 local_irq_enable();
1291 /* Let ten ticks pass... */
1292 mdelay((10 * 1000) / HZ);
1293 local_irq_restore(flags);
1294
1295 /*
1296 * Expect a few ticks at least, to be sure some possible
1297 * glue logic does not lock up after one or two first
1298 * ticks in a non-ExtINT mode. Also the local APIC
1299 * might have cached one ExtINT interrupt. Finally, at
1300 * least one tick may be lost due to delays.
1301 */
1302
1303 /* jiffies wrap? */
1304 if (time_after(jiffies, t1 + 4))
1305 return 1;
1306 return 0;
1307 }
1308
1309 /*
1310 * In the SMP+IOAPIC case it might happen that there are an unspecified
1311 * number of pending IRQ events unhandled. These cases are very rare,
1312 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1313 * better to do it this way as thus we do not have to be aware of
1314 * 'pending' interrupts in the IRQ path, except at this point.
1315 */
1316 /*
1317 * Edge triggered needs to resend any interrupt
1318 * that was delayed but this is now handled in the device
1319 * independent code.
1320 */
1321
1322 /*
1323 * Starting up a edge-triggered IO-APIC interrupt is
1324 * nasty - we need to make sure that we get the edge.
1325 * If it is already asserted for some reason, we need
1326 * return 1 to indicate that is was pending.
1327 *
1328 * This is not complete - we should be able to fake
1329 * an edge even if it isn't on the 8259A...
1330 */
1331
1332 static unsigned int startup_ioapic_irq(unsigned int irq)
1333 {
1334 int was_pending = 0;
1335 unsigned long flags;
1336
1337 spin_lock_irqsave(&ioapic_lock, flags);
1338 if (irq < 16) {
1339 disable_8259A_irq(irq);
1340 if (i8259A_irq_pending(irq))
1341 was_pending = 1;
1342 }
1343 __unmask_IO_APIC_irq(irq);
1344 spin_unlock_irqrestore(&ioapic_lock, flags);
1345
1346 return was_pending;
1347 }
1348
1349 static int ioapic_retrigger_irq(unsigned int irq)
1350 {
1351 struct irq_cfg *cfg = &irq_cfg[irq];
1352 cpumask_t mask;
1353 unsigned long flags;
1354
1355 spin_lock_irqsave(&vector_lock, flags);
1356 cpus_clear(mask);
1357 cpu_set(first_cpu(cfg->domain), mask);
1358
1359 send_IPI_mask(mask, cfg->vector);
1360 spin_unlock_irqrestore(&vector_lock, flags);
1361
1362 return 1;
1363 }
1364
1365 /*
1366 * Level and edge triggered IO-APIC interrupts need different handling,
1367 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1368 * handled with the level-triggered descriptor, but that one has slightly
1369 * more overhead. Level-triggered interrupts cannot be handled with the
1370 * edge-triggered handler, without risking IRQ storms and other ugly
1371 * races.
1372 */
1373
1374 #ifdef CONFIG_SMP
1375 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1376 {
1377 unsigned vector, me;
1378 ack_APIC_irq();
1379 exit_idle();
1380 irq_enter();
1381
1382 me = smp_processor_id();
1383 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1384 unsigned int irq;
1385 struct irq_desc *desc;
1386 struct irq_cfg *cfg;
1387 irq = __get_cpu_var(vector_irq)[vector];
1388 if (irq >= NR_IRQS)
1389 continue;
1390
1391 desc = irq_desc + irq;
1392 cfg = irq_cfg + irq;
1393 spin_lock(&desc->lock);
1394 if (!cfg->move_cleanup_count)
1395 goto unlock;
1396
1397 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1398 goto unlock;
1399
1400 __get_cpu_var(vector_irq)[vector] = -1;
1401 cfg->move_cleanup_count--;
1402 unlock:
1403 spin_unlock(&desc->lock);
1404 }
1405
1406 irq_exit();
1407 }
1408
1409 static void irq_complete_move(unsigned int irq)
1410 {
1411 struct irq_cfg *cfg = irq_cfg + irq;
1412 unsigned vector, me;
1413
1414 if (likely(!cfg->move_in_progress))
1415 return;
1416
1417 vector = ~get_irq_regs()->orig_ax;
1418 me = smp_processor_id();
1419 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1420 cpumask_t cleanup_mask;
1421
1422 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1423 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1424 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1425 cfg->move_in_progress = 0;
1426 }
1427 }
1428 #else
1429 static inline void irq_complete_move(unsigned int irq) {}
1430 #endif
1431
1432 static void ack_apic_edge(unsigned int irq)
1433 {
1434 irq_complete_move(irq);
1435 move_native_irq(irq);
1436 ack_APIC_irq();
1437 }
1438
1439 static void ack_apic_level(unsigned int irq)
1440 {
1441 int do_unmask_irq = 0;
1442
1443 irq_complete_move(irq);
1444 #ifdef CONFIG_GENERIC_PENDING_IRQ
1445 /* If we are moving the irq we need to mask it */
1446 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1447 do_unmask_irq = 1;
1448 mask_IO_APIC_irq(irq);
1449 }
1450 #endif
1451
1452 /*
1453 * We must acknowledge the irq before we move it or the acknowledge will
1454 * not propagate properly.
1455 */
1456 ack_APIC_irq();
1457
1458 /* Now we can move and renable the irq */
1459 if (unlikely(do_unmask_irq)) {
1460 /* Only migrate the irq if the ack has been received.
1461 *
1462 * On rare occasions the broadcast level triggered ack gets
1463 * delayed going to ioapics, and if we reprogram the
1464 * vector while Remote IRR is still set the irq will never
1465 * fire again.
1466 *
1467 * To prevent this scenario we read the Remote IRR bit
1468 * of the ioapic. This has two effects.
1469 * - On any sane system the read of the ioapic will
1470 * flush writes (and acks) going to the ioapic from
1471 * this cpu.
1472 * - We get to see if the ACK has actually been delivered.
1473 *
1474 * Based on failed experiments of reprogramming the
1475 * ioapic entry from outside of irq context starting
1476 * with masking the ioapic entry and then polling until
1477 * Remote IRR was clear before reprogramming the
1478 * ioapic I don't trust the Remote IRR bit to be
1479 * completey accurate.
1480 *
1481 * However there appears to be no other way to plug
1482 * this race, so if the Remote IRR bit is not
1483 * accurate and is causing problems then it is a hardware bug
1484 * and you can go talk to the chipset vendor about it.
1485 */
1486 if (!io_apic_level_ack_pending(irq))
1487 move_masked_irq(irq);
1488 unmask_IO_APIC_irq(irq);
1489 }
1490 }
1491
1492 static struct irq_chip ioapic_chip __read_mostly = {
1493 .name = "IO-APIC",
1494 .startup = startup_ioapic_irq,
1495 .mask = mask_IO_APIC_irq,
1496 .unmask = unmask_IO_APIC_irq,
1497 .ack = ack_apic_edge,
1498 .eoi = ack_apic_level,
1499 #ifdef CONFIG_SMP
1500 .set_affinity = set_ioapic_affinity_irq,
1501 #endif
1502 .retrigger = ioapic_retrigger_irq,
1503 };
1504
1505 static inline void init_IO_APIC_traps(void)
1506 {
1507 int irq;
1508
1509 /*
1510 * NOTE! The local APIC isn't very good at handling
1511 * multiple interrupts at the same interrupt level.
1512 * As the interrupt level is determined by taking the
1513 * vector number and shifting that right by 4, we
1514 * want to spread these out a bit so that they don't
1515 * all fall in the same interrupt level.
1516 *
1517 * Also, we've got to be careful not to trash gate
1518 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1519 */
1520 for (irq = 0; irq < NR_IRQS ; irq++) {
1521 int tmp = irq;
1522 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1523 /*
1524 * Hmm.. We don't have an entry for this,
1525 * so default to an old-fashioned 8259
1526 * interrupt if we can..
1527 */
1528 if (irq < 16)
1529 make_8259A_irq(irq);
1530 else
1531 /* Strange. Oh, well.. */
1532 irq_desc[irq].chip = &no_irq_chip;
1533 }
1534 }
1535 }
1536
1537 static void enable_lapic_irq (unsigned int irq)
1538 {
1539 unsigned long v;
1540
1541 v = apic_read(APIC_LVT0);
1542 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1543 }
1544
1545 static void disable_lapic_irq (unsigned int irq)
1546 {
1547 unsigned long v;
1548
1549 v = apic_read(APIC_LVT0);
1550 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1551 }
1552
1553 static void ack_lapic_irq (unsigned int irq)
1554 {
1555 ack_APIC_irq();
1556 }
1557
1558 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1559
1560 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1561 .name = "local-APIC",
1562 .typename = "local-APIC-edge",
1563 .startup = NULL, /* startup_irq() not used for IRQ0 */
1564 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1565 .enable = enable_lapic_irq,
1566 .disable = disable_lapic_irq,
1567 .ack = ack_lapic_irq,
1568 .end = end_lapic_irq,
1569 };
1570
1571 static void __init setup_nmi(void)
1572 {
1573 /*
1574 * Dirty trick to enable the NMI watchdog ...
1575 * We put the 8259A master into AEOI mode and
1576 * unmask on all local APICs LVT0 as NMI.
1577 *
1578 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1579 * is from Maciej W. Rozycki - so we do not have to EOI from
1580 * the NMI handler or the timer interrupt.
1581 */
1582 printk(KERN_INFO "activating NMI Watchdog ...");
1583
1584 enable_NMI_through_LVT0();
1585
1586 printk(" done.\n");
1587 }
1588
1589 /*
1590 * This looks a bit hackish but it's about the only one way of sending
1591 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1592 * not support the ExtINT mode, unfortunately. We need to send these
1593 * cycles as some i82489DX-based boards have glue logic that keeps the
1594 * 8259A interrupt line asserted until INTA. --macro
1595 */
1596 static inline void unlock_ExtINT_logic(void)
1597 {
1598 int apic, pin, i;
1599 struct IO_APIC_route_entry entry0, entry1;
1600 unsigned char save_control, save_freq_select;
1601 unsigned long flags;
1602
1603 pin = find_isa_irq_pin(8, mp_INT);
1604 apic = find_isa_irq_apic(8, mp_INT);
1605 if (pin == -1)
1606 return;
1607
1608 spin_lock_irqsave(&ioapic_lock, flags);
1609 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1610 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1611 spin_unlock_irqrestore(&ioapic_lock, flags);
1612 clear_IO_APIC_pin(apic, pin);
1613
1614 memset(&entry1, 0, sizeof(entry1));
1615
1616 entry1.dest_mode = 0; /* physical delivery */
1617 entry1.mask = 0; /* unmask IRQ now */
1618 entry1.dest = hard_smp_processor_id();
1619 entry1.delivery_mode = dest_ExtINT;
1620 entry1.polarity = entry0.polarity;
1621 entry1.trigger = 0;
1622 entry1.vector = 0;
1623
1624 spin_lock_irqsave(&ioapic_lock, flags);
1625 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1626 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1627 spin_unlock_irqrestore(&ioapic_lock, flags);
1628
1629 save_control = CMOS_READ(RTC_CONTROL);
1630 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1631 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1632 RTC_FREQ_SELECT);
1633 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1634
1635 i = 100;
1636 while (i-- > 0) {
1637 mdelay(10);
1638 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1639 i -= 10;
1640 }
1641
1642 CMOS_WRITE(save_control, RTC_CONTROL);
1643 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1644 clear_IO_APIC_pin(apic, pin);
1645
1646 spin_lock_irqsave(&ioapic_lock, flags);
1647 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1648 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1649 spin_unlock_irqrestore(&ioapic_lock, flags);
1650 }
1651
1652 /*
1653 * This code may look a bit paranoid, but it's supposed to cooperate with
1654 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1655 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1656 * fanatically on his truly buggy board.
1657 *
1658 * FIXME: really need to revamp this for modern platforms only.
1659 */
1660 static inline void __init check_timer(void)
1661 {
1662 struct irq_cfg *cfg = irq_cfg + 0;
1663 int apic1, pin1, apic2, pin2;
1664 unsigned long flags;
1665
1666 local_irq_save(flags);
1667
1668 /*
1669 * get/set the timer IRQ vector:
1670 */
1671 disable_8259A_irq(0);
1672 assign_irq_vector(0, TARGET_CPUS);
1673
1674 /*
1675 * Subtle, code in do_timer_interrupt() expects an AEOI
1676 * mode for the 8259A whenever interrupts are routed
1677 * through I/O APICs. Also IRQ0 has to be enabled in
1678 * the 8259A which implies the virtual wire has to be
1679 * disabled in the local APIC.
1680 */
1681 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1682 init_8259A(1);
1683 if (timer_over_8254 > 0)
1684 enable_8259A_irq(0);
1685
1686 pin1 = find_isa_irq_pin(0, mp_INT);
1687 apic1 = find_isa_irq_apic(0, mp_INT);
1688 pin2 = ioapic_i8259.pin;
1689 apic2 = ioapic_i8259.apic;
1690
1691 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1692 cfg->vector, apic1, pin1, apic2, pin2);
1693
1694 if (pin1 != -1) {
1695 /*
1696 * Ok, does IRQ0 through the IOAPIC work?
1697 */
1698 unmask_IO_APIC_irq(0);
1699 if (!no_timer_check && timer_irq_works()) {
1700 nmi_watchdog_default();
1701 if (nmi_watchdog == NMI_IO_APIC) {
1702 disable_8259A_irq(0);
1703 setup_nmi();
1704 enable_8259A_irq(0);
1705 }
1706 if (disable_timer_pin_1 > 0)
1707 clear_IO_APIC_pin(0, pin1);
1708 goto out;
1709 }
1710 clear_IO_APIC_pin(apic1, pin1);
1711 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1712 "connected to IO-APIC\n");
1713 }
1714
1715 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1716 "through the 8259A ... ");
1717 if (pin2 != -1) {
1718 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1719 apic2, pin2);
1720 /*
1721 * legacy devices should be connected to IO APIC #0
1722 */
1723 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1724 if (timer_irq_works()) {
1725 apic_printk(APIC_VERBOSE," works.\n");
1726 nmi_watchdog_default();
1727 if (nmi_watchdog == NMI_IO_APIC) {
1728 setup_nmi();
1729 }
1730 goto out;
1731 }
1732 /*
1733 * Cleanup, just in case ...
1734 */
1735 clear_IO_APIC_pin(apic2, pin2);
1736 }
1737 apic_printk(APIC_VERBOSE," failed.\n");
1738
1739 if (nmi_watchdog == NMI_IO_APIC) {
1740 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1741 nmi_watchdog = 0;
1742 }
1743
1744 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1745
1746 disable_8259A_irq(0);
1747 irq_desc[0].chip = &lapic_irq_type;
1748 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1749 enable_8259A_irq(0);
1750
1751 if (timer_irq_works()) {
1752 apic_printk(APIC_VERBOSE," works.\n");
1753 goto out;
1754 }
1755 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1756 apic_printk(APIC_VERBOSE," failed.\n");
1757
1758 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1759
1760 init_8259A(0);
1761 make_8259A_irq(0);
1762 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1763
1764 unlock_ExtINT_logic();
1765
1766 if (timer_irq_works()) {
1767 apic_printk(APIC_VERBOSE," works.\n");
1768 goto out;
1769 }
1770 apic_printk(APIC_VERBOSE," failed :(.\n");
1771 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1772 out:
1773 local_irq_restore(flags);
1774 }
1775
1776 static int __init notimercheck(char *s)
1777 {
1778 no_timer_check = 1;
1779 return 1;
1780 }
1781 __setup("no_timer_check", notimercheck);
1782
1783 /*
1784 *
1785 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1786 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1787 * Linux doesn't really care, as it's not actually used
1788 * for any interrupt handling anyway.
1789 */
1790 #define PIC_IRQS (1<<2)
1791
1792 void __init setup_IO_APIC(void)
1793 {
1794
1795 /*
1796 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1797 */
1798
1799 if (acpi_ioapic)
1800 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1801 else
1802 io_apic_irqs = ~PIC_IRQS;
1803
1804 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1805
1806 sync_Arb_IDs();
1807 setup_IO_APIC_irqs();
1808 init_IO_APIC_traps();
1809 check_timer();
1810 if (!acpi_ioapic)
1811 print_IO_APIC();
1812 }
1813
1814 struct sysfs_ioapic_data {
1815 struct sys_device dev;
1816 struct IO_APIC_route_entry entry[0];
1817 };
1818 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1819
1820 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1821 {
1822 struct IO_APIC_route_entry *entry;
1823 struct sysfs_ioapic_data *data;
1824 int i;
1825
1826 data = container_of(dev, struct sysfs_ioapic_data, dev);
1827 entry = data->entry;
1828 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1829 *entry = ioapic_read_entry(dev->id, i);
1830
1831 return 0;
1832 }
1833
1834 static int ioapic_resume(struct sys_device *dev)
1835 {
1836 struct IO_APIC_route_entry *entry;
1837 struct sysfs_ioapic_data *data;
1838 unsigned long flags;
1839 union IO_APIC_reg_00 reg_00;
1840 int i;
1841
1842 data = container_of(dev, struct sysfs_ioapic_data, dev);
1843 entry = data->entry;
1844
1845 spin_lock_irqsave(&ioapic_lock, flags);
1846 reg_00.raw = io_apic_read(dev->id, 0);
1847 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1848 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1849 io_apic_write(dev->id, 0, reg_00.raw);
1850 }
1851 spin_unlock_irqrestore(&ioapic_lock, flags);
1852 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1853 ioapic_write_entry(dev->id, i, entry[i]);
1854
1855 return 0;
1856 }
1857
1858 static struct sysdev_class ioapic_sysdev_class = {
1859 .name = "ioapic",
1860 .suspend = ioapic_suspend,
1861 .resume = ioapic_resume,
1862 };
1863
1864 static int __init ioapic_init_sysfs(void)
1865 {
1866 struct sys_device * dev;
1867 int i, size, error;
1868
1869 error = sysdev_class_register(&ioapic_sysdev_class);
1870 if (error)
1871 return error;
1872
1873 for (i = 0; i < nr_ioapics; i++ ) {
1874 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1875 * sizeof(struct IO_APIC_route_entry);
1876 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1877 if (!mp_ioapic_data[i]) {
1878 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1879 continue;
1880 }
1881 dev = &mp_ioapic_data[i]->dev;
1882 dev->id = i;
1883 dev->cls = &ioapic_sysdev_class;
1884 error = sysdev_register(dev);
1885 if (error) {
1886 kfree(mp_ioapic_data[i]);
1887 mp_ioapic_data[i] = NULL;
1888 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1889 continue;
1890 }
1891 }
1892
1893 return 0;
1894 }
1895
1896 device_initcall(ioapic_init_sysfs);
1897
1898 /*
1899 * Dynamic irq allocate and deallocation
1900 */
1901 int create_irq(void)
1902 {
1903 /* Allocate an unused irq */
1904 int irq;
1905 int new;
1906 unsigned long flags;
1907
1908 irq = -ENOSPC;
1909 spin_lock_irqsave(&vector_lock, flags);
1910 for (new = (NR_IRQS - 1); new >= 0; new--) {
1911 if (platform_legacy_irq(new))
1912 continue;
1913 if (irq_cfg[new].vector != 0)
1914 continue;
1915 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1916 irq = new;
1917 break;
1918 }
1919 spin_unlock_irqrestore(&vector_lock, flags);
1920
1921 if (irq >= 0) {
1922 dynamic_irq_init(irq);
1923 }
1924 return irq;
1925 }
1926
1927 void destroy_irq(unsigned int irq)
1928 {
1929 unsigned long flags;
1930
1931 dynamic_irq_cleanup(irq);
1932
1933 spin_lock_irqsave(&vector_lock, flags);
1934 __clear_irq_vector(irq);
1935 spin_unlock_irqrestore(&vector_lock, flags);
1936 }
1937
1938 /*
1939 * MSI message composition
1940 */
1941 #ifdef CONFIG_PCI_MSI
1942 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1943 {
1944 struct irq_cfg *cfg = irq_cfg + irq;
1945 int err;
1946 unsigned dest;
1947 cpumask_t tmp;
1948
1949 tmp = TARGET_CPUS;
1950 err = assign_irq_vector(irq, tmp);
1951 if (!err) {
1952 cpus_and(tmp, cfg->domain, tmp);
1953 dest = cpu_mask_to_apicid(tmp);
1954
1955 msg->address_hi = MSI_ADDR_BASE_HI;
1956 msg->address_lo =
1957 MSI_ADDR_BASE_LO |
1958 ((INT_DEST_MODE == 0) ?
1959 MSI_ADDR_DEST_MODE_PHYSICAL:
1960 MSI_ADDR_DEST_MODE_LOGICAL) |
1961 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1962 MSI_ADDR_REDIRECTION_CPU:
1963 MSI_ADDR_REDIRECTION_LOWPRI) |
1964 MSI_ADDR_DEST_ID(dest);
1965
1966 msg->data =
1967 MSI_DATA_TRIGGER_EDGE |
1968 MSI_DATA_LEVEL_ASSERT |
1969 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1970 MSI_DATA_DELIVERY_FIXED:
1971 MSI_DATA_DELIVERY_LOWPRI) |
1972 MSI_DATA_VECTOR(cfg->vector);
1973 }
1974 return err;
1975 }
1976
1977 #ifdef CONFIG_SMP
1978 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1979 {
1980 struct irq_cfg *cfg = irq_cfg + irq;
1981 struct msi_msg msg;
1982 unsigned int dest;
1983 cpumask_t tmp;
1984
1985 cpus_and(tmp, mask, cpu_online_map);
1986 if (cpus_empty(tmp))
1987 return;
1988
1989 if (assign_irq_vector(irq, mask))
1990 return;
1991
1992 cpus_and(tmp, cfg->domain, mask);
1993 dest = cpu_mask_to_apicid(tmp);
1994
1995 read_msi_msg(irq, &msg);
1996
1997 msg.data &= ~MSI_DATA_VECTOR_MASK;
1998 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1999 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2000 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2001
2002 write_msi_msg(irq, &msg);
2003 irq_desc[irq].affinity = mask;
2004 }
2005 #endif /* CONFIG_SMP */
2006
2007 /*
2008 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2009 * which implement the MSI or MSI-X Capability Structure.
2010 */
2011 static struct irq_chip msi_chip = {
2012 .name = "PCI-MSI",
2013 .unmask = unmask_msi_irq,
2014 .mask = mask_msi_irq,
2015 .ack = ack_apic_edge,
2016 #ifdef CONFIG_SMP
2017 .set_affinity = set_msi_irq_affinity,
2018 #endif
2019 .retrigger = ioapic_retrigger_irq,
2020 };
2021
2022 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2023 {
2024 struct msi_msg msg;
2025 int irq, ret;
2026 irq = create_irq();
2027 if (irq < 0)
2028 return irq;
2029
2030 ret = msi_compose_msg(dev, irq, &msg);
2031 if (ret < 0) {
2032 destroy_irq(irq);
2033 return ret;
2034 }
2035
2036 set_irq_msi(irq, desc);
2037 write_msi_msg(irq, &msg);
2038
2039 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2040
2041 return 0;
2042 }
2043
2044 void arch_teardown_msi_irq(unsigned int irq)
2045 {
2046 destroy_irq(irq);
2047 }
2048
2049 #ifdef CONFIG_DMAR
2050 #ifdef CONFIG_SMP
2051 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2052 {
2053 struct irq_cfg *cfg = irq_cfg + irq;
2054 struct msi_msg msg;
2055 unsigned int dest;
2056 cpumask_t tmp;
2057
2058 cpus_and(tmp, mask, cpu_online_map);
2059 if (cpus_empty(tmp))
2060 return;
2061
2062 if (assign_irq_vector(irq, mask))
2063 return;
2064
2065 cpus_and(tmp, cfg->domain, mask);
2066 dest = cpu_mask_to_apicid(tmp);
2067
2068 dmar_msi_read(irq, &msg);
2069
2070 msg.data &= ~MSI_DATA_VECTOR_MASK;
2071 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2072 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2073 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2074
2075 dmar_msi_write(irq, &msg);
2076 irq_desc[irq].affinity = mask;
2077 }
2078 #endif /* CONFIG_SMP */
2079
2080 struct irq_chip dmar_msi_type = {
2081 .name = "DMAR_MSI",
2082 .unmask = dmar_msi_unmask,
2083 .mask = dmar_msi_mask,
2084 .ack = ack_apic_edge,
2085 #ifdef CONFIG_SMP
2086 .set_affinity = dmar_msi_set_affinity,
2087 #endif
2088 .retrigger = ioapic_retrigger_irq,
2089 };
2090
2091 int arch_setup_dmar_msi(unsigned int irq)
2092 {
2093 int ret;
2094 struct msi_msg msg;
2095
2096 ret = msi_compose_msg(NULL, irq, &msg);
2097 if (ret < 0)
2098 return ret;
2099 dmar_msi_write(irq, &msg);
2100 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2101 "edge");
2102 return 0;
2103 }
2104 #endif
2105
2106 #endif /* CONFIG_PCI_MSI */
2107 /*
2108 * Hypertransport interrupt support
2109 */
2110 #ifdef CONFIG_HT_IRQ
2111
2112 #ifdef CONFIG_SMP
2113
2114 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2115 {
2116 struct ht_irq_msg msg;
2117 fetch_ht_irq_msg(irq, &msg);
2118
2119 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2120 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2121
2122 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2123 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2124
2125 write_ht_irq_msg(irq, &msg);
2126 }
2127
2128 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2129 {
2130 struct irq_cfg *cfg = irq_cfg + irq;
2131 unsigned int dest;
2132 cpumask_t tmp;
2133
2134 cpus_and(tmp, mask, cpu_online_map);
2135 if (cpus_empty(tmp))
2136 return;
2137
2138 if (assign_irq_vector(irq, mask))
2139 return;
2140
2141 cpus_and(tmp, cfg->domain, mask);
2142 dest = cpu_mask_to_apicid(tmp);
2143
2144 target_ht_irq(irq, dest, cfg->vector);
2145 irq_desc[irq].affinity = mask;
2146 }
2147 #endif
2148
2149 static struct irq_chip ht_irq_chip = {
2150 .name = "PCI-HT",
2151 .mask = mask_ht_irq,
2152 .unmask = unmask_ht_irq,
2153 .ack = ack_apic_edge,
2154 #ifdef CONFIG_SMP
2155 .set_affinity = set_ht_irq_affinity,
2156 #endif
2157 .retrigger = ioapic_retrigger_irq,
2158 };
2159
2160 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2161 {
2162 struct irq_cfg *cfg = irq_cfg + irq;
2163 int err;
2164 cpumask_t tmp;
2165
2166 tmp = TARGET_CPUS;
2167 err = assign_irq_vector(irq, tmp);
2168 if (!err) {
2169 struct ht_irq_msg msg;
2170 unsigned dest;
2171
2172 cpus_and(tmp, cfg->domain, tmp);
2173 dest = cpu_mask_to_apicid(tmp);
2174
2175 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2176
2177 msg.address_lo =
2178 HT_IRQ_LOW_BASE |
2179 HT_IRQ_LOW_DEST_ID(dest) |
2180 HT_IRQ_LOW_VECTOR(cfg->vector) |
2181 ((INT_DEST_MODE == 0) ?
2182 HT_IRQ_LOW_DM_PHYSICAL :
2183 HT_IRQ_LOW_DM_LOGICAL) |
2184 HT_IRQ_LOW_RQEOI_EDGE |
2185 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2186 HT_IRQ_LOW_MT_FIXED :
2187 HT_IRQ_LOW_MT_ARBITRATED) |
2188 HT_IRQ_LOW_IRQ_MASKED;
2189
2190 write_ht_irq_msg(irq, &msg);
2191
2192 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2193 handle_edge_irq, "edge");
2194 }
2195 return err;
2196 }
2197 #endif /* CONFIG_HT_IRQ */
2198
2199 /* --------------------------------------------------------------------------
2200 ACPI-based IOAPIC Configuration
2201 -------------------------------------------------------------------------- */
2202
2203 #ifdef CONFIG_ACPI
2204
2205 #define IO_APIC_MAX_ID 0xFE
2206
2207 int __init io_apic_get_redir_entries (int ioapic)
2208 {
2209 union IO_APIC_reg_01 reg_01;
2210 unsigned long flags;
2211
2212 spin_lock_irqsave(&ioapic_lock, flags);
2213 reg_01.raw = io_apic_read(ioapic, 1);
2214 spin_unlock_irqrestore(&ioapic_lock, flags);
2215
2216 return reg_01.bits.entries;
2217 }
2218
2219
2220 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2221 {
2222 if (!IO_APIC_IRQ(irq)) {
2223 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2224 ioapic);
2225 return -EINVAL;
2226 }
2227
2228 /*
2229 * IRQs < 16 are already in the irq_2_pin[] map
2230 */
2231 if (irq >= 16)
2232 add_pin_to_irq(irq, ioapic, pin);
2233
2234 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2235
2236 return 0;
2237 }
2238
2239
2240 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2241 {
2242 int i;
2243
2244 if (skip_ioapic_setup)
2245 return -1;
2246
2247 for (i = 0; i < mp_irq_entries; i++)
2248 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2249 mp_irqs[i].mpc_srcbusirq == bus_irq)
2250 break;
2251 if (i >= mp_irq_entries)
2252 return -1;
2253
2254 *trigger = irq_trigger(i);
2255 *polarity = irq_polarity(i);
2256 return 0;
2257 }
2258
2259 #endif /* CONFIG_ACPI */
2260
2261 /*
2262 * This function currently is only a helper for the i386 smp boot process where
2263 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2264 * so mask in all cases should simply be TARGET_CPUS
2265 */
2266 #ifdef CONFIG_SMP
2267 void __init setup_ioapic_dest(void)
2268 {
2269 int pin, ioapic, irq, irq_entry;
2270
2271 if (skip_ioapic_setup == 1)
2272 return;
2273
2274 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2275 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2276 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2277 if (irq_entry == -1)
2278 continue;
2279 irq = pin_2_irq(irq_entry, ioapic, pin);
2280
2281 /* setup_IO_APIC_irqs could fail to get vector for some device
2282 * when you have too many devices, because at that time only boot
2283 * cpu is online.
2284 */
2285 if (!irq_cfg[irq].vector)
2286 setup_IO_APIC_irq(ioapic, pin, irq,
2287 irq_trigger(irq_entry),
2288 irq_polarity(irq_entry));
2289 else
2290 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2291 }
2292
2293 }
2294 }
2295 #endif
2296
2297 #define IOAPIC_RESOURCE_NAME_SIZE 11
2298
2299 static struct resource *ioapic_resources;
2300
2301 static struct resource * __init ioapic_setup_resources(void)
2302 {
2303 unsigned long n;
2304 struct resource *res;
2305 char *mem;
2306 int i;
2307
2308 if (nr_ioapics <= 0)
2309 return NULL;
2310
2311 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2312 n *= nr_ioapics;
2313
2314 mem = alloc_bootmem(n);
2315 res = (void *)mem;
2316
2317 if (mem != NULL) {
2318 memset(mem, 0, n);
2319 mem += sizeof(struct resource) * nr_ioapics;
2320
2321 for (i = 0; i < nr_ioapics; i++) {
2322 res[i].name = mem;
2323 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2324 sprintf(mem, "IOAPIC %u", i);
2325 mem += IOAPIC_RESOURCE_NAME_SIZE;
2326 }
2327 }
2328
2329 ioapic_resources = res;
2330
2331 return res;
2332 }
2333
2334 void __init ioapic_init_mappings(void)
2335 {
2336 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2337 struct resource *ioapic_res;
2338 int i;
2339
2340 ioapic_res = ioapic_setup_resources();
2341 for (i = 0; i < nr_ioapics; i++) {
2342 if (smp_found_config) {
2343 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2344 } else {
2345 ioapic_phys = (unsigned long)
2346 alloc_bootmem_pages(PAGE_SIZE);
2347 ioapic_phys = __pa(ioapic_phys);
2348 }
2349 set_fixmap_nocache(idx, ioapic_phys);
2350 apic_printk(APIC_VERBOSE,
2351 "mapped IOAPIC to %016lx (%016lx)\n",
2352 __fix_to_virt(idx), ioapic_phys);
2353 idx++;
2354
2355 if (ioapic_res != NULL) {
2356 ioapic_res->start = ioapic_phys;
2357 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2358 ioapic_res++;
2359 }
2360 }
2361 }
2362
2363 static int __init ioapic_insert_resources(void)
2364 {
2365 int i;
2366 struct resource *r = ioapic_resources;
2367
2368 if (!r) {
2369 printk(KERN_ERR
2370 "IO APIC resources could be not be allocated.\n");
2371 return -1;
2372 }
2373
2374 for (i = 0; i < nr_ioapics; i++) {
2375 insert_resource(&iomem_resource, r);
2376 r++;
2377 }
2378
2379 return 0;
2380 }
2381
2382 /* Insert the IO APIC resources after PCI initialization has occured to handle
2383 * IO APICS that are mapped in on a BAR in PCI space. */
2384 late_initcall(ioapic_insert_resources);
2385
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