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x86: I/O APIC: keep IRQ off when changing LVT registers
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/nmi.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
51
52 #include <mach_ipi.h>
53 #include <mach_apic.h>
54
55 struct irq_cfg {
56 cpumask_t domain;
57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
59 u8 vector;
60 u8 move_in_progress : 1;
61 };
62
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
81 };
82
83 static int assign_irq_vector(int irq, cpumask_t mask);
84
85 #define __apicdebuginit __init
86
87 int sis_apic_bug; /* not actually supported, dummy for compile */
88
89 static int no_timer_check;
90
91 static int disable_timer_pin_1 __initdata;
92
93
94 /* Where if anywhere is the i8259 connect in external int mode */
95 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
96
97 static DEFINE_SPINLOCK(ioapic_lock);
98 DEFINE_SPINLOCK(vector_lock);
99
100 /*
101 * # of IRQ routing registers
102 */
103 int nr_ioapic_registers[MAX_IO_APICS];
104
105 /* I/O APIC entries */
106 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
107 int nr_ioapics;
108
109 /* MP IRQ source entries */
110 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
111
112 /* # of MP IRQ source entries */
113 int mp_irq_entries;
114
115 /*
116 * Rough estimation of how many shared IRQs there are, can
117 * be changed anytime.
118 */
119 #define MAX_PLUS_SHARED_IRQS NR_IRQS
120 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
121
122 /*
123 * This is performance-critical, we want to do it O(1)
124 *
125 * the indexing order of this array favors 1:1 mappings
126 * between pins and IRQs.
127 */
128
129 static struct irq_pin_list {
130 short apic, pin, next;
131 } irq_2_pin[PIN_MAP_SIZE];
132
133 struct io_apic {
134 unsigned int index;
135 unsigned int unused[3];
136 unsigned int data;
137 };
138
139 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
140 {
141 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
142 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
143 }
144
145 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
146 {
147 struct io_apic __iomem *io_apic = io_apic_base(apic);
148 writel(reg, &io_apic->index);
149 return readl(&io_apic->data);
150 }
151
152 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
153 {
154 struct io_apic __iomem *io_apic = io_apic_base(apic);
155 writel(reg, &io_apic->index);
156 writel(value, &io_apic->data);
157 }
158
159 /*
160 * Re-write a value: to be used for read-modify-write
161 * cycles where the read already set up the index register.
162 */
163 static inline void io_apic_modify(unsigned int apic, unsigned int value)
164 {
165 struct io_apic __iomem *io_apic = io_apic_base(apic);
166 writel(value, &io_apic->data);
167 }
168
169 static bool io_apic_level_ack_pending(unsigned int irq)
170 {
171 struct irq_pin_list *entry;
172 unsigned long flags;
173
174 spin_lock_irqsave(&ioapic_lock, flags);
175 entry = irq_2_pin + irq;
176 for (;;) {
177 unsigned int reg;
178 int pin;
179
180 pin = entry->pin;
181 if (pin == -1)
182 break;
183 reg = io_apic_read(entry->apic, 0x10 + pin*2);
184 /* Is the remote IRR bit set? */
185 if ((reg >> 14) & 1) {
186 spin_unlock_irqrestore(&ioapic_lock, flags);
187 return true;
188 }
189 if (!entry->next)
190 break;
191 entry = irq_2_pin + entry->next;
192 }
193 spin_unlock_irqrestore(&ioapic_lock, flags);
194
195 return false;
196 }
197
198 /*
199 * Synchronize the IO-APIC and the CPU by doing
200 * a dummy read from the IO-APIC
201 */
202 static inline void io_apic_sync(unsigned int apic)
203 {
204 struct io_apic __iomem *io_apic = io_apic_base(apic);
205 readl(&io_apic->data);
206 }
207
208 #define __DO_ACTION(R, ACTION, FINAL) \
209 \
210 { \
211 int pin; \
212 struct irq_pin_list *entry = irq_2_pin + irq; \
213 \
214 BUG_ON(irq >= NR_IRQS); \
215 for (;;) { \
216 unsigned int reg; \
217 pin = entry->pin; \
218 if (pin == -1) \
219 break; \
220 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
221 reg ACTION; \
222 io_apic_modify(entry->apic, reg); \
223 FINAL; \
224 if (!entry->next) \
225 break; \
226 entry = irq_2_pin + entry->next; \
227 } \
228 }
229
230 union entry_union {
231 struct { u32 w1, w2; };
232 struct IO_APIC_route_entry entry;
233 };
234
235 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
236 {
237 union entry_union eu;
238 unsigned long flags;
239 spin_lock_irqsave(&ioapic_lock, flags);
240 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
241 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
242 spin_unlock_irqrestore(&ioapic_lock, flags);
243 return eu.entry;
244 }
245
246 /*
247 * When we write a new IO APIC routing entry, we need to write the high
248 * word first! If the mask bit in the low word is clear, we will enable
249 * the interrupt, and we need to make sure the entry is fully populated
250 * before that happens.
251 */
252 static void
253 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
254 {
255 union entry_union eu;
256 eu.entry = e;
257 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
258 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
259 }
260
261 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
262 {
263 unsigned long flags;
264 spin_lock_irqsave(&ioapic_lock, flags);
265 __ioapic_write_entry(apic, pin, e);
266 spin_unlock_irqrestore(&ioapic_lock, flags);
267 }
268
269 /*
270 * When we mask an IO APIC routing entry, we need to write the low
271 * word first, in order to set the mask bit before we change the
272 * high bits!
273 */
274 static void ioapic_mask_entry(int apic, int pin)
275 {
276 unsigned long flags;
277 union entry_union eu = { .entry.mask = 1 };
278
279 spin_lock_irqsave(&ioapic_lock, flags);
280 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
281 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
282 spin_unlock_irqrestore(&ioapic_lock, flags);
283 }
284
285 #ifdef CONFIG_SMP
286 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
287 {
288 int apic, pin;
289 struct irq_pin_list *entry = irq_2_pin + irq;
290
291 BUG_ON(irq >= NR_IRQS);
292 for (;;) {
293 unsigned int reg;
294 apic = entry->apic;
295 pin = entry->pin;
296 if (pin == -1)
297 break;
298 io_apic_write(apic, 0x11 + pin*2, dest);
299 reg = io_apic_read(apic, 0x10 + pin*2);
300 reg &= ~0x000000ff;
301 reg |= vector;
302 io_apic_modify(apic, reg);
303 if (!entry->next)
304 break;
305 entry = irq_2_pin + entry->next;
306 }
307 }
308
309 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
310 {
311 struct irq_cfg *cfg = irq_cfg + irq;
312 unsigned long flags;
313 unsigned int dest;
314 cpumask_t tmp;
315
316 cpus_and(tmp, mask, cpu_online_map);
317 if (cpus_empty(tmp))
318 return;
319
320 if (assign_irq_vector(irq, mask))
321 return;
322
323 cpus_and(tmp, cfg->domain, mask);
324 dest = cpu_mask_to_apicid(tmp);
325
326 /*
327 * Only the high 8 bits are valid.
328 */
329 dest = SET_APIC_LOGICAL_ID(dest);
330
331 spin_lock_irqsave(&ioapic_lock, flags);
332 __target_IO_APIC_irq(irq, dest, cfg->vector);
333 irq_desc[irq].affinity = mask;
334 spin_unlock_irqrestore(&ioapic_lock, flags);
335 }
336 #endif
337
338 /*
339 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
340 * shared ISA-space IRQs, so we have to support them. We are super
341 * fast in the common case, and fast for shared ISA-space IRQs.
342 */
343 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
344 {
345 static int first_free_entry = NR_IRQS;
346 struct irq_pin_list *entry = irq_2_pin + irq;
347
348 BUG_ON(irq >= NR_IRQS);
349 while (entry->next)
350 entry = irq_2_pin + entry->next;
351
352 if (entry->pin != -1) {
353 entry->next = first_free_entry;
354 entry = irq_2_pin + entry->next;
355 if (++first_free_entry >= PIN_MAP_SIZE)
356 panic("io_apic.c: ran out of irq_2_pin entries!");
357 }
358 entry->apic = apic;
359 entry->pin = pin;
360 }
361
362
363 #define DO_ACTION(name,R,ACTION, FINAL) \
364 \
365 static void name##_IO_APIC_irq (unsigned int irq) \
366 __DO_ACTION(R, ACTION, FINAL)
367
368 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
369 /* mask = 1 */
370 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
371 /* mask = 0 */
372
373 static void mask_IO_APIC_irq (unsigned int irq)
374 {
375 unsigned long flags;
376
377 spin_lock_irqsave(&ioapic_lock, flags);
378 __mask_IO_APIC_irq(irq);
379 spin_unlock_irqrestore(&ioapic_lock, flags);
380 }
381
382 static void unmask_IO_APIC_irq (unsigned int irq)
383 {
384 unsigned long flags;
385
386 spin_lock_irqsave(&ioapic_lock, flags);
387 __unmask_IO_APIC_irq(irq);
388 spin_unlock_irqrestore(&ioapic_lock, flags);
389 }
390
391 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
392 {
393 struct IO_APIC_route_entry entry;
394
395 /* Check delivery_mode to be sure we're not clearing an SMI pin */
396 entry = ioapic_read_entry(apic, pin);
397 if (entry.delivery_mode == dest_SMI)
398 return;
399 /*
400 * Disable it in the IO-APIC irq-routing table:
401 */
402 ioapic_mask_entry(apic, pin);
403 }
404
405 static void clear_IO_APIC (void)
406 {
407 int apic, pin;
408
409 for (apic = 0; apic < nr_ioapics; apic++)
410 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
411 clear_IO_APIC_pin(apic, pin);
412 }
413
414 int skip_ioapic_setup;
415 int ioapic_force;
416
417 static int __init parse_noapic(char *str)
418 {
419 disable_ioapic_setup();
420 return 0;
421 }
422 early_param("noapic", parse_noapic);
423
424 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
425 static int __init disable_timer_pin_setup(char *arg)
426 {
427 disable_timer_pin_1 = 1;
428 return 1;
429 }
430 __setup("disable_timer_pin_1", disable_timer_pin_setup);
431
432
433 /*
434 * Find the IRQ entry number of a certain pin.
435 */
436 static int find_irq_entry(int apic, int pin, int type)
437 {
438 int i;
439
440 for (i = 0; i < mp_irq_entries; i++)
441 if (mp_irqs[i].mpc_irqtype == type &&
442 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
443 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
444 mp_irqs[i].mpc_dstirq == pin)
445 return i;
446
447 return -1;
448 }
449
450 /*
451 * Find the pin to which IRQ[irq] (ISA) is connected
452 */
453 static int __init find_isa_irq_pin(int irq, int type)
454 {
455 int i;
456
457 for (i = 0; i < mp_irq_entries; i++) {
458 int lbus = mp_irqs[i].mpc_srcbus;
459
460 if (test_bit(lbus, mp_bus_not_pci) &&
461 (mp_irqs[i].mpc_irqtype == type) &&
462 (mp_irqs[i].mpc_srcbusirq == irq))
463
464 return mp_irqs[i].mpc_dstirq;
465 }
466 return -1;
467 }
468
469 static int __init find_isa_irq_apic(int irq, int type)
470 {
471 int i;
472
473 for (i = 0; i < mp_irq_entries; i++) {
474 int lbus = mp_irqs[i].mpc_srcbus;
475
476 if (test_bit(lbus, mp_bus_not_pci) &&
477 (mp_irqs[i].mpc_irqtype == type) &&
478 (mp_irqs[i].mpc_srcbusirq == irq))
479 break;
480 }
481 if (i < mp_irq_entries) {
482 int apic;
483 for(apic = 0; apic < nr_ioapics; apic++) {
484 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
485 return apic;
486 }
487 }
488
489 return -1;
490 }
491
492 /*
493 * Find a specific PCI IRQ entry.
494 * Not an __init, possibly needed by modules
495 */
496 static int pin_2_irq(int idx, int apic, int pin);
497
498 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
499 {
500 int apic, i, best_guess = -1;
501
502 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
503 bus, slot, pin);
504 if (mp_bus_id_to_pci_bus[bus] == -1) {
505 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
506 return -1;
507 }
508 for (i = 0; i < mp_irq_entries; i++) {
509 int lbus = mp_irqs[i].mpc_srcbus;
510
511 for (apic = 0; apic < nr_ioapics; apic++)
512 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
513 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
514 break;
515
516 if (!test_bit(lbus, mp_bus_not_pci) &&
517 !mp_irqs[i].mpc_irqtype &&
518 (bus == lbus) &&
519 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
520 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
521
522 if (!(apic || IO_APIC_IRQ(irq)))
523 continue;
524
525 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
526 return irq;
527 /*
528 * Use the first all-but-pin matching entry as a
529 * best-guess fuzzy result for broken mptables.
530 */
531 if (best_guess < 0)
532 best_guess = irq;
533 }
534 }
535 BUG_ON(best_guess >= NR_IRQS);
536 return best_guess;
537 }
538
539 /* ISA interrupts are always polarity zero edge triggered,
540 * when listed as conforming in the MP table. */
541
542 #define default_ISA_trigger(idx) (0)
543 #define default_ISA_polarity(idx) (0)
544
545 /* PCI interrupts are always polarity one level triggered,
546 * when listed as conforming in the MP table. */
547
548 #define default_PCI_trigger(idx) (1)
549 #define default_PCI_polarity(idx) (1)
550
551 static int MPBIOS_polarity(int idx)
552 {
553 int bus = mp_irqs[idx].mpc_srcbus;
554 int polarity;
555
556 /*
557 * Determine IRQ line polarity (high active or low active):
558 */
559 switch (mp_irqs[idx].mpc_irqflag & 3)
560 {
561 case 0: /* conforms, ie. bus-type dependent polarity */
562 if (test_bit(bus, mp_bus_not_pci))
563 polarity = default_ISA_polarity(idx);
564 else
565 polarity = default_PCI_polarity(idx);
566 break;
567 case 1: /* high active */
568 {
569 polarity = 0;
570 break;
571 }
572 case 2: /* reserved */
573 {
574 printk(KERN_WARNING "broken BIOS!!\n");
575 polarity = 1;
576 break;
577 }
578 case 3: /* low active */
579 {
580 polarity = 1;
581 break;
582 }
583 default: /* invalid */
584 {
585 printk(KERN_WARNING "broken BIOS!!\n");
586 polarity = 1;
587 break;
588 }
589 }
590 return polarity;
591 }
592
593 static int MPBIOS_trigger(int idx)
594 {
595 int bus = mp_irqs[idx].mpc_srcbus;
596 int trigger;
597
598 /*
599 * Determine IRQ trigger mode (edge or level sensitive):
600 */
601 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
602 {
603 case 0: /* conforms, ie. bus-type dependent */
604 if (test_bit(bus, mp_bus_not_pci))
605 trigger = default_ISA_trigger(idx);
606 else
607 trigger = default_PCI_trigger(idx);
608 break;
609 case 1: /* edge */
610 {
611 trigger = 0;
612 break;
613 }
614 case 2: /* reserved */
615 {
616 printk(KERN_WARNING "broken BIOS!!\n");
617 trigger = 1;
618 break;
619 }
620 case 3: /* level */
621 {
622 trigger = 1;
623 break;
624 }
625 default: /* invalid */
626 {
627 printk(KERN_WARNING "broken BIOS!!\n");
628 trigger = 0;
629 break;
630 }
631 }
632 return trigger;
633 }
634
635 static inline int irq_polarity(int idx)
636 {
637 return MPBIOS_polarity(idx);
638 }
639
640 static inline int irq_trigger(int idx)
641 {
642 return MPBIOS_trigger(idx);
643 }
644
645 static int pin_2_irq(int idx, int apic, int pin)
646 {
647 int irq, i;
648 int bus = mp_irqs[idx].mpc_srcbus;
649
650 /*
651 * Debugging check, we are in big trouble if this message pops up!
652 */
653 if (mp_irqs[idx].mpc_dstirq != pin)
654 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
655
656 if (test_bit(bus, mp_bus_not_pci)) {
657 irq = mp_irqs[idx].mpc_srcbusirq;
658 } else {
659 /*
660 * PCI IRQs are mapped in order
661 */
662 i = irq = 0;
663 while (i < apic)
664 irq += nr_ioapic_registers[i++];
665 irq += pin;
666 }
667 BUG_ON(irq >= NR_IRQS);
668 return irq;
669 }
670
671 static int __assign_irq_vector(int irq, cpumask_t mask)
672 {
673 /*
674 * NOTE! The local APIC isn't very good at handling
675 * multiple interrupts at the same interrupt level.
676 * As the interrupt level is determined by taking the
677 * vector number and shifting that right by 4, we
678 * want to spread these out a bit so that they don't
679 * all fall in the same interrupt level.
680 *
681 * Also, we've got to be careful not to trash gate
682 * 0x80, because int 0x80 is hm, kind of importantish. ;)
683 */
684 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
685 unsigned int old_vector;
686 int cpu;
687 struct irq_cfg *cfg;
688
689 BUG_ON((unsigned)irq >= NR_IRQS);
690 cfg = &irq_cfg[irq];
691
692 /* Only try and allocate irqs on cpus that are present */
693 cpus_and(mask, mask, cpu_online_map);
694
695 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
696 return -EBUSY;
697
698 old_vector = cfg->vector;
699 if (old_vector) {
700 cpumask_t tmp;
701 cpus_and(tmp, cfg->domain, mask);
702 if (!cpus_empty(tmp))
703 return 0;
704 }
705
706 for_each_cpu_mask(cpu, mask) {
707 cpumask_t domain, new_mask;
708 int new_cpu;
709 int vector, offset;
710
711 domain = vector_allocation_domain(cpu);
712 cpus_and(new_mask, domain, cpu_online_map);
713
714 vector = current_vector;
715 offset = current_offset;
716 next:
717 vector += 8;
718 if (vector >= FIRST_SYSTEM_VECTOR) {
719 /* If we run out of vectors on large boxen, must share them. */
720 offset = (offset + 1) % 8;
721 vector = FIRST_DEVICE_VECTOR + offset;
722 }
723 if (unlikely(current_vector == vector))
724 continue;
725 if (vector == IA32_SYSCALL_VECTOR)
726 goto next;
727 for_each_cpu_mask(new_cpu, new_mask)
728 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
729 goto next;
730 /* Found one! */
731 current_vector = vector;
732 current_offset = offset;
733 if (old_vector) {
734 cfg->move_in_progress = 1;
735 cfg->old_domain = cfg->domain;
736 }
737 for_each_cpu_mask(new_cpu, new_mask)
738 per_cpu(vector_irq, new_cpu)[vector] = irq;
739 cfg->vector = vector;
740 cfg->domain = domain;
741 return 0;
742 }
743 return -ENOSPC;
744 }
745
746 static int assign_irq_vector(int irq, cpumask_t mask)
747 {
748 int err;
749 unsigned long flags;
750
751 spin_lock_irqsave(&vector_lock, flags);
752 err = __assign_irq_vector(irq, mask);
753 spin_unlock_irqrestore(&vector_lock, flags);
754 return err;
755 }
756
757 static void __clear_irq_vector(int irq)
758 {
759 struct irq_cfg *cfg;
760 cpumask_t mask;
761 int cpu, vector;
762
763 BUG_ON((unsigned)irq >= NR_IRQS);
764 cfg = &irq_cfg[irq];
765 BUG_ON(!cfg->vector);
766
767 vector = cfg->vector;
768 cpus_and(mask, cfg->domain, cpu_online_map);
769 for_each_cpu_mask(cpu, mask)
770 per_cpu(vector_irq, cpu)[vector] = -1;
771
772 cfg->vector = 0;
773 cpus_clear(cfg->domain);
774 }
775
776 void __setup_vector_irq(int cpu)
777 {
778 /* Initialize vector_irq on a new cpu */
779 /* This function must be called with vector_lock held */
780 int irq, vector;
781
782 /* Mark the inuse vectors */
783 for (irq = 0; irq < NR_IRQS; ++irq) {
784 if (!cpu_isset(cpu, irq_cfg[irq].domain))
785 continue;
786 vector = irq_cfg[irq].vector;
787 per_cpu(vector_irq, cpu)[vector] = irq;
788 }
789 /* Mark the free vectors */
790 for (vector = 0; vector < NR_VECTORS; ++vector) {
791 irq = per_cpu(vector_irq, cpu)[vector];
792 if (irq < 0)
793 continue;
794 if (!cpu_isset(cpu, irq_cfg[irq].domain))
795 per_cpu(vector_irq, cpu)[vector] = -1;
796 }
797 }
798
799
800 static struct irq_chip ioapic_chip;
801
802 static void ioapic_register_intr(int irq, unsigned long trigger)
803 {
804 if (trigger) {
805 irq_desc[irq].status |= IRQ_LEVEL;
806 set_irq_chip_and_handler_name(irq, &ioapic_chip,
807 handle_fasteoi_irq, "fasteoi");
808 } else {
809 irq_desc[irq].status &= ~IRQ_LEVEL;
810 set_irq_chip_and_handler_name(irq, &ioapic_chip,
811 handle_edge_irq, "edge");
812 }
813 }
814
815 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
816 int trigger, int polarity)
817 {
818 struct irq_cfg *cfg = irq_cfg + irq;
819 struct IO_APIC_route_entry entry;
820 cpumask_t mask;
821
822 if (!IO_APIC_IRQ(irq))
823 return;
824
825 mask = TARGET_CPUS;
826 if (assign_irq_vector(irq, mask))
827 return;
828
829 cpus_and(mask, cfg->domain, mask);
830
831 apic_printk(APIC_VERBOSE,KERN_DEBUG
832 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
833 "IRQ %d Mode:%i Active:%i)\n",
834 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
835 irq, trigger, polarity);
836
837 /*
838 * add it to the IO-APIC irq-routing table:
839 */
840 memset(&entry,0,sizeof(entry));
841
842 entry.delivery_mode = INT_DELIVERY_MODE;
843 entry.dest_mode = INT_DEST_MODE;
844 entry.dest = cpu_mask_to_apicid(mask);
845 entry.mask = 0; /* enable IRQ */
846 entry.trigger = trigger;
847 entry.polarity = polarity;
848 entry.vector = cfg->vector;
849
850 /* Mask level triggered irqs.
851 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
852 */
853 if (trigger)
854 entry.mask = 1;
855
856 ioapic_register_intr(irq, trigger);
857 if (irq < 16)
858 disable_8259A_irq(irq);
859
860 ioapic_write_entry(apic, pin, entry);
861 }
862
863 static void __init setup_IO_APIC_irqs(void)
864 {
865 int apic, pin, idx, irq, first_notcon = 1;
866
867 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
868
869 for (apic = 0; apic < nr_ioapics; apic++) {
870 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
871
872 idx = find_irq_entry(apic,pin,mp_INT);
873 if (idx == -1) {
874 if (first_notcon) {
875 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
876 first_notcon = 0;
877 } else
878 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
879 continue;
880 }
881 if (!first_notcon) {
882 apic_printk(APIC_VERBOSE, " not connected.\n");
883 first_notcon = 1;
884 }
885
886 irq = pin_2_irq(idx, apic, pin);
887 add_pin_to_irq(irq, apic, pin);
888
889 setup_IO_APIC_irq(apic, pin, irq,
890 irq_trigger(idx), irq_polarity(idx));
891 }
892 }
893
894 if (!first_notcon)
895 apic_printk(APIC_VERBOSE, " not connected.\n");
896 }
897
898 /*
899 * Set up the 8259A-master output pin as broadcast to all
900 * CPUs.
901 */
902 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
903 {
904 struct IO_APIC_route_entry entry;
905
906 memset(&entry, 0, sizeof(entry));
907
908 disable_8259A_irq(0);
909
910 /* mask LVT0 */
911 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
912
913 /*
914 * We use logical delivery to get the timer IRQ
915 * to the first CPU.
916 */
917 entry.dest_mode = INT_DEST_MODE;
918 entry.mask = 0; /* unmask IRQ now */
919 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
920 entry.delivery_mode = INT_DELIVERY_MODE;
921 entry.polarity = 0;
922 entry.trigger = 0;
923 entry.vector = vector;
924
925 /*
926 * The timer IRQ doesn't have to know that behind the
927 * scene we have a 8259A-master in AEOI mode ...
928 */
929 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
930
931 /*
932 * Add it to the IO-APIC irq-routing table:
933 */
934 ioapic_write_entry(apic, pin, entry);
935
936 enable_8259A_irq(0);
937 }
938
939 void __apicdebuginit print_IO_APIC(void)
940 {
941 int apic, i;
942 union IO_APIC_reg_00 reg_00;
943 union IO_APIC_reg_01 reg_01;
944 union IO_APIC_reg_02 reg_02;
945 unsigned long flags;
946
947 if (apic_verbosity == APIC_QUIET)
948 return;
949
950 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
951 for (i = 0; i < nr_ioapics; i++)
952 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
953 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
954
955 /*
956 * We are a bit conservative about what we expect. We have to
957 * know about every hardware change ASAP.
958 */
959 printk(KERN_INFO "testing the IO APIC.......................\n");
960
961 for (apic = 0; apic < nr_ioapics; apic++) {
962
963 spin_lock_irqsave(&ioapic_lock, flags);
964 reg_00.raw = io_apic_read(apic, 0);
965 reg_01.raw = io_apic_read(apic, 1);
966 if (reg_01.bits.version >= 0x10)
967 reg_02.raw = io_apic_read(apic, 2);
968 spin_unlock_irqrestore(&ioapic_lock, flags);
969
970 printk("\n");
971 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
972 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
973 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
974
975 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
976 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
977
978 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
979 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
980
981 if (reg_01.bits.version >= 0x10) {
982 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
983 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
984 }
985
986 printk(KERN_DEBUG ".... IRQ redirection table:\n");
987
988 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
989 " Stat Dmod Deli Vect: \n");
990
991 for (i = 0; i <= reg_01.bits.entries; i++) {
992 struct IO_APIC_route_entry entry;
993
994 entry = ioapic_read_entry(apic, i);
995
996 printk(KERN_DEBUG " %02x %03X ",
997 i,
998 entry.dest
999 );
1000
1001 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1002 entry.mask,
1003 entry.trigger,
1004 entry.irr,
1005 entry.polarity,
1006 entry.delivery_status,
1007 entry.dest_mode,
1008 entry.delivery_mode,
1009 entry.vector
1010 );
1011 }
1012 }
1013 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1014 for (i = 0; i < NR_IRQS; i++) {
1015 struct irq_pin_list *entry = irq_2_pin + i;
1016 if (entry->pin < 0)
1017 continue;
1018 printk(KERN_DEBUG "IRQ%d ", i);
1019 for (;;) {
1020 printk("-> %d:%d", entry->apic, entry->pin);
1021 if (!entry->next)
1022 break;
1023 entry = irq_2_pin + entry->next;
1024 }
1025 printk("\n");
1026 }
1027
1028 printk(KERN_INFO ".................................... done.\n");
1029
1030 return;
1031 }
1032
1033 #if 0
1034
1035 static __apicdebuginit void print_APIC_bitfield (int base)
1036 {
1037 unsigned int v;
1038 int i, j;
1039
1040 if (apic_verbosity == APIC_QUIET)
1041 return;
1042
1043 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1044 for (i = 0; i < 8; i++) {
1045 v = apic_read(base + i*0x10);
1046 for (j = 0; j < 32; j++) {
1047 if (v & (1<<j))
1048 printk("1");
1049 else
1050 printk("0");
1051 }
1052 printk("\n");
1053 }
1054 }
1055
1056 void __apicdebuginit print_local_APIC(void * dummy)
1057 {
1058 unsigned int v, ver, maxlvt;
1059
1060 if (apic_verbosity == APIC_QUIET)
1061 return;
1062
1063 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1064 smp_processor_id(), hard_smp_processor_id());
1065 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1066 v = apic_read(APIC_LVR);
1067 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1068 ver = GET_APIC_VERSION(v);
1069 maxlvt = lapic_get_maxlvt();
1070
1071 v = apic_read(APIC_TASKPRI);
1072 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1073
1074 v = apic_read(APIC_ARBPRI);
1075 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1076 v & APIC_ARBPRI_MASK);
1077 v = apic_read(APIC_PROCPRI);
1078 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1079
1080 v = apic_read(APIC_EOI);
1081 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1082 v = apic_read(APIC_RRR);
1083 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1084 v = apic_read(APIC_LDR);
1085 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1086 v = apic_read(APIC_DFR);
1087 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1088 v = apic_read(APIC_SPIV);
1089 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1090
1091 printk(KERN_DEBUG "... APIC ISR field:\n");
1092 print_APIC_bitfield(APIC_ISR);
1093 printk(KERN_DEBUG "... APIC TMR field:\n");
1094 print_APIC_bitfield(APIC_TMR);
1095 printk(KERN_DEBUG "... APIC IRR field:\n");
1096 print_APIC_bitfield(APIC_IRR);
1097
1098 v = apic_read(APIC_ESR);
1099 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1100
1101 v = apic_read(APIC_ICR);
1102 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1103 v = apic_read(APIC_ICR2);
1104 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1105
1106 v = apic_read(APIC_LVTT);
1107 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1108
1109 if (maxlvt > 3) { /* PC is LVT#4. */
1110 v = apic_read(APIC_LVTPC);
1111 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1112 }
1113 v = apic_read(APIC_LVT0);
1114 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1115 v = apic_read(APIC_LVT1);
1116 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1117
1118 if (maxlvt > 2) { /* ERR is LVT#3. */
1119 v = apic_read(APIC_LVTERR);
1120 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1121 }
1122
1123 v = apic_read(APIC_TMICT);
1124 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1125 v = apic_read(APIC_TMCCT);
1126 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1127 v = apic_read(APIC_TDCR);
1128 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1129 printk("\n");
1130 }
1131
1132 void print_all_local_APICs (void)
1133 {
1134 on_each_cpu(print_local_APIC, NULL, 1, 1);
1135 }
1136
1137 void __apicdebuginit print_PIC(void)
1138 {
1139 unsigned int v;
1140 unsigned long flags;
1141
1142 if (apic_verbosity == APIC_QUIET)
1143 return;
1144
1145 printk(KERN_DEBUG "\nprinting PIC contents\n");
1146
1147 spin_lock_irqsave(&i8259A_lock, flags);
1148
1149 v = inb(0xa1) << 8 | inb(0x21);
1150 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1151
1152 v = inb(0xa0) << 8 | inb(0x20);
1153 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1154
1155 outb(0x0b,0xa0);
1156 outb(0x0b,0x20);
1157 v = inb(0xa0) << 8 | inb(0x20);
1158 outb(0x0a,0xa0);
1159 outb(0x0a,0x20);
1160
1161 spin_unlock_irqrestore(&i8259A_lock, flags);
1162
1163 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1164
1165 v = inb(0x4d1) << 8 | inb(0x4d0);
1166 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1167 }
1168
1169 #endif /* 0 */
1170
1171 void __init enable_IO_APIC(void)
1172 {
1173 union IO_APIC_reg_01 reg_01;
1174 int i8259_apic, i8259_pin;
1175 int i, apic;
1176 unsigned long flags;
1177
1178 for (i = 0; i < PIN_MAP_SIZE; i++) {
1179 irq_2_pin[i].pin = -1;
1180 irq_2_pin[i].next = 0;
1181 }
1182
1183 /*
1184 * The number of IO-APIC IRQ registers (== #pins):
1185 */
1186 for (apic = 0; apic < nr_ioapics; apic++) {
1187 spin_lock_irqsave(&ioapic_lock, flags);
1188 reg_01.raw = io_apic_read(apic, 1);
1189 spin_unlock_irqrestore(&ioapic_lock, flags);
1190 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1191 }
1192 for(apic = 0; apic < nr_ioapics; apic++) {
1193 int pin;
1194 /* See if any of the pins is in ExtINT mode */
1195 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1196 struct IO_APIC_route_entry entry;
1197 entry = ioapic_read_entry(apic, pin);
1198
1199 /* If the interrupt line is enabled and in ExtInt mode
1200 * I have found the pin where the i8259 is connected.
1201 */
1202 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1203 ioapic_i8259.apic = apic;
1204 ioapic_i8259.pin = pin;
1205 goto found_i8259;
1206 }
1207 }
1208 }
1209 found_i8259:
1210 /* Look to see what if the MP table has reported the ExtINT */
1211 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1212 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1213 /* Trust the MP table if nothing is setup in the hardware */
1214 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1215 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1216 ioapic_i8259.pin = i8259_pin;
1217 ioapic_i8259.apic = i8259_apic;
1218 }
1219 /* Complain if the MP table and the hardware disagree */
1220 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1221 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1222 {
1223 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1224 }
1225
1226 /*
1227 * Do not trust the IO-APIC being empty at bootup
1228 */
1229 clear_IO_APIC();
1230 }
1231
1232 /*
1233 * Not an __init, needed by the reboot code
1234 */
1235 void disable_IO_APIC(void)
1236 {
1237 /*
1238 * Clear the IO-APIC before rebooting:
1239 */
1240 clear_IO_APIC();
1241
1242 /*
1243 * If the i8259 is routed through an IOAPIC
1244 * Put that IOAPIC in virtual wire mode
1245 * so legacy interrupts can be delivered.
1246 */
1247 if (ioapic_i8259.pin != -1) {
1248 struct IO_APIC_route_entry entry;
1249
1250 memset(&entry, 0, sizeof(entry));
1251 entry.mask = 0; /* Enabled */
1252 entry.trigger = 0; /* Edge */
1253 entry.irr = 0;
1254 entry.polarity = 0; /* High */
1255 entry.delivery_status = 0;
1256 entry.dest_mode = 0; /* Physical */
1257 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1258 entry.vector = 0;
1259 entry.dest = GET_APIC_ID(read_apic_id());
1260
1261 /*
1262 * Add it to the IO-APIC irq-routing table:
1263 */
1264 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1265 }
1266
1267 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1268 }
1269
1270 /*
1271 * There is a nasty bug in some older SMP boards, their mptable lies
1272 * about the timer IRQ. We do the following to work around the situation:
1273 *
1274 * - timer IRQ defaults to IO-APIC IRQ
1275 * - if this function detects that timer IRQs are defunct, then we fall
1276 * back to ISA timer IRQs
1277 */
1278 static int __init timer_irq_works(void)
1279 {
1280 unsigned long t1 = jiffies;
1281 unsigned long flags;
1282
1283 local_save_flags(flags);
1284 local_irq_enable();
1285 /* Let ten ticks pass... */
1286 mdelay((10 * 1000) / HZ);
1287 local_irq_restore(flags);
1288
1289 /*
1290 * Expect a few ticks at least, to be sure some possible
1291 * glue logic does not lock up after one or two first
1292 * ticks in a non-ExtINT mode. Also the local APIC
1293 * might have cached one ExtINT interrupt. Finally, at
1294 * least one tick may be lost due to delays.
1295 */
1296
1297 /* jiffies wrap? */
1298 if (time_after(jiffies, t1 + 4))
1299 return 1;
1300 return 0;
1301 }
1302
1303 /*
1304 * In the SMP+IOAPIC case it might happen that there are an unspecified
1305 * number of pending IRQ events unhandled. These cases are very rare,
1306 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1307 * better to do it this way as thus we do not have to be aware of
1308 * 'pending' interrupts in the IRQ path, except at this point.
1309 */
1310 /*
1311 * Edge triggered needs to resend any interrupt
1312 * that was delayed but this is now handled in the device
1313 * independent code.
1314 */
1315
1316 /*
1317 * Starting up a edge-triggered IO-APIC interrupt is
1318 * nasty - we need to make sure that we get the edge.
1319 * If it is already asserted for some reason, we need
1320 * return 1 to indicate that is was pending.
1321 *
1322 * This is not complete - we should be able to fake
1323 * an edge even if it isn't on the 8259A...
1324 */
1325
1326 static unsigned int startup_ioapic_irq(unsigned int irq)
1327 {
1328 int was_pending = 0;
1329 unsigned long flags;
1330
1331 spin_lock_irqsave(&ioapic_lock, flags);
1332 if (irq < 16) {
1333 disable_8259A_irq(irq);
1334 if (i8259A_irq_pending(irq))
1335 was_pending = 1;
1336 }
1337 __unmask_IO_APIC_irq(irq);
1338 spin_unlock_irqrestore(&ioapic_lock, flags);
1339
1340 return was_pending;
1341 }
1342
1343 static int ioapic_retrigger_irq(unsigned int irq)
1344 {
1345 struct irq_cfg *cfg = &irq_cfg[irq];
1346 cpumask_t mask;
1347 unsigned long flags;
1348
1349 spin_lock_irqsave(&vector_lock, flags);
1350 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1351 send_IPI_mask(mask, cfg->vector);
1352 spin_unlock_irqrestore(&vector_lock, flags);
1353
1354 return 1;
1355 }
1356
1357 /*
1358 * Level and edge triggered IO-APIC interrupts need different handling,
1359 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1360 * handled with the level-triggered descriptor, but that one has slightly
1361 * more overhead. Level-triggered interrupts cannot be handled with the
1362 * edge-triggered handler, without risking IRQ storms and other ugly
1363 * races.
1364 */
1365
1366 #ifdef CONFIG_SMP
1367 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1368 {
1369 unsigned vector, me;
1370 ack_APIC_irq();
1371 exit_idle();
1372 irq_enter();
1373
1374 me = smp_processor_id();
1375 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1376 unsigned int irq;
1377 struct irq_desc *desc;
1378 struct irq_cfg *cfg;
1379 irq = __get_cpu_var(vector_irq)[vector];
1380 if (irq >= NR_IRQS)
1381 continue;
1382
1383 desc = irq_desc + irq;
1384 cfg = irq_cfg + irq;
1385 spin_lock(&desc->lock);
1386 if (!cfg->move_cleanup_count)
1387 goto unlock;
1388
1389 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1390 goto unlock;
1391
1392 __get_cpu_var(vector_irq)[vector] = -1;
1393 cfg->move_cleanup_count--;
1394 unlock:
1395 spin_unlock(&desc->lock);
1396 }
1397
1398 irq_exit();
1399 }
1400
1401 static void irq_complete_move(unsigned int irq)
1402 {
1403 struct irq_cfg *cfg = irq_cfg + irq;
1404 unsigned vector, me;
1405
1406 if (likely(!cfg->move_in_progress))
1407 return;
1408
1409 vector = ~get_irq_regs()->orig_ax;
1410 me = smp_processor_id();
1411 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1412 cpumask_t cleanup_mask;
1413
1414 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1415 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1416 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1417 cfg->move_in_progress = 0;
1418 }
1419 }
1420 #else
1421 static inline void irq_complete_move(unsigned int irq) {}
1422 #endif
1423
1424 static void ack_apic_edge(unsigned int irq)
1425 {
1426 irq_complete_move(irq);
1427 move_native_irq(irq);
1428 ack_APIC_irq();
1429 }
1430
1431 static void ack_apic_level(unsigned int irq)
1432 {
1433 int do_unmask_irq = 0;
1434
1435 irq_complete_move(irq);
1436 #ifdef CONFIG_GENERIC_PENDING_IRQ
1437 /* If we are moving the irq we need to mask it */
1438 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1439 do_unmask_irq = 1;
1440 mask_IO_APIC_irq(irq);
1441 }
1442 #endif
1443
1444 /*
1445 * We must acknowledge the irq before we move it or the acknowledge will
1446 * not propagate properly.
1447 */
1448 ack_APIC_irq();
1449
1450 /* Now we can move and renable the irq */
1451 if (unlikely(do_unmask_irq)) {
1452 /* Only migrate the irq if the ack has been received.
1453 *
1454 * On rare occasions the broadcast level triggered ack gets
1455 * delayed going to ioapics, and if we reprogram the
1456 * vector while Remote IRR is still set the irq will never
1457 * fire again.
1458 *
1459 * To prevent this scenario we read the Remote IRR bit
1460 * of the ioapic. This has two effects.
1461 * - On any sane system the read of the ioapic will
1462 * flush writes (and acks) going to the ioapic from
1463 * this cpu.
1464 * - We get to see if the ACK has actually been delivered.
1465 *
1466 * Based on failed experiments of reprogramming the
1467 * ioapic entry from outside of irq context starting
1468 * with masking the ioapic entry and then polling until
1469 * Remote IRR was clear before reprogramming the
1470 * ioapic I don't trust the Remote IRR bit to be
1471 * completey accurate.
1472 *
1473 * However there appears to be no other way to plug
1474 * this race, so if the Remote IRR bit is not
1475 * accurate and is causing problems then it is a hardware bug
1476 * and you can go talk to the chipset vendor about it.
1477 */
1478 if (!io_apic_level_ack_pending(irq))
1479 move_masked_irq(irq);
1480 unmask_IO_APIC_irq(irq);
1481 }
1482 }
1483
1484 static struct irq_chip ioapic_chip __read_mostly = {
1485 .name = "IO-APIC",
1486 .startup = startup_ioapic_irq,
1487 .mask = mask_IO_APIC_irq,
1488 .unmask = unmask_IO_APIC_irq,
1489 .ack = ack_apic_edge,
1490 .eoi = ack_apic_level,
1491 #ifdef CONFIG_SMP
1492 .set_affinity = set_ioapic_affinity_irq,
1493 #endif
1494 .retrigger = ioapic_retrigger_irq,
1495 };
1496
1497 static inline void init_IO_APIC_traps(void)
1498 {
1499 int irq;
1500
1501 /*
1502 * NOTE! The local APIC isn't very good at handling
1503 * multiple interrupts at the same interrupt level.
1504 * As the interrupt level is determined by taking the
1505 * vector number and shifting that right by 4, we
1506 * want to spread these out a bit so that they don't
1507 * all fall in the same interrupt level.
1508 *
1509 * Also, we've got to be careful not to trash gate
1510 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1511 */
1512 for (irq = 0; irq < NR_IRQS ; irq++) {
1513 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1514 /*
1515 * Hmm.. We don't have an entry for this,
1516 * so default to an old-fashioned 8259
1517 * interrupt if we can..
1518 */
1519 if (irq < 16)
1520 make_8259A_irq(irq);
1521 else
1522 /* Strange. Oh, well.. */
1523 irq_desc[irq].chip = &no_irq_chip;
1524 }
1525 }
1526 }
1527
1528 static void enable_lapic_irq (unsigned int irq)
1529 {
1530 unsigned long v;
1531
1532 v = apic_read(APIC_LVT0);
1533 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1534 }
1535
1536 static void disable_lapic_irq (unsigned int irq)
1537 {
1538 unsigned long v;
1539
1540 v = apic_read(APIC_LVT0);
1541 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1542 }
1543
1544 static void ack_lapic_irq (unsigned int irq)
1545 {
1546 ack_APIC_irq();
1547 }
1548
1549 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1550
1551 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1552 .name = "local-APIC",
1553 .typename = "local-APIC-edge",
1554 .startup = NULL, /* startup_irq() not used for IRQ0 */
1555 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1556 .enable = enable_lapic_irq,
1557 .disable = disable_lapic_irq,
1558 .ack = ack_lapic_irq,
1559 .end = end_lapic_irq,
1560 };
1561
1562 static void __init setup_nmi(void)
1563 {
1564 /*
1565 * Dirty trick to enable the NMI watchdog ...
1566 * We put the 8259A master into AEOI mode and
1567 * unmask on all local APICs LVT0 as NMI.
1568 *
1569 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1570 * is from Maciej W. Rozycki - so we do not have to EOI from
1571 * the NMI handler or the timer interrupt.
1572 */
1573 printk(KERN_INFO "activating NMI Watchdog ...");
1574
1575 enable_NMI_through_LVT0();
1576
1577 printk(" done.\n");
1578 }
1579
1580 /*
1581 * This looks a bit hackish but it's about the only one way of sending
1582 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1583 * not support the ExtINT mode, unfortunately. We need to send these
1584 * cycles as some i82489DX-based boards have glue logic that keeps the
1585 * 8259A interrupt line asserted until INTA. --macro
1586 */
1587 static inline void __init unlock_ExtINT_logic(void)
1588 {
1589 int apic, pin, i;
1590 struct IO_APIC_route_entry entry0, entry1;
1591 unsigned char save_control, save_freq_select;
1592
1593 pin = find_isa_irq_pin(8, mp_INT);
1594 apic = find_isa_irq_apic(8, mp_INT);
1595 if (pin == -1)
1596 return;
1597
1598 entry0 = ioapic_read_entry(apic, pin);
1599
1600 clear_IO_APIC_pin(apic, pin);
1601
1602 memset(&entry1, 0, sizeof(entry1));
1603
1604 entry1.dest_mode = 0; /* physical delivery */
1605 entry1.mask = 0; /* unmask IRQ now */
1606 entry1.dest = hard_smp_processor_id();
1607 entry1.delivery_mode = dest_ExtINT;
1608 entry1.polarity = entry0.polarity;
1609 entry1.trigger = 0;
1610 entry1.vector = 0;
1611
1612 ioapic_write_entry(apic, pin, entry1);
1613
1614 save_control = CMOS_READ(RTC_CONTROL);
1615 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1616 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1617 RTC_FREQ_SELECT);
1618 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1619
1620 i = 100;
1621 while (i-- > 0) {
1622 mdelay(10);
1623 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1624 i -= 10;
1625 }
1626
1627 CMOS_WRITE(save_control, RTC_CONTROL);
1628 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1629 clear_IO_APIC_pin(apic, pin);
1630
1631 ioapic_write_entry(apic, pin, entry0);
1632 }
1633
1634 /*
1635 * This code may look a bit paranoid, but it's supposed to cooperate with
1636 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1637 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1638 * fanatically on his truly buggy board.
1639 *
1640 * FIXME: really need to revamp this for modern platforms only.
1641 */
1642 static inline void __init check_timer(void)
1643 {
1644 struct irq_cfg *cfg = irq_cfg + 0;
1645 int apic1, pin1, apic2, pin2;
1646 unsigned long flags;
1647
1648 local_irq_save(flags);
1649
1650 /*
1651 * get/set the timer IRQ vector:
1652 */
1653 disable_8259A_irq(0);
1654 assign_irq_vector(0, TARGET_CPUS);
1655
1656 /*
1657 * As IRQ0 is to be enabled in the 8259A, the virtual
1658 * wire has to be disabled in the local APIC.
1659 */
1660 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1661 init_8259A(1);
1662
1663 pin1 = find_isa_irq_pin(0, mp_INT);
1664 apic1 = find_isa_irq_apic(0, mp_INT);
1665 pin2 = ioapic_i8259.pin;
1666 apic2 = ioapic_i8259.apic;
1667
1668 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1669 cfg->vector, apic1, pin1, apic2, pin2);
1670
1671 if (pin1 != -1) {
1672 /*
1673 * Ok, does IRQ0 through the IOAPIC work?
1674 */
1675 unmask_IO_APIC_irq(0);
1676 if (!no_timer_check && timer_irq_works()) {
1677 nmi_watchdog_default();
1678 if (nmi_watchdog == NMI_IO_APIC) {
1679 setup_nmi();
1680 enable_8259A_irq(0);
1681 }
1682 if (disable_timer_pin_1 > 0)
1683 clear_IO_APIC_pin(0, pin1);
1684 goto out;
1685 }
1686 clear_IO_APIC_pin(apic1, pin1);
1687 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1688 "connected to IO-APIC\n");
1689 }
1690
1691 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1692 "through the 8259A ... ");
1693 if (pin2 != -1) {
1694 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1695 apic2, pin2);
1696 /*
1697 * legacy devices should be connected to IO APIC #0
1698 */
1699 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1700 enable_8259A_irq(0);
1701 if (timer_irq_works()) {
1702 apic_printk(APIC_VERBOSE," works.\n");
1703 nmi_watchdog_default();
1704 if (nmi_watchdog == NMI_IO_APIC) {
1705 disable_8259A_irq(0);
1706 setup_nmi();
1707 enable_8259A_irq(0);
1708 }
1709 goto out;
1710 }
1711 /*
1712 * Cleanup, just in case ...
1713 */
1714 disable_8259A_irq(0);
1715 clear_IO_APIC_pin(apic2, pin2);
1716 }
1717 apic_printk(APIC_VERBOSE," failed.\n");
1718
1719 if (nmi_watchdog == NMI_IO_APIC) {
1720 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1721 nmi_watchdog = 0;
1722 }
1723
1724 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1725
1726 irq_desc[0].chip = &lapic_irq_type;
1727 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1728 enable_8259A_irq(0);
1729
1730 if (timer_irq_works()) {
1731 apic_printk(APIC_VERBOSE," works.\n");
1732 goto out;
1733 }
1734 disable_8259A_irq(0);
1735 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1736 apic_printk(APIC_VERBOSE," failed.\n");
1737
1738 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1739
1740 init_8259A(0);
1741 make_8259A_irq(0);
1742 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1743
1744 unlock_ExtINT_logic();
1745
1746 if (timer_irq_works()) {
1747 apic_printk(APIC_VERBOSE," works.\n");
1748 goto out;
1749 }
1750 apic_printk(APIC_VERBOSE," failed :(.\n");
1751 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1752 out:
1753 local_irq_restore(flags);
1754 }
1755
1756 static int __init notimercheck(char *s)
1757 {
1758 no_timer_check = 1;
1759 return 1;
1760 }
1761 __setup("no_timer_check", notimercheck);
1762
1763 /*
1764 *
1765 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1766 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1767 * Linux doesn't really care, as it's not actually used
1768 * for any interrupt handling anyway.
1769 */
1770 #define PIC_IRQS (1<<2)
1771
1772 void __init setup_IO_APIC(void)
1773 {
1774
1775 /*
1776 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1777 */
1778
1779 if (acpi_ioapic)
1780 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1781 else
1782 io_apic_irqs = ~PIC_IRQS;
1783
1784 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1785
1786 sync_Arb_IDs();
1787 setup_IO_APIC_irqs();
1788 init_IO_APIC_traps();
1789 check_timer();
1790 if (!acpi_ioapic)
1791 print_IO_APIC();
1792 }
1793
1794 struct sysfs_ioapic_data {
1795 struct sys_device dev;
1796 struct IO_APIC_route_entry entry[0];
1797 };
1798 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1799
1800 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1801 {
1802 struct IO_APIC_route_entry *entry;
1803 struct sysfs_ioapic_data *data;
1804 int i;
1805
1806 data = container_of(dev, struct sysfs_ioapic_data, dev);
1807 entry = data->entry;
1808 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1809 *entry = ioapic_read_entry(dev->id, i);
1810
1811 return 0;
1812 }
1813
1814 static int ioapic_resume(struct sys_device *dev)
1815 {
1816 struct IO_APIC_route_entry *entry;
1817 struct sysfs_ioapic_data *data;
1818 unsigned long flags;
1819 union IO_APIC_reg_00 reg_00;
1820 int i;
1821
1822 data = container_of(dev, struct sysfs_ioapic_data, dev);
1823 entry = data->entry;
1824
1825 spin_lock_irqsave(&ioapic_lock, flags);
1826 reg_00.raw = io_apic_read(dev->id, 0);
1827 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1828 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1829 io_apic_write(dev->id, 0, reg_00.raw);
1830 }
1831 spin_unlock_irqrestore(&ioapic_lock, flags);
1832 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1833 ioapic_write_entry(dev->id, i, entry[i]);
1834
1835 return 0;
1836 }
1837
1838 static struct sysdev_class ioapic_sysdev_class = {
1839 .name = "ioapic",
1840 .suspend = ioapic_suspend,
1841 .resume = ioapic_resume,
1842 };
1843
1844 static int __init ioapic_init_sysfs(void)
1845 {
1846 struct sys_device * dev;
1847 int i, size, error;
1848
1849 error = sysdev_class_register(&ioapic_sysdev_class);
1850 if (error)
1851 return error;
1852
1853 for (i = 0; i < nr_ioapics; i++ ) {
1854 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1855 * sizeof(struct IO_APIC_route_entry);
1856 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1857 if (!mp_ioapic_data[i]) {
1858 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1859 continue;
1860 }
1861 dev = &mp_ioapic_data[i]->dev;
1862 dev->id = i;
1863 dev->cls = &ioapic_sysdev_class;
1864 error = sysdev_register(dev);
1865 if (error) {
1866 kfree(mp_ioapic_data[i]);
1867 mp_ioapic_data[i] = NULL;
1868 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1869 continue;
1870 }
1871 }
1872
1873 return 0;
1874 }
1875
1876 device_initcall(ioapic_init_sysfs);
1877
1878 /*
1879 * Dynamic irq allocate and deallocation
1880 */
1881 int create_irq(void)
1882 {
1883 /* Allocate an unused irq */
1884 int irq;
1885 int new;
1886 unsigned long flags;
1887
1888 irq = -ENOSPC;
1889 spin_lock_irqsave(&vector_lock, flags);
1890 for (new = (NR_IRQS - 1); new >= 0; new--) {
1891 if (platform_legacy_irq(new))
1892 continue;
1893 if (irq_cfg[new].vector != 0)
1894 continue;
1895 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1896 irq = new;
1897 break;
1898 }
1899 spin_unlock_irqrestore(&vector_lock, flags);
1900
1901 if (irq >= 0) {
1902 dynamic_irq_init(irq);
1903 }
1904 return irq;
1905 }
1906
1907 void destroy_irq(unsigned int irq)
1908 {
1909 unsigned long flags;
1910
1911 dynamic_irq_cleanup(irq);
1912
1913 spin_lock_irqsave(&vector_lock, flags);
1914 __clear_irq_vector(irq);
1915 spin_unlock_irqrestore(&vector_lock, flags);
1916 }
1917
1918 /*
1919 * MSI message composition
1920 */
1921 #ifdef CONFIG_PCI_MSI
1922 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1923 {
1924 struct irq_cfg *cfg = irq_cfg + irq;
1925 int err;
1926 unsigned dest;
1927 cpumask_t tmp;
1928
1929 tmp = TARGET_CPUS;
1930 err = assign_irq_vector(irq, tmp);
1931 if (!err) {
1932 cpus_and(tmp, cfg->domain, tmp);
1933 dest = cpu_mask_to_apicid(tmp);
1934
1935 msg->address_hi = MSI_ADDR_BASE_HI;
1936 msg->address_lo =
1937 MSI_ADDR_BASE_LO |
1938 ((INT_DEST_MODE == 0) ?
1939 MSI_ADDR_DEST_MODE_PHYSICAL:
1940 MSI_ADDR_DEST_MODE_LOGICAL) |
1941 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1942 MSI_ADDR_REDIRECTION_CPU:
1943 MSI_ADDR_REDIRECTION_LOWPRI) |
1944 MSI_ADDR_DEST_ID(dest);
1945
1946 msg->data =
1947 MSI_DATA_TRIGGER_EDGE |
1948 MSI_DATA_LEVEL_ASSERT |
1949 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1950 MSI_DATA_DELIVERY_FIXED:
1951 MSI_DATA_DELIVERY_LOWPRI) |
1952 MSI_DATA_VECTOR(cfg->vector);
1953 }
1954 return err;
1955 }
1956
1957 #ifdef CONFIG_SMP
1958 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1959 {
1960 struct irq_cfg *cfg = irq_cfg + irq;
1961 struct msi_msg msg;
1962 unsigned int dest;
1963 cpumask_t tmp;
1964
1965 cpus_and(tmp, mask, cpu_online_map);
1966 if (cpus_empty(tmp))
1967 return;
1968
1969 if (assign_irq_vector(irq, mask))
1970 return;
1971
1972 cpus_and(tmp, cfg->domain, mask);
1973 dest = cpu_mask_to_apicid(tmp);
1974
1975 read_msi_msg(irq, &msg);
1976
1977 msg.data &= ~MSI_DATA_VECTOR_MASK;
1978 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1979 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1980 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1981
1982 write_msi_msg(irq, &msg);
1983 irq_desc[irq].affinity = mask;
1984 }
1985 #endif /* CONFIG_SMP */
1986
1987 /*
1988 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1989 * which implement the MSI or MSI-X Capability Structure.
1990 */
1991 static struct irq_chip msi_chip = {
1992 .name = "PCI-MSI",
1993 .unmask = unmask_msi_irq,
1994 .mask = mask_msi_irq,
1995 .ack = ack_apic_edge,
1996 #ifdef CONFIG_SMP
1997 .set_affinity = set_msi_irq_affinity,
1998 #endif
1999 .retrigger = ioapic_retrigger_irq,
2000 };
2001
2002 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2003 {
2004 struct msi_msg msg;
2005 int irq, ret;
2006 irq = create_irq();
2007 if (irq < 0)
2008 return irq;
2009
2010 ret = msi_compose_msg(dev, irq, &msg);
2011 if (ret < 0) {
2012 destroy_irq(irq);
2013 return ret;
2014 }
2015
2016 set_irq_msi(irq, desc);
2017 write_msi_msg(irq, &msg);
2018
2019 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2020
2021 return 0;
2022 }
2023
2024 void arch_teardown_msi_irq(unsigned int irq)
2025 {
2026 destroy_irq(irq);
2027 }
2028
2029 #ifdef CONFIG_DMAR
2030 #ifdef CONFIG_SMP
2031 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2032 {
2033 struct irq_cfg *cfg = irq_cfg + irq;
2034 struct msi_msg msg;
2035 unsigned int dest;
2036 cpumask_t tmp;
2037
2038 cpus_and(tmp, mask, cpu_online_map);
2039 if (cpus_empty(tmp))
2040 return;
2041
2042 if (assign_irq_vector(irq, mask))
2043 return;
2044
2045 cpus_and(tmp, cfg->domain, mask);
2046 dest = cpu_mask_to_apicid(tmp);
2047
2048 dmar_msi_read(irq, &msg);
2049
2050 msg.data &= ~MSI_DATA_VECTOR_MASK;
2051 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2052 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2053 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2054
2055 dmar_msi_write(irq, &msg);
2056 irq_desc[irq].affinity = mask;
2057 }
2058 #endif /* CONFIG_SMP */
2059
2060 struct irq_chip dmar_msi_type = {
2061 .name = "DMAR_MSI",
2062 .unmask = dmar_msi_unmask,
2063 .mask = dmar_msi_mask,
2064 .ack = ack_apic_edge,
2065 #ifdef CONFIG_SMP
2066 .set_affinity = dmar_msi_set_affinity,
2067 #endif
2068 .retrigger = ioapic_retrigger_irq,
2069 };
2070
2071 int arch_setup_dmar_msi(unsigned int irq)
2072 {
2073 int ret;
2074 struct msi_msg msg;
2075
2076 ret = msi_compose_msg(NULL, irq, &msg);
2077 if (ret < 0)
2078 return ret;
2079 dmar_msi_write(irq, &msg);
2080 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2081 "edge");
2082 return 0;
2083 }
2084 #endif
2085
2086 #endif /* CONFIG_PCI_MSI */
2087 /*
2088 * Hypertransport interrupt support
2089 */
2090 #ifdef CONFIG_HT_IRQ
2091
2092 #ifdef CONFIG_SMP
2093
2094 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2095 {
2096 struct ht_irq_msg msg;
2097 fetch_ht_irq_msg(irq, &msg);
2098
2099 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2100 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2101
2102 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2103 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2104
2105 write_ht_irq_msg(irq, &msg);
2106 }
2107
2108 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2109 {
2110 struct irq_cfg *cfg = irq_cfg + irq;
2111 unsigned int dest;
2112 cpumask_t tmp;
2113
2114 cpus_and(tmp, mask, cpu_online_map);
2115 if (cpus_empty(tmp))
2116 return;
2117
2118 if (assign_irq_vector(irq, mask))
2119 return;
2120
2121 cpus_and(tmp, cfg->domain, mask);
2122 dest = cpu_mask_to_apicid(tmp);
2123
2124 target_ht_irq(irq, dest, cfg->vector);
2125 irq_desc[irq].affinity = mask;
2126 }
2127 #endif
2128
2129 static struct irq_chip ht_irq_chip = {
2130 .name = "PCI-HT",
2131 .mask = mask_ht_irq,
2132 .unmask = unmask_ht_irq,
2133 .ack = ack_apic_edge,
2134 #ifdef CONFIG_SMP
2135 .set_affinity = set_ht_irq_affinity,
2136 #endif
2137 .retrigger = ioapic_retrigger_irq,
2138 };
2139
2140 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2141 {
2142 struct irq_cfg *cfg = irq_cfg + irq;
2143 int err;
2144 cpumask_t tmp;
2145
2146 tmp = TARGET_CPUS;
2147 err = assign_irq_vector(irq, tmp);
2148 if (!err) {
2149 struct ht_irq_msg msg;
2150 unsigned dest;
2151
2152 cpus_and(tmp, cfg->domain, tmp);
2153 dest = cpu_mask_to_apicid(tmp);
2154
2155 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2156
2157 msg.address_lo =
2158 HT_IRQ_LOW_BASE |
2159 HT_IRQ_LOW_DEST_ID(dest) |
2160 HT_IRQ_LOW_VECTOR(cfg->vector) |
2161 ((INT_DEST_MODE == 0) ?
2162 HT_IRQ_LOW_DM_PHYSICAL :
2163 HT_IRQ_LOW_DM_LOGICAL) |
2164 HT_IRQ_LOW_RQEOI_EDGE |
2165 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2166 HT_IRQ_LOW_MT_FIXED :
2167 HT_IRQ_LOW_MT_ARBITRATED) |
2168 HT_IRQ_LOW_IRQ_MASKED;
2169
2170 write_ht_irq_msg(irq, &msg);
2171
2172 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2173 handle_edge_irq, "edge");
2174 }
2175 return err;
2176 }
2177 #endif /* CONFIG_HT_IRQ */
2178
2179 /* --------------------------------------------------------------------------
2180 ACPI-based IOAPIC Configuration
2181 -------------------------------------------------------------------------- */
2182
2183 #ifdef CONFIG_ACPI
2184
2185 #define IO_APIC_MAX_ID 0xFE
2186
2187 int __init io_apic_get_redir_entries (int ioapic)
2188 {
2189 union IO_APIC_reg_01 reg_01;
2190 unsigned long flags;
2191
2192 spin_lock_irqsave(&ioapic_lock, flags);
2193 reg_01.raw = io_apic_read(ioapic, 1);
2194 spin_unlock_irqrestore(&ioapic_lock, flags);
2195
2196 return reg_01.bits.entries;
2197 }
2198
2199
2200 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2201 {
2202 if (!IO_APIC_IRQ(irq)) {
2203 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2204 ioapic);
2205 return -EINVAL;
2206 }
2207
2208 /*
2209 * IRQs < 16 are already in the irq_2_pin[] map
2210 */
2211 if (irq >= 16)
2212 add_pin_to_irq(irq, ioapic, pin);
2213
2214 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2215
2216 return 0;
2217 }
2218
2219
2220 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2221 {
2222 int i;
2223
2224 if (skip_ioapic_setup)
2225 return -1;
2226
2227 for (i = 0; i < mp_irq_entries; i++)
2228 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2229 mp_irqs[i].mpc_srcbusirq == bus_irq)
2230 break;
2231 if (i >= mp_irq_entries)
2232 return -1;
2233
2234 *trigger = irq_trigger(i);
2235 *polarity = irq_polarity(i);
2236 return 0;
2237 }
2238
2239 #endif /* CONFIG_ACPI */
2240
2241 /*
2242 * This function currently is only a helper for the i386 smp boot process where
2243 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2244 * so mask in all cases should simply be TARGET_CPUS
2245 */
2246 #ifdef CONFIG_SMP
2247 void __init setup_ioapic_dest(void)
2248 {
2249 int pin, ioapic, irq, irq_entry;
2250
2251 if (skip_ioapic_setup == 1)
2252 return;
2253
2254 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2255 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2256 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2257 if (irq_entry == -1)
2258 continue;
2259 irq = pin_2_irq(irq_entry, ioapic, pin);
2260
2261 /* setup_IO_APIC_irqs could fail to get vector for some device
2262 * when you have too many devices, because at that time only boot
2263 * cpu is online.
2264 */
2265 if (!irq_cfg[irq].vector)
2266 setup_IO_APIC_irq(ioapic, pin, irq,
2267 irq_trigger(irq_entry),
2268 irq_polarity(irq_entry));
2269 else
2270 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2271 }
2272
2273 }
2274 }
2275 #endif
2276
2277 #define IOAPIC_RESOURCE_NAME_SIZE 11
2278
2279 static struct resource *ioapic_resources;
2280
2281 static struct resource * __init ioapic_setup_resources(void)
2282 {
2283 unsigned long n;
2284 struct resource *res;
2285 char *mem;
2286 int i;
2287
2288 if (nr_ioapics <= 0)
2289 return NULL;
2290
2291 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2292 n *= nr_ioapics;
2293
2294 mem = alloc_bootmem(n);
2295 res = (void *)mem;
2296
2297 if (mem != NULL) {
2298 mem += sizeof(struct resource) * nr_ioapics;
2299
2300 for (i = 0; i < nr_ioapics; i++) {
2301 res[i].name = mem;
2302 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2303 sprintf(mem, "IOAPIC %u", i);
2304 mem += IOAPIC_RESOURCE_NAME_SIZE;
2305 }
2306 }
2307
2308 ioapic_resources = res;
2309
2310 return res;
2311 }
2312
2313 void __init ioapic_init_mappings(void)
2314 {
2315 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2316 struct resource *ioapic_res;
2317 int i;
2318
2319 ioapic_res = ioapic_setup_resources();
2320 for (i = 0; i < nr_ioapics; i++) {
2321 if (smp_found_config) {
2322 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2323 } else {
2324 ioapic_phys = (unsigned long)
2325 alloc_bootmem_pages(PAGE_SIZE);
2326 ioapic_phys = __pa(ioapic_phys);
2327 }
2328 set_fixmap_nocache(idx, ioapic_phys);
2329 apic_printk(APIC_VERBOSE,
2330 "mapped IOAPIC to %016lx (%016lx)\n",
2331 __fix_to_virt(idx), ioapic_phys);
2332 idx++;
2333
2334 if (ioapic_res != NULL) {
2335 ioapic_res->start = ioapic_phys;
2336 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2337 ioapic_res++;
2338 }
2339 }
2340 }
2341
2342 static int __init ioapic_insert_resources(void)
2343 {
2344 int i;
2345 struct resource *r = ioapic_resources;
2346
2347 if (!r) {
2348 printk(KERN_ERR
2349 "IO APIC resources could be not be allocated.\n");
2350 return -1;
2351 }
2352
2353 for (i = 0; i < nr_ioapics; i++) {
2354 insert_resource(&iomem_resource, r);
2355 r++;
2356 }
2357
2358 return 0;
2359 }
2360
2361 /* Insert the IO APIC resources after PCI initialization has occured to handle
2362 * IO APICS that are mapped in on a BAR in PCI space. */
2363 late_initcall(ioapic_insert_resources);
2364
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