2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
46 #include <asm/proto.h>
50 #include <asm/msidef.h>
51 #include <asm/hypertransport.h>
52 #include <asm/irq_remapping.h>
55 #include <mach_apic.h>
60 unsigned move_cleanup_count
;
62 u8 move_in_progress
: 1;
65 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
66 static struct irq_cfg irq_cfg
[NR_IRQS
] __read_mostly
= {
67 [0] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
68 [1] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
69 [2] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
70 [3] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
71 [4] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
72 [5] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
73 [6] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
74 [7] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
75 [8] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
76 [9] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
77 [10] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
78 [11] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
79 [12] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
80 [13] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
81 [14] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
82 [15] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
85 static int assign_irq_vector(int irq
, cpumask_t mask
);
87 int first_system_vector
= 0xfe;
89 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
91 #define __apicdebuginit __init
93 int sis_apic_bug
; /* not actually supported, dummy for compile */
95 static int no_timer_check
;
97 static int disable_timer_pin_1 __initdata
;
99 static bool mask_ioapic_irq_2 __initdata
;
101 void __init
force_mask_ioapic_irq_2(void)
103 mask_ioapic_irq_2
= true;
106 int timer_through_8259 __initdata
;
108 /* Where if anywhere is the i8259 connect in external int mode */
109 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
111 static DEFINE_SPINLOCK(ioapic_lock
);
112 DEFINE_SPINLOCK(vector_lock
);
115 * # of IRQ routing registers
117 int nr_ioapic_registers
[MAX_IO_APICS
];
119 /* I/O APIC RTE contents at the OS boot up */
120 struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
122 /* I/O APIC entries */
123 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
126 /* MP IRQ source entries */
127 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
129 /* # of MP IRQ source entries */
132 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
135 * Rough estimation of how many shared IRQs there are, can
136 * be changed anytime.
138 #define MAX_PLUS_SHARED_IRQS NR_IRQS
139 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
142 * This is performance-critical, we want to do it O(1)
144 * the indexing order of this array favors 1:1 mappings
145 * between pins and IRQs.
148 static struct irq_pin_list
{
149 short apic
, pin
, next
;
150 } irq_2_pin
[PIN_MAP_SIZE
];
154 unsigned int unused
[3];
158 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
160 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
161 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
164 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
166 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
167 writel(reg
, &io_apic
->index
);
168 return readl(&io_apic
->data
);
171 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
173 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
174 writel(reg
, &io_apic
->index
);
175 writel(value
, &io_apic
->data
);
179 * Re-write a value: to be used for read-modify-write
180 * cycles where the read already set up the index register.
182 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
184 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
185 writel(value
, &io_apic
->data
);
188 static bool io_apic_level_ack_pending(unsigned int irq
)
190 struct irq_pin_list
*entry
;
193 spin_lock_irqsave(&ioapic_lock
, flags
);
194 entry
= irq_2_pin
+ irq
;
202 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
203 /* Is the remote IRR bit set? */
204 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
205 spin_unlock_irqrestore(&ioapic_lock
, flags
);
210 entry
= irq_2_pin
+ entry
->next
;
212 spin_unlock_irqrestore(&ioapic_lock
, flags
);
218 * Synchronize the IO-APIC and the CPU by doing
219 * a dummy read from the IO-APIC
221 static inline void io_apic_sync(unsigned int apic
)
223 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
224 readl(&io_apic
->data
);
227 #define __DO_ACTION(R, ACTION, FINAL) \
231 struct irq_pin_list *entry = irq_2_pin + irq; \
233 BUG_ON(irq >= NR_IRQS); \
239 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
241 io_apic_modify(entry->apic, reg); \
245 entry = irq_2_pin + entry->next; \
250 struct { u32 w1
, w2
; };
251 struct IO_APIC_route_entry entry
;
254 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
256 union entry_union eu
;
258 spin_lock_irqsave(&ioapic_lock
, flags
);
259 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
260 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
261 spin_unlock_irqrestore(&ioapic_lock
, flags
);
266 * When we write a new IO APIC routing entry, we need to write the high
267 * word first! If the mask bit in the low word is clear, we will enable
268 * the interrupt, and we need to make sure the entry is fully populated
269 * before that happens.
272 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
274 union entry_union eu
;
276 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
277 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
280 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
283 spin_lock_irqsave(&ioapic_lock
, flags
);
284 __ioapic_write_entry(apic
, pin
, e
);
285 spin_unlock_irqrestore(&ioapic_lock
, flags
);
289 * When we mask an IO APIC routing entry, we need to write the low
290 * word first, in order to set the mask bit before we change the
293 static void ioapic_mask_entry(int apic
, int pin
)
296 union entry_union eu
= { .entry
.mask
= 1 };
298 spin_lock_irqsave(&ioapic_lock
, flags
);
299 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
300 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
301 spin_unlock_irqrestore(&ioapic_lock
, flags
);
305 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
308 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
310 BUG_ON(irq
>= NR_IRQS
);
318 * With interrupt-remapping, destination information comes
319 * from interrupt-remapping table entry.
321 if (!irq_remapped(irq
))
322 io_apic_write(apic
, 0x11 + pin
*2, dest
);
323 reg
= io_apic_read(apic
, 0x10 + pin
*2);
324 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
326 io_apic_modify(apic
, reg
);
329 entry
= irq_2_pin
+ entry
->next
;
333 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
335 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
340 cpus_and(tmp
, mask
, cpu_online_map
);
344 if (assign_irq_vector(irq
, mask
))
347 cpus_and(tmp
, cfg
->domain
, mask
);
348 dest
= cpu_mask_to_apicid(tmp
);
351 * Only the high 8 bits are valid.
353 dest
= SET_APIC_LOGICAL_ID(dest
);
355 spin_lock_irqsave(&ioapic_lock
, flags
);
356 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
357 irq_desc
[irq
].affinity
= mask
;
358 spin_unlock_irqrestore(&ioapic_lock
, flags
);
363 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
364 * shared ISA-space IRQs, so we have to support them. We are super
365 * fast in the common case, and fast for shared ISA-space IRQs.
367 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
369 static int first_free_entry
= NR_IRQS
;
370 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
372 BUG_ON(irq
>= NR_IRQS
);
374 entry
= irq_2_pin
+ entry
->next
;
376 if (entry
->pin
!= -1) {
377 entry
->next
= first_free_entry
;
378 entry
= irq_2_pin
+ entry
->next
;
379 if (++first_free_entry
>= PIN_MAP_SIZE
)
380 panic("io_apic.c: ran out of irq_2_pin entries!");
387 * Reroute an IRQ to a different pin.
389 static void __init
replace_pin_at_irq(unsigned int irq
,
390 int oldapic
, int oldpin
,
391 int newapic
, int newpin
)
393 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
396 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
397 entry
->apic
= newapic
;
402 entry
= irq_2_pin
+ entry
->next
;
407 #define DO_ACTION(name,R,ACTION, FINAL) \
409 static void name##_IO_APIC_irq (unsigned int irq) \
410 __DO_ACTION(R, ACTION, FINAL)
413 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, io_apic_sync(entry
->apic
))
416 DO_ACTION(__unmask
, 0, &= ~IO_APIC_REDIR_MASKED
, )
418 static void mask_IO_APIC_irq (unsigned int irq
)
422 spin_lock_irqsave(&ioapic_lock
, flags
);
423 __mask_IO_APIC_irq(irq
);
424 spin_unlock_irqrestore(&ioapic_lock
, flags
);
427 static void unmask_IO_APIC_irq (unsigned int irq
)
431 spin_lock_irqsave(&ioapic_lock
, flags
);
432 __unmask_IO_APIC_irq(irq
);
433 spin_unlock_irqrestore(&ioapic_lock
, flags
);
436 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
438 struct IO_APIC_route_entry entry
;
440 /* Check delivery_mode to be sure we're not clearing an SMI pin */
441 entry
= ioapic_read_entry(apic
, pin
);
442 if (entry
.delivery_mode
== dest_SMI
)
445 * Disable it in the IO-APIC irq-routing table:
447 ioapic_mask_entry(apic
, pin
);
450 static void clear_IO_APIC (void)
454 for (apic
= 0; apic
< nr_ioapics
; apic
++)
455 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
456 clear_IO_APIC_pin(apic
, pin
);
460 * Saves and masks all the unmasked IO-APIC RTE's
462 int save_mask_IO_APIC_setup(void)
464 union IO_APIC_reg_01 reg_01
;
469 * The number of IO-APIC IRQ registers (== #pins):
471 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
472 spin_lock_irqsave(&ioapic_lock
, flags
);
473 reg_01
.raw
= io_apic_read(apic
, 1);
474 spin_unlock_irqrestore(&ioapic_lock
, flags
);
475 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
478 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
479 early_ioapic_entries
[apic
] =
480 kzalloc(sizeof(struct IO_APIC_route_entry
) *
481 nr_ioapic_registers
[apic
], GFP_KERNEL
);
482 if (!early_ioapic_entries
[apic
])
486 for (apic
= 0; apic
< nr_ioapics
; apic
++)
487 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
488 struct IO_APIC_route_entry entry
;
490 entry
= early_ioapic_entries
[apic
][pin
] =
491 ioapic_read_entry(apic
, pin
);
494 ioapic_write_entry(apic
, pin
, entry
);
500 void restore_IO_APIC_setup(void)
504 for (apic
= 0; apic
< nr_ioapics
; apic
++)
505 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
506 ioapic_write_entry(apic
, pin
,
507 early_ioapic_entries
[apic
][pin
]);
510 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
513 * for now plain restore of previous settings.
514 * TBD: In the case of OS enabling interrupt-remapping,
515 * IO-APIC RTE's need to be setup to point to interrupt-remapping
516 * table entries. for now, do a plain restore, and wait for
517 * the setup_IO_APIC_irqs() to do proper initialization.
519 restore_IO_APIC_setup();
522 int skip_ioapic_setup
;
525 static int __init
parse_noapic(char *str
)
527 disable_ioapic_setup();
530 early_param("noapic", parse_noapic
);
532 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
533 static int __init
disable_timer_pin_setup(char *arg
)
535 disable_timer_pin_1
= 1;
538 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
542 * Find the IRQ entry number of a certain pin.
544 static int find_irq_entry(int apic
, int pin
, int type
)
548 for (i
= 0; i
< mp_irq_entries
; i
++)
549 if (mp_irqs
[i
].mp_irqtype
== type
&&
550 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
551 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
552 mp_irqs
[i
].mp_dstirq
== pin
)
559 * Find the pin to which IRQ[irq] (ISA) is connected
561 static int __init
find_isa_irq_pin(int irq
, int type
)
565 for (i
= 0; i
< mp_irq_entries
; i
++) {
566 int lbus
= mp_irqs
[i
].mp_srcbus
;
568 if (test_bit(lbus
, mp_bus_not_pci
) &&
569 (mp_irqs
[i
].mp_irqtype
== type
) &&
570 (mp_irqs
[i
].mp_srcbusirq
== irq
))
572 return mp_irqs
[i
].mp_dstirq
;
577 static int __init
find_isa_irq_apic(int irq
, int type
)
581 for (i
= 0; i
< mp_irq_entries
; i
++) {
582 int lbus
= mp_irqs
[i
].mp_srcbus
;
584 if (test_bit(lbus
, mp_bus_not_pci
) &&
585 (mp_irqs
[i
].mp_irqtype
== type
) &&
586 (mp_irqs
[i
].mp_srcbusirq
== irq
))
589 if (i
< mp_irq_entries
) {
591 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
592 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
601 * Find a specific PCI IRQ entry.
602 * Not an __init, possibly needed by modules
604 static int pin_2_irq(int idx
, int apic
, int pin
);
606 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
608 int apic
, i
, best_guess
= -1;
610 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
612 if (test_bit(bus
, mp_bus_not_pci
)) {
613 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
616 for (i
= 0; i
< mp_irq_entries
; i
++) {
617 int lbus
= mp_irqs
[i
].mp_srcbus
;
619 for (apic
= 0; apic
< nr_ioapics
; apic
++)
620 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
621 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
624 if (!test_bit(lbus
, mp_bus_not_pci
) &&
625 !mp_irqs
[i
].mp_irqtype
&&
627 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
628 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
630 if (!(apic
|| IO_APIC_IRQ(irq
)))
633 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
636 * Use the first all-but-pin matching entry as a
637 * best-guess fuzzy result for broken mptables.
643 BUG_ON(best_guess
>= NR_IRQS
);
647 /* ISA interrupts are always polarity zero edge triggered,
648 * when listed as conforming in the MP table. */
650 #define default_ISA_trigger(idx) (0)
651 #define default_ISA_polarity(idx) (0)
653 /* PCI interrupts are always polarity one level triggered,
654 * when listed as conforming in the MP table. */
656 #define default_PCI_trigger(idx) (1)
657 #define default_PCI_polarity(idx) (1)
659 static int MPBIOS_polarity(int idx
)
661 int bus
= mp_irqs
[idx
].mp_srcbus
;
665 * Determine IRQ line polarity (high active or low active):
667 switch (mp_irqs
[idx
].mp_irqflag
& 3)
669 case 0: /* conforms, ie. bus-type dependent polarity */
670 if (test_bit(bus
, mp_bus_not_pci
))
671 polarity
= default_ISA_polarity(idx
);
673 polarity
= default_PCI_polarity(idx
);
675 case 1: /* high active */
680 case 2: /* reserved */
682 printk(KERN_WARNING
"broken BIOS!!\n");
686 case 3: /* low active */
691 default: /* invalid */
693 printk(KERN_WARNING
"broken BIOS!!\n");
701 static int MPBIOS_trigger(int idx
)
703 int bus
= mp_irqs
[idx
].mp_srcbus
;
707 * Determine IRQ trigger mode (edge or level sensitive):
709 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
711 case 0: /* conforms, ie. bus-type dependent */
712 if (test_bit(bus
, mp_bus_not_pci
))
713 trigger
= default_ISA_trigger(idx
);
715 trigger
= default_PCI_trigger(idx
);
722 case 2: /* reserved */
724 printk(KERN_WARNING
"broken BIOS!!\n");
733 default: /* invalid */
735 printk(KERN_WARNING
"broken BIOS!!\n");
743 static inline int irq_polarity(int idx
)
745 return MPBIOS_polarity(idx
);
748 static inline int irq_trigger(int idx
)
750 return MPBIOS_trigger(idx
);
753 static int pin_2_irq(int idx
, int apic
, int pin
)
756 int bus
= mp_irqs
[idx
].mp_srcbus
;
759 * Debugging check, we are in big trouble if this message pops up!
761 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
762 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
764 if (test_bit(bus
, mp_bus_not_pci
)) {
765 irq
= mp_irqs
[idx
].mp_srcbusirq
;
768 * PCI IRQs are mapped in order
772 irq
+= nr_ioapic_registers
[i
++];
775 BUG_ON(irq
>= NR_IRQS
);
779 static int __assign_irq_vector(int irq
, cpumask_t mask
)
782 * NOTE! The local APIC isn't very good at handling
783 * multiple interrupts at the same interrupt level.
784 * As the interrupt level is determined by taking the
785 * vector number and shifting that right by 4, we
786 * want to spread these out a bit so that they don't
787 * all fall in the same interrupt level.
789 * Also, we've got to be careful not to trash gate
790 * 0x80, because int 0x80 is hm, kind of importantish. ;)
792 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
793 unsigned int old_vector
;
797 BUG_ON((unsigned)irq
>= NR_IRQS
);
800 /* Only try and allocate irqs on cpus that are present */
801 cpus_and(mask
, mask
, cpu_online_map
);
803 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
806 old_vector
= cfg
->vector
;
809 cpus_and(tmp
, cfg
->domain
, mask
);
810 if (!cpus_empty(tmp
))
814 for_each_cpu_mask(cpu
, mask
) {
815 cpumask_t domain
, new_mask
;
819 domain
= vector_allocation_domain(cpu
);
820 cpus_and(new_mask
, domain
, cpu_online_map
);
822 vector
= current_vector
;
823 offset
= current_offset
;
826 if (vector
>= first_system_vector
) {
827 /* If we run out of vectors on large boxen, must share them. */
828 offset
= (offset
+ 1) % 8;
829 vector
= FIRST_DEVICE_VECTOR
+ offset
;
831 if (unlikely(current_vector
== vector
))
833 if (vector
== IA32_SYSCALL_VECTOR
)
835 for_each_cpu_mask(new_cpu
, new_mask
)
836 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
839 current_vector
= vector
;
840 current_offset
= offset
;
842 cfg
->move_in_progress
= 1;
843 cfg
->old_domain
= cfg
->domain
;
845 for_each_cpu_mask(new_cpu
, new_mask
)
846 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
847 cfg
->vector
= vector
;
848 cfg
->domain
= domain
;
854 static int assign_irq_vector(int irq
, cpumask_t mask
)
859 spin_lock_irqsave(&vector_lock
, flags
);
860 err
= __assign_irq_vector(irq
, mask
);
861 spin_unlock_irqrestore(&vector_lock
, flags
);
865 static void __clear_irq_vector(int irq
)
871 BUG_ON((unsigned)irq
>= NR_IRQS
);
873 BUG_ON(!cfg
->vector
);
875 vector
= cfg
->vector
;
876 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
877 for_each_cpu_mask(cpu
, mask
)
878 per_cpu(vector_irq
, cpu
)[vector
] = -1;
881 cpus_clear(cfg
->domain
);
884 static void __setup_vector_irq(int cpu
)
886 /* Initialize vector_irq on a new cpu */
887 /* This function must be called with vector_lock held */
890 /* Mark the inuse vectors */
891 for (irq
= 0; irq
< NR_IRQS
; ++irq
) {
892 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
894 vector
= irq_cfg
[irq
].vector
;
895 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
897 /* Mark the free vectors */
898 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
899 irq
= per_cpu(vector_irq
, cpu
)[vector
];
902 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
903 per_cpu(vector_irq
, cpu
)[vector
] = -1;
907 void setup_vector_irq(int cpu
)
909 spin_lock(&vector_lock
);
910 __setup_vector_irq(smp_processor_id());
911 spin_unlock(&vector_lock
);
915 static struct irq_chip ioapic_chip
;
916 #ifdef CONFIG_INTR_REMAP
917 static struct irq_chip ir_ioapic_chip
;
920 static void ioapic_register_intr(int irq
, unsigned long trigger
)
923 irq_desc
[irq
].status
|= IRQ_LEVEL
;
925 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
927 #ifdef CONFIG_INTR_REMAP
928 if (irq_remapped(irq
)) {
929 irq_desc
[irq
].status
|= IRQ_MOVE_PCNTXT
;
931 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
935 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
936 handle_edge_irq
, "edge");
941 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
945 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
946 handle_edge_irq
, "edge");
949 static int setup_ioapic_entry(int apic
, int irq
,
950 struct IO_APIC_route_entry
*entry
,
951 unsigned int destination
, int trigger
,
952 int polarity
, int vector
)
955 * add it to the IO-APIC irq-routing table:
957 memset(entry
,0,sizeof(*entry
));
959 #ifdef CONFIG_INTR_REMAP
960 if (intr_remapping_enabled
) {
961 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
963 struct IR_IO_APIC_route_entry
*ir_entry
=
964 (struct IR_IO_APIC_route_entry
*) entry
;
968 panic("No mapping iommu for ioapic %d\n", apic
);
970 index
= alloc_irte(iommu
, irq
, 1);
972 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
974 memset(&irte
, 0, sizeof(irte
));
977 irte
.dst_mode
= INT_DEST_MODE
;
978 irte
.trigger_mode
= trigger
;
979 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
980 irte
.vector
= vector
;
981 irte
.dest_id
= IRTE_DEST(destination
);
983 modify_irte(irq
, &irte
);
985 ir_entry
->index2
= (index
>> 15) & 0x1;
987 ir_entry
->format
= 1;
988 ir_entry
->index
= (index
& 0x7fff);
992 entry
->delivery_mode
= INT_DELIVERY_MODE
;
993 entry
->dest_mode
= INT_DEST_MODE
;
994 entry
->dest
= destination
;
997 entry
->mask
= 0; /* enable IRQ */
998 entry
->trigger
= trigger
;
999 entry
->polarity
= polarity
;
1000 entry
->vector
= vector
;
1002 /* Mask level triggered irqs.
1003 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1010 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1011 int trigger
, int polarity
)
1013 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1014 struct IO_APIC_route_entry entry
;
1017 if (!IO_APIC_IRQ(irq
))
1021 if (assign_irq_vector(irq
, mask
))
1024 cpus_and(mask
, cfg
->domain
, mask
);
1026 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1027 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1028 "IRQ %d Mode:%i Active:%i)\n",
1029 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1030 irq
, trigger
, polarity
);
1033 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1034 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1036 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1037 mp_ioapics
[apic
].mp_apicid
, pin
);
1038 __clear_irq_vector(irq
);
1042 ioapic_register_intr(irq
, trigger
);
1044 disable_8259A_irq(irq
);
1046 ioapic_write_entry(apic
, pin
, entry
);
1049 static void __init
setup_IO_APIC_irqs(void)
1051 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1053 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1055 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1056 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1058 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1061 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1064 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1067 if (!first_notcon
) {
1068 apic_printk(APIC_VERBOSE
, " not connected.\n");
1072 irq
= pin_2_irq(idx
, apic
, pin
);
1073 add_pin_to_irq(irq
, apic
, pin
);
1075 setup_IO_APIC_irq(apic
, pin
, irq
,
1076 irq_trigger(idx
), irq_polarity(idx
));
1081 apic_printk(APIC_VERBOSE
, " not connected.\n");
1085 * Set up the timer pin, possibly with the 8259A-master behind.
1087 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1090 struct IO_APIC_route_entry entry
;
1092 if (intr_remapping_enabled
)
1095 memset(&entry
, 0, sizeof(entry
));
1098 * We use logical delivery to get the timer IRQ
1101 entry
.dest_mode
= INT_DEST_MODE
;
1102 entry
.mask
= 1; /* mask IRQ now */
1103 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1104 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1107 entry
.vector
= vector
;
1110 * The timer IRQ doesn't have to know that behind the
1111 * scene we may have a 8259A-master in AEOI mode ...
1113 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1116 * Add it to the IO-APIC irq-routing table:
1118 ioapic_write_entry(apic
, pin
, entry
);
1121 void __apicdebuginit
print_IO_APIC(void)
1124 union IO_APIC_reg_00 reg_00
;
1125 union IO_APIC_reg_01 reg_01
;
1126 union IO_APIC_reg_02 reg_02
;
1127 unsigned long flags
;
1129 if (apic_verbosity
== APIC_QUIET
)
1132 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1133 for (i
= 0; i
< nr_ioapics
; i
++)
1134 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1135 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1138 * We are a bit conservative about what we expect. We have to
1139 * know about every hardware change ASAP.
1141 printk(KERN_INFO
"testing the IO APIC.......................\n");
1143 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1145 spin_lock_irqsave(&ioapic_lock
, flags
);
1146 reg_00
.raw
= io_apic_read(apic
, 0);
1147 reg_01
.raw
= io_apic_read(apic
, 1);
1148 if (reg_01
.bits
.version
>= 0x10)
1149 reg_02
.raw
= io_apic_read(apic
, 2);
1150 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1153 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1154 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1155 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1157 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1158 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1160 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1161 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1163 if (reg_01
.bits
.version
>= 0x10) {
1164 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1165 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1168 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1170 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1171 " Stat Dmod Deli Vect: \n");
1173 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1174 struct IO_APIC_route_entry entry
;
1176 entry
= ioapic_read_entry(apic
, i
);
1178 printk(KERN_DEBUG
" %02x %03X ",
1183 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1188 entry
.delivery_status
,
1190 entry
.delivery_mode
,
1195 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1196 for (i
= 0; i
< NR_IRQS
; i
++) {
1197 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1200 printk(KERN_DEBUG
"IRQ%d ", i
);
1202 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1205 entry
= irq_2_pin
+ entry
->next
;
1210 printk(KERN_INFO
".................................... done.\n");
1217 static __apicdebuginit
void print_APIC_bitfield (int base
)
1222 if (apic_verbosity
== APIC_QUIET
)
1225 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1226 for (i
= 0; i
< 8; i
++) {
1227 v
= apic_read(base
+ i
*0x10);
1228 for (j
= 0; j
< 32; j
++) {
1238 void __apicdebuginit
print_local_APIC(void * dummy
)
1240 unsigned int v
, ver
, maxlvt
;
1243 if (apic_verbosity
== APIC_QUIET
)
1246 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1247 smp_processor_id(), hard_smp_processor_id());
1248 v
= apic_read(APIC_ID
);
1249 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(read_apic_id()));
1250 v
= apic_read(APIC_LVR
);
1251 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1252 ver
= GET_APIC_VERSION(v
);
1253 maxlvt
= lapic_get_maxlvt();
1255 v
= apic_read(APIC_TASKPRI
);
1256 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1258 v
= apic_read(APIC_ARBPRI
);
1259 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1260 v
& APIC_ARBPRI_MASK
);
1261 v
= apic_read(APIC_PROCPRI
);
1262 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1264 v
= apic_read(APIC_EOI
);
1265 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1266 v
= apic_read(APIC_RRR
);
1267 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1268 v
= apic_read(APIC_LDR
);
1269 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1270 v
= apic_read(APIC_DFR
);
1271 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1272 v
= apic_read(APIC_SPIV
);
1273 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1275 printk(KERN_DEBUG
"... APIC ISR field:\n");
1276 print_APIC_bitfield(APIC_ISR
);
1277 printk(KERN_DEBUG
"... APIC TMR field:\n");
1278 print_APIC_bitfield(APIC_TMR
);
1279 printk(KERN_DEBUG
"... APIC IRR field:\n");
1280 print_APIC_bitfield(APIC_IRR
);
1282 v
= apic_read(APIC_ESR
);
1283 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1285 icr
= apic_icr_read();
1286 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1287 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1289 v
= apic_read(APIC_LVTT
);
1290 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1292 if (maxlvt
> 3) { /* PC is LVT#4. */
1293 v
= apic_read(APIC_LVTPC
);
1294 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1296 v
= apic_read(APIC_LVT0
);
1297 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1298 v
= apic_read(APIC_LVT1
);
1299 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1301 if (maxlvt
> 2) { /* ERR is LVT#3. */
1302 v
= apic_read(APIC_LVTERR
);
1303 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1306 v
= apic_read(APIC_TMICT
);
1307 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1308 v
= apic_read(APIC_TMCCT
);
1309 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1310 v
= apic_read(APIC_TDCR
);
1311 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1315 void print_all_local_APICs (void)
1317 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1320 void __apicdebuginit
print_PIC(void)
1323 unsigned long flags
;
1325 if (apic_verbosity
== APIC_QUIET
)
1328 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1330 spin_lock_irqsave(&i8259A_lock
, flags
);
1332 v
= inb(0xa1) << 8 | inb(0x21);
1333 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1335 v
= inb(0xa0) << 8 | inb(0x20);
1336 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1340 v
= inb(0xa0) << 8 | inb(0x20);
1344 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1346 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1348 v
= inb(0x4d1) << 8 | inb(0x4d0);
1349 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1354 void __init
enable_IO_APIC(void)
1356 union IO_APIC_reg_01 reg_01
;
1357 int i8259_apic
, i8259_pin
;
1359 unsigned long flags
;
1361 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1362 irq_2_pin
[i
].pin
= -1;
1363 irq_2_pin
[i
].next
= 0;
1367 * The number of IO-APIC IRQ registers (== #pins):
1369 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1370 spin_lock_irqsave(&ioapic_lock
, flags
);
1371 reg_01
.raw
= io_apic_read(apic
, 1);
1372 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1373 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1375 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1377 /* See if any of the pins is in ExtINT mode */
1378 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1379 struct IO_APIC_route_entry entry
;
1380 entry
= ioapic_read_entry(apic
, pin
);
1382 /* If the interrupt line is enabled and in ExtInt mode
1383 * I have found the pin where the i8259 is connected.
1385 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1386 ioapic_i8259
.apic
= apic
;
1387 ioapic_i8259
.pin
= pin
;
1393 /* Look to see what if the MP table has reported the ExtINT */
1394 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1395 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1396 /* Trust the MP table if nothing is setup in the hardware */
1397 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1398 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1399 ioapic_i8259
.pin
= i8259_pin
;
1400 ioapic_i8259
.apic
= i8259_apic
;
1402 /* Complain if the MP table and the hardware disagree */
1403 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1404 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1406 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1410 * Do not trust the IO-APIC being empty at bootup
1416 * Not an __init, needed by the reboot code
1418 void disable_IO_APIC(void)
1421 * Clear the IO-APIC before rebooting:
1426 * If the i8259 is routed through an IOAPIC
1427 * Put that IOAPIC in virtual wire mode
1428 * so legacy interrupts can be delivered.
1430 if (ioapic_i8259
.pin
!= -1) {
1431 struct IO_APIC_route_entry entry
;
1433 memset(&entry
, 0, sizeof(entry
));
1434 entry
.mask
= 0; /* Enabled */
1435 entry
.trigger
= 0; /* Edge */
1437 entry
.polarity
= 0; /* High */
1438 entry
.delivery_status
= 0;
1439 entry
.dest_mode
= 0; /* Physical */
1440 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1442 entry
.dest
= GET_APIC_ID(read_apic_id());
1445 * Add it to the IO-APIC irq-routing table:
1447 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1450 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1454 * There is a nasty bug in some older SMP boards, their mptable lies
1455 * about the timer IRQ. We do the following to work around the situation:
1457 * - timer IRQ defaults to IO-APIC IRQ
1458 * - if this function detects that timer IRQs are defunct, then we fall
1459 * back to ISA timer IRQs
1461 static int __init
timer_irq_works(void)
1463 unsigned long t1
= jiffies
;
1464 unsigned long flags
;
1466 local_save_flags(flags
);
1468 /* Let ten ticks pass... */
1469 mdelay((10 * 1000) / HZ
);
1470 local_irq_restore(flags
);
1473 * Expect a few ticks at least, to be sure some possible
1474 * glue logic does not lock up after one or two first
1475 * ticks in a non-ExtINT mode. Also the local APIC
1476 * might have cached one ExtINT interrupt. Finally, at
1477 * least one tick may be lost due to delays.
1481 if (time_after(jiffies
, t1
+ 4))
1487 * In the SMP+IOAPIC case it might happen that there are an unspecified
1488 * number of pending IRQ events unhandled. These cases are very rare,
1489 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1490 * better to do it this way as thus we do not have to be aware of
1491 * 'pending' interrupts in the IRQ path, except at this point.
1494 * Edge triggered needs to resend any interrupt
1495 * that was delayed but this is now handled in the device
1500 * Starting up a edge-triggered IO-APIC interrupt is
1501 * nasty - we need to make sure that we get the edge.
1502 * If it is already asserted for some reason, we need
1503 * return 1 to indicate that is was pending.
1505 * This is not complete - we should be able to fake
1506 * an edge even if it isn't on the 8259A...
1509 static unsigned int startup_ioapic_irq(unsigned int irq
)
1511 int was_pending
= 0;
1512 unsigned long flags
;
1514 spin_lock_irqsave(&ioapic_lock
, flags
);
1516 disable_8259A_irq(irq
);
1517 if (i8259A_irq_pending(irq
))
1520 __unmask_IO_APIC_irq(irq
);
1521 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1526 static int ioapic_retrigger_irq(unsigned int irq
)
1528 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
1530 unsigned long flags
;
1532 spin_lock_irqsave(&vector_lock
, flags
);
1533 mask
= cpumask_of_cpu(first_cpu(cfg
->domain
));
1534 send_IPI_mask(mask
, cfg
->vector
);
1535 spin_unlock_irqrestore(&vector_lock
, flags
);
1541 * Level and edge triggered IO-APIC interrupts need different handling,
1542 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1543 * handled with the level-triggered descriptor, but that one has slightly
1544 * more overhead. Level-triggered interrupts cannot be handled with the
1545 * edge-triggered handler, without risking IRQ storms and other ugly
1551 #ifdef CONFIG_INTR_REMAP
1552 static void ir_irq_migration(struct work_struct
*work
);
1554 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
1557 * Migrate the IO-APIC irq in the presence of intr-remapping.
1559 * For edge triggered, irq migration is a simple atomic update(of vector
1560 * and cpu destination) of IRTE and flush the hardware cache.
1562 * For level triggered, we need to modify the io-apic RTE aswell with the update
1563 * vector information, along with modifying IRTE with vector and destination.
1564 * So irq migration for level triggered is little bit more complex compared to
1565 * edge triggered migration. But the good news is, we use the same algorithm
1566 * for level triggered migration as we have today, only difference being,
1567 * we now initiate the irq migration from process context instead of the
1568 * interrupt context.
1570 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1571 * suppression) to the IO-APIC, level triggered irq migration will also be
1572 * as simple as edge triggered migration and we can do the irq migration
1573 * with a simple atomic update to IO-APIC RTE.
1575 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
1577 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1578 struct irq_desc
*desc
= irq_desc
+ irq
;
1579 cpumask_t tmp
, cleanup_mask
;
1581 int modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
1583 unsigned long flags
;
1585 cpus_and(tmp
, mask
, cpu_online_map
);
1586 if (cpus_empty(tmp
))
1589 if (get_irte(irq
, &irte
))
1592 if (assign_irq_vector(irq
, mask
))
1595 cpus_and(tmp
, cfg
->domain
, mask
);
1596 dest
= cpu_mask_to_apicid(tmp
);
1598 if (modify_ioapic_rte
) {
1599 spin_lock_irqsave(&ioapic_lock
, flags
);
1600 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
1601 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1604 irte
.vector
= cfg
->vector
;
1605 irte
.dest_id
= IRTE_DEST(dest
);
1608 * Modified the IRTE and flushes the Interrupt entry cache.
1610 modify_irte(irq
, &irte
);
1612 if (cfg
->move_in_progress
) {
1613 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1614 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1615 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1616 cfg
->move_in_progress
= 0;
1619 irq_desc
[irq
].affinity
= mask
;
1622 static int migrate_irq_remapped_level(int irq
)
1626 mask_IO_APIC_irq(irq
);
1628 if (io_apic_level_ack_pending(irq
)) {
1630 * Interrupt in progress. Migrating irq now will change the
1631 * vector information in the IO-APIC RTE and that will confuse
1632 * the EOI broadcast performed by cpu.
1633 * So, delay the irq migration to the next instance.
1635 schedule_delayed_work(&ir_migration_work
, 1);
1639 /* everthing is clear. we have right of way */
1640 migrate_ioapic_irq(irq
, irq_desc
[irq
].pending_mask
);
1643 irq_desc
[irq
].status
&= ~IRQ_MOVE_PENDING
;
1644 cpus_clear(irq_desc
[irq
].pending_mask
);
1647 unmask_IO_APIC_irq(irq
);
1651 static void ir_irq_migration(struct work_struct
*work
)
1655 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1656 struct irq_desc
*desc
= irq_desc
+ irq
;
1657 if (desc
->status
& IRQ_MOVE_PENDING
) {
1658 unsigned long flags
;
1660 spin_lock_irqsave(&desc
->lock
, flags
);
1661 if (!desc
->chip
->set_affinity
||
1662 !(desc
->status
& IRQ_MOVE_PENDING
)) {
1663 desc
->status
&= ~IRQ_MOVE_PENDING
;
1664 spin_unlock_irqrestore(&desc
->lock
, flags
);
1668 desc
->chip
->set_affinity(irq
,
1669 irq_desc
[irq
].pending_mask
);
1670 spin_unlock_irqrestore(&desc
->lock
, flags
);
1676 * Migrates the IRQ destination in the process context.
1678 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
1680 if (irq_desc
[irq
].status
& IRQ_LEVEL
) {
1681 irq_desc
[irq
].status
|= IRQ_MOVE_PENDING
;
1682 irq_desc
[irq
].pending_mask
= mask
;
1683 migrate_irq_remapped_level(irq
);
1687 migrate_ioapic_irq(irq
, mask
);
1691 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1693 unsigned vector
, me
;
1698 me
= smp_processor_id();
1699 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1701 struct irq_desc
*desc
;
1702 struct irq_cfg
*cfg
;
1703 irq
= __get_cpu_var(vector_irq
)[vector
];
1707 desc
= irq_desc
+ irq
;
1708 cfg
= irq_cfg
+ irq
;
1709 spin_lock(&desc
->lock
);
1710 if (!cfg
->move_cleanup_count
)
1713 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1716 __get_cpu_var(vector_irq
)[vector
] = -1;
1717 cfg
->move_cleanup_count
--;
1719 spin_unlock(&desc
->lock
);
1725 static void irq_complete_move(unsigned int irq
)
1727 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1728 unsigned vector
, me
;
1730 if (likely(!cfg
->move_in_progress
))
1733 vector
= ~get_irq_regs()->orig_ax
;
1734 me
= smp_processor_id();
1735 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1736 cpumask_t cleanup_mask
;
1738 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1739 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1740 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1741 cfg
->move_in_progress
= 0;
1745 static inline void irq_complete_move(unsigned int irq
) {}
1747 #ifdef CONFIG_INTR_REMAP
1748 static void ack_x2apic_level(unsigned int irq
)
1753 static void ack_x2apic_edge(unsigned int irq
)
1759 static void ack_apic_edge(unsigned int irq
)
1761 irq_complete_move(irq
);
1762 move_native_irq(irq
);
1766 static void ack_apic_level(unsigned int irq
)
1768 int do_unmask_irq
= 0;
1770 irq_complete_move(irq
);
1771 #ifdef CONFIG_GENERIC_PENDING_IRQ
1772 /* If we are moving the irq we need to mask it */
1773 if (unlikely(irq_desc
[irq
].status
& IRQ_MOVE_PENDING
)) {
1775 mask_IO_APIC_irq(irq
);
1780 * We must acknowledge the irq before we move it or the acknowledge will
1781 * not propagate properly.
1785 /* Now we can move and renable the irq */
1786 if (unlikely(do_unmask_irq
)) {
1787 /* Only migrate the irq if the ack has been received.
1789 * On rare occasions the broadcast level triggered ack gets
1790 * delayed going to ioapics, and if we reprogram the
1791 * vector while Remote IRR is still set the irq will never
1794 * To prevent this scenario we read the Remote IRR bit
1795 * of the ioapic. This has two effects.
1796 * - On any sane system the read of the ioapic will
1797 * flush writes (and acks) going to the ioapic from
1799 * - We get to see if the ACK has actually been delivered.
1801 * Based on failed experiments of reprogramming the
1802 * ioapic entry from outside of irq context starting
1803 * with masking the ioapic entry and then polling until
1804 * Remote IRR was clear before reprogramming the
1805 * ioapic I don't trust the Remote IRR bit to be
1806 * completey accurate.
1808 * However there appears to be no other way to plug
1809 * this race, so if the Remote IRR bit is not
1810 * accurate and is causing problems then it is a hardware bug
1811 * and you can go talk to the chipset vendor about it.
1813 if (!io_apic_level_ack_pending(irq
))
1814 move_masked_irq(irq
);
1815 unmask_IO_APIC_irq(irq
);
1819 static struct irq_chip ioapic_chip __read_mostly
= {
1821 .startup
= startup_ioapic_irq
,
1822 .mask
= mask_IO_APIC_irq
,
1823 .unmask
= unmask_IO_APIC_irq
,
1824 .ack
= ack_apic_edge
,
1825 .eoi
= ack_apic_level
,
1827 .set_affinity
= set_ioapic_affinity_irq
,
1829 .retrigger
= ioapic_retrigger_irq
,
1832 #ifdef CONFIG_INTR_REMAP
1833 static struct irq_chip ir_ioapic_chip __read_mostly
= {
1834 .name
= "IR-IO-APIC",
1835 .startup
= startup_ioapic_irq
,
1836 .mask
= mask_IO_APIC_irq
,
1837 .unmask
= unmask_IO_APIC_irq
,
1838 .ack
= ack_x2apic_edge
,
1839 .eoi
= ack_x2apic_level
,
1841 .set_affinity
= set_ir_ioapic_affinity_irq
,
1843 .retrigger
= ioapic_retrigger_irq
,
1847 static inline void init_IO_APIC_traps(void)
1852 * NOTE! The local APIC isn't very good at handling
1853 * multiple interrupts at the same interrupt level.
1854 * As the interrupt level is determined by taking the
1855 * vector number and shifting that right by 4, we
1856 * want to spread these out a bit so that they don't
1857 * all fall in the same interrupt level.
1859 * Also, we've got to be careful not to trash gate
1860 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1862 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1863 if (IO_APIC_IRQ(irq
) && !irq_cfg
[irq
].vector
) {
1865 * Hmm.. We don't have an entry for this,
1866 * so default to an old-fashioned 8259
1867 * interrupt if we can..
1870 make_8259A_irq(irq
);
1872 /* Strange. Oh, well.. */
1873 irq_desc
[irq
].chip
= &no_irq_chip
;
1878 static void unmask_lapic_irq(unsigned int irq
)
1882 v
= apic_read(APIC_LVT0
);
1883 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1886 static void mask_lapic_irq(unsigned int irq
)
1890 v
= apic_read(APIC_LVT0
);
1891 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1894 static void ack_lapic_irq (unsigned int irq
)
1899 static struct irq_chip lapic_chip __read_mostly
= {
1900 .name
= "local-APIC",
1901 .mask
= mask_lapic_irq
,
1902 .unmask
= unmask_lapic_irq
,
1903 .ack
= ack_lapic_irq
,
1906 static void lapic_register_intr(int irq
)
1908 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1909 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
1913 static void __init
setup_nmi(void)
1916 * Dirty trick to enable the NMI watchdog ...
1917 * We put the 8259A master into AEOI mode and
1918 * unmask on all local APICs LVT0 as NMI.
1920 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1921 * is from Maciej W. Rozycki - so we do not have to EOI from
1922 * the NMI handler or the timer interrupt.
1924 printk(KERN_INFO
"activating NMI Watchdog ...");
1926 enable_NMI_through_LVT0();
1932 * This looks a bit hackish but it's about the only one way of sending
1933 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1934 * not support the ExtINT mode, unfortunately. We need to send these
1935 * cycles as some i82489DX-based boards have glue logic that keeps the
1936 * 8259A interrupt line asserted until INTA. --macro
1938 static inline void __init
unlock_ExtINT_logic(void)
1941 struct IO_APIC_route_entry entry0
, entry1
;
1942 unsigned char save_control
, save_freq_select
;
1944 pin
= find_isa_irq_pin(8, mp_INT
);
1945 apic
= find_isa_irq_apic(8, mp_INT
);
1949 entry0
= ioapic_read_entry(apic
, pin
);
1951 clear_IO_APIC_pin(apic
, pin
);
1953 memset(&entry1
, 0, sizeof(entry1
));
1955 entry1
.dest_mode
= 0; /* physical delivery */
1956 entry1
.mask
= 0; /* unmask IRQ now */
1957 entry1
.dest
= hard_smp_processor_id();
1958 entry1
.delivery_mode
= dest_ExtINT
;
1959 entry1
.polarity
= entry0
.polarity
;
1963 ioapic_write_entry(apic
, pin
, entry1
);
1965 save_control
= CMOS_READ(RTC_CONTROL
);
1966 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1967 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1969 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1974 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1978 CMOS_WRITE(save_control
, RTC_CONTROL
);
1979 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1980 clear_IO_APIC_pin(apic
, pin
);
1982 ioapic_write_entry(apic
, pin
, entry0
);
1986 * This code may look a bit paranoid, but it's supposed to cooperate with
1987 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1988 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1989 * fanatically on his truly buggy board.
1991 * FIXME: really need to revamp this for modern platforms only.
1993 static inline void __init
check_timer(void)
1995 struct irq_cfg
*cfg
= irq_cfg
+ 0;
1996 int apic1
, pin1
, apic2
, pin2
;
1997 unsigned long flags
;
2000 local_irq_save(flags
);
2003 * get/set the timer IRQ vector:
2005 disable_8259A_irq(0);
2006 assign_irq_vector(0, TARGET_CPUS
);
2009 * As IRQ0 is to be enabled in the 8259A, the virtual
2010 * wire has to be disabled in the local APIC.
2012 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2015 pin1
= find_isa_irq_pin(0, mp_INT
);
2016 apic1
= find_isa_irq_apic(0, mp_INT
);
2017 pin2
= ioapic_i8259
.pin
;
2018 apic2
= ioapic_i8259
.apic
;
2020 apic_printk(APIC_VERBOSE
,KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2021 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2023 if (mask_ioapic_irq_2
)
2024 mask_IO_APIC_irq(2);
2027 * Some BIOS writers are clueless and report the ExtINTA
2028 * I/O APIC input from the cascaded 8259A as the timer
2029 * interrupt input. So just in case, if only one pin
2030 * was found above, try it both directly and through the
2034 if (intr_remapping_enabled
)
2035 panic("BIOS bug: timer not connected to IO-APIC");
2039 } else if (pin2
== -1) {
2046 * Ok, does IRQ0 through the IOAPIC work?
2049 add_pin_to_irq(0, apic1
, pin1
);
2050 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2052 unmask_IO_APIC_irq(0);
2053 if (!no_timer_check
&& timer_irq_works()) {
2054 if (nmi_watchdog
== NMI_IO_APIC
) {
2056 enable_8259A_irq(0);
2058 if (disable_timer_pin_1
> 0)
2059 clear_IO_APIC_pin(0, pin1
);
2062 if (intr_remapping_enabled
)
2063 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2064 clear_IO_APIC_pin(apic1
, pin1
);
2066 apic_printk(APIC_QUIET
,KERN_ERR
"..MP-BIOS bug: "
2067 "8254 timer not connected to IO-APIC\n");
2069 apic_printk(APIC_VERBOSE
,KERN_INFO
2070 "...trying to set up timer (IRQ0) "
2071 "through the 8259A ... ");
2072 apic_printk(APIC_VERBOSE
,"\n..... (found apic %d pin %d) ...",
2075 * legacy devices should be connected to IO APIC #0
2077 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2078 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2079 unmask_IO_APIC_irq(0);
2080 enable_8259A_irq(0);
2081 if (timer_irq_works()) {
2082 apic_printk(APIC_VERBOSE
," works.\n");
2083 timer_through_8259
= 1;
2084 if (nmi_watchdog
== NMI_IO_APIC
) {
2085 disable_8259A_irq(0);
2087 enable_8259A_irq(0);
2092 * Cleanup, just in case ...
2094 disable_8259A_irq(0);
2095 clear_IO_APIC_pin(apic2
, pin2
);
2096 apic_printk(APIC_VERBOSE
," failed.\n");
2099 if (nmi_watchdog
== NMI_IO_APIC
) {
2100 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2101 nmi_watchdog
= NMI_NONE
;
2104 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2106 lapic_register_intr(0);
2107 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2108 enable_8259A_irq(0);
2110 if (timer_irq_works()) {
2111 apic_printk(APIC_VERBOSE
," works.\n");
2114 disable_8259A_irq(0);
2115 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2116 apic_printk(APIC_VERBOSE
," failed.\n");
2118 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2122 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2124 unlock_ExtINT_logic();
2126 if (timer_irq_works()) {
2127 apic_printk(APIC_VERBOSE
," works.\n");
2130 apic_printk(APIC_VERBOSE
," failed :(.\n");
2131 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
2133 local_irq_restore(flags
);
2136 static int __init
notimercheck(char *s
)
2141 __setup("no_timer_check", notimercheck
);
2144 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2145 * to devices. However there may be an I/O APIC pin available for
2146 * this interrupt regardless. The pin may be left unconnected, but
2147 * typically it will be reused as an ExtINT cascade interrupt for
2148 * the master 8259A. In the MPS case such a pin will normally be
2149 * reported as an ExtINT interrupt in the MP table. With ACPI
2150 * there is no provision for ExtINT interrupts, and in the absence
2151 * of an override it would be treated as an ordinary ISA I/O APIC
2152 * interrupt, that is edge-triggered and unmasked by default. We
2153 * used to do this, but it caused problems on some systems because
2154 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2155 * the same ExtINT cascade interrupt to drive the local APIC of the
2156 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2157 * the I/O APIC in all cases now. No actual device should request
2158 * it anyway. --macro
2160 #define PIC_IRQS (1<<2)
2162 void __init
setup_IO_APIC(void)
2166 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2169 io_apic_irqs
= ~PIC_IRQS
;
2171 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2174 setup_IO_APIC_irqs();
2175 init_IO_APIC_traps();
2181 struct sysfs_ioapic_data
{
2182 struct sys_device dev
;
2183 struct IO_APIC_route_entry entry
[0];
2185 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2187 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2189 struct IO_APIC_route_entry
*entry
;
2190 struct sysfs_ioapic_data
*data
;
2193 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2194 entry
= data
->entry
;
2195 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2196 *entry
= ioapic_read_entry(dev
->id
, i
);
2201 static int ioapic_resume(struct sys_device
*dev
)
2203 struct IO_APIC_route_entry
*entry
;
2204 struct sysfs_ioapic_data
*data
;
2205 unsigned long flags
;
2206 union IO_APIC_reg_00 reg_00
;
2209 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2210 entry
= data
->entry
;
2212 spin_lock_irqsave(&ioapic_lock
, flags
);
2213 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2214 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2215 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2216 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2218 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2219 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2220 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2225 static struct sysdev_class ioapic_sysdev_class
= {
2227 .suspend
= ioapic_suspend
,
2228 .resume
= ioapic_resume
,
2231 static int __init
ioapic_init_sysfs(void)
2233 struct sys_device
* dev
;
2236 error
= sysdev_class_register(&ioapic_sysdev_class
);
2240 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2241 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2242 * sizeof(struct IO_APIC_route_entry
);
2243 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2244 if (!mp_ioapic_data
[i
]) {
2245 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2248 dev
= &mp_ioapic_data
[i
]->dev
;
2250 dev
->cls
= &ioapic_sysdev_class
;
2251 error
= sysdev_register(dev
);
2253 kfree(mp_ioapic_data
[i
]);
2254 mp_ioapic_data
[i
] = NULL
;
2255 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2263 device_initcall(ioapic_init_sysfs
);
2266 * Dynamic irq allocate and deallocation
2268 int create_irq(void)
2270 /* Allocate an unused irq */
2273 unsigned long flags
;
2276 spin_lock_irqsave(&vector_lock
, flags
);
2277 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2278 if (platform_legacy_irq(new))
2280 if (irq_cfg
[new].vector
!= 0)
2282 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
2286 spin_unlock_irqrestore(&vector_lock
, flags
);
2289 dynamic_irq_init(irq
);
2294 void destroy_irq(unsigned int irq
)
2296 unsigned long flags
;
2298 dynamic_irq_cleanup(irq
);
2300 spin_lock_irqsave(&vector_lock
, flags
);
2301 __clear_irq_vector(irq
);
2302 spin_unlock_irqrestore(&vector_lock
, flags
);
2306 * MSI message composition
2308 #ifdef CONFIG_PCI_MSI
2309 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2311 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2317 err
= assign_irq_vector(irq
, tmp
);
2319 cpus_and(tmp
, cfg
->domain
, tmp
);
2320 dest
= cpu_mask_to_apicid(tmp
);
2322 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2325 ((INT_DEST_MODE
== 0) ?
2326 MSI_ADDR_DEST_MODE_PHYSICAL
:
2327 MSI_ADDR_DEST_MODE_LOGICAL
) |
2328 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2329 MSI_ADDR_REDIRECTION_CPU
:
2330 MSI_ADDR_REDIRECTION_LOWPRI
) |
2331 MSI_ADDR_DEST_ID(dest
);
2334 MSI_DATA_TRIGGER_EDGE
|
2335 MSI_DATA_LEVEL_ASSERT
|
2336 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2337 MSI_DATA_DELIVERY_FIXED
:
2338 MSI_DATA_DELIVERY_LOWPRI
) |
2339 MSI_DATA_VECTOR(cfg
->vector
);
2345 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2347 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2352 cpus_and(tmp
, mask
, cpu_online_map
);
2353 if (cpus_empty(tmp
))
2356 if (assign_irq_vector(irq
, mask
))
2359 cpus_and(tmp
, cfg
->domain
, mask
);
2360 dest
= cpu_mask_to_apicid(tmp
);
2362 read_msi_msg(irq
, &msg
);
2364 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2365 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2366 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2367 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2369 write_msi_msg(irq
, &msg
);
2370 irq_desc
[irq
].affinity
= mask
;
2372 #endif /* CONFIG_SMP */
2375 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2376 * which implement the MSI or MSI-X Capability Structure.
2378 static struct irq_chip msi_chip
= {
2380 .unmask
= unmask_msi_irq
,
2381 .mask
= mask_msi_irq
,
2382 .ack
= ack_apic_edge
,
2384 .set_affinity
= set_msi_irq_affinity
,
2386 .retrigger
= ioapic_retrigger_irq
,
2389 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2397 ret
= msi_compose_msg(dev
, irq
, &msg
);
2403 set_irq_msi(irq
, desc
);
2404 write_msi_msg(irq
, &msg
);
2406 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2411 void arch_teardown_msi_irq(unsigned int irq
)
2418 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
2420 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2425 cpus_and(tmp
, mask
, cpu_online_map
);
2426 if (cpus_empty(tmp
))
2429 if (assign_irq_vector(irq
, mask
))
2432 cpus_and(tmp
, cfg
->domain
, mask
);
2433 dest
= cpu_mask_to_apicid(tmp
);
2435 dmar_msi_read(irq
, &msg
);
2437 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2438 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2439 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2440 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2442 dmar_msi_write(irq
, &msg
);
2443 irq_desc
[irq
].affinity
= mask
;
2445 #endif /* CONFIG_SMP */
2447 struct irq_chip dmar_msi_type
= {
2449 .unmask
= dmar_msi_unmask
,
2450 .mask
= dmar_msi_mask
,
2451 .ack
= ack_apic_edge
,
2453 .set_affinity
= dmar_msi_set_affinity
,
2455 .retrigger
= ioapic_retrigger_irq
,
2458 int arch_setup_dmar_msi(unsigned int irq
)
2463 ret
= msi_compose_msg(NULL
, irq
, &msg
);
2466 dmar_msi_write(irq
, &msg
);
2467 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
2473 #endif /* CONFIG_PCI_MSI */
2475 * Hypertransport interrupt support
2477 #ifdef CONFIG_HT_IRQ
2481 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2483 struct ht_irq_msg msg
;
2484 fetch_ht_irq_msg(irq
, &msg
);
2486 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2487 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2489 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2490 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2492 write_ht_irq_msg(irq
, &msg
);
2495 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2497 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2501 cpus_and(tmp
, mask
, cpu_online_map
);
2502 if (cpus_empty(tmp
))
2505 if (assign_irq_vector(irq
, mask
))
2508 cpus_and(tmp
, cfg
->domain
, mask
);
2509 dest
= cpu_mask_to_apicid(tmp
);
2511 target_ht_irq(irq
, dest
, cfg
->vector
);
2512 irq_desc
[irq
].affinity
= mask
;
2516 static struct irq_chip ht_irq_chip
= {
2518 .mask
= mask_ht_irq
,
2519 .unmask
= unmask_ht_irq
,
2520 .ack
= ack_apic_edge
,
2522 .set_affinity
= set_ht_irq_affinity
,
2524 .retrigger
= ioapic_retrigger_irq
,
2527 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2529 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2534 err
= assign_irq_vector(irq
, tmp
);
2536 struct ht_irq_msg msg
;
2539 cpus_and(tmp
, cfg
->domain
, tmp
);
2540 dest
= cpu_mask_to_apicid(tmp
);
2542 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2546 HT_IRQ_LOW_DEST_ID(dest
) |
2547 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2548 ((INT_DEST_MODE
== 0) ?
2549 HT_IRQ_LOW_DM_PHYSICAL
:
2550 HT_IRQ_LOW_DM_LOGICAL
) |
2551 HT_IRQ_LOW_RQEOI_EDGE
|
2552 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2553 HT_IRQ_LOW_MT_FIXED
:
2554 HT_IRQ_LOW_MT_ARBITRATED
) |
2555 HT_IRQ_LOW_IRQ_MASKED
;
2557 write_ht_irq_msg(irq
, &msg
);
2559 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2560 handle_edge_irq
, "edge");
2564 #endif /* CONFIG_HT_IRQ */
2566 /* --------------------------------------------------------------------------
2567 ACPI-based IOAPIC Configuration
2568 -------------------------------------------------------------------------- */
2572 #define IO_APIC_MAX_ID 0xFE
2574 int __init
io_apic_get_redir_entries (int ioapic
)
2576 union IO_APIC_reg_01 reg_01
;
2577 unsigned long flags
;
2579 spin_lock_irqsave(&ioapic_lock
, flags
);
2580 reg_01
.raw
= io_apic_read(ioapic
, 1);
2581 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2583 return reg_01
.bits
.entries
;
2587 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2589 if (!IO_APIC_IRQ(irq
)) {
2590 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2596 * IRQs < 16 are already in the irq_2_pin[] map
2599 add_pin_to_irq(irq
, ioapic
, pin
);
2601 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2607 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2611 if (skip_ioapic_setup
)
2614 for (i
= 0; i
< mp_irq_entries
; i
++)
2615 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2616 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2618 if (i
>= mp_irq_entries
)
2621 *trigger
= irq_trigger(i
);
2622 *polarity
= irq_polarity(i
);
2626 #endif /* CONFIG_ACPI */
2629 * This function currently is only a helper for the i386 smp boot process where
2630 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2631 * so mask in all cases should simply be TARGET_CPUS
2634 void __init
setup_ioapic_dest(void)
2636 int pin
, ioapic
, irq
, irq_entry
;
2638 if (skip_ioapic_setup
== 1)
2641 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2642 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2643 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2644 if (irq_entry
== -1)
2646 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2648 /* setup_IO_APIC_irqs could fail to get vector for some device
2649 * when you have too many devices, because at that time only boot
2652 if (!irq_cfg
[irq
].vector
)
2653 setup_IO_APIC_irq(ioapic
, pin
, irq
,
2654 irq_trigger(irq_entry
),
2655 irq_polarity(irq_entry
));
2656 #ifdef CONFIG_INTR_REMAP
2657 else if (intr_remapping_enabled
)
2658 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2661 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2668 #define IOAPIC_RESOURCE_NAME_SIZE 11
2670 static struct resource
*ioapic_resources
;
2672 static struct resource
* __init
ioapic_setup_resources(void)
2675 struct resource
*res
;
2679 if (nr_ioapics
<= 0)
2682 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
2685 mem
= alloc_bootmem(n
);
2689 mem
+= sizeof(struct resource
) * nr_ioapics
;
2691 for (i
= 0; i
< nr_ioapics
; i
++) {
2693 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
2694 sprintf(mem
, "IOAPIC %u", i
);
2695 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
2699 ioapic_resources
= res
;
2704 void __init
ioapic_init_mappings(void)
2706 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2707 struct resource
*ioapic_res
;
2710 ioapic_res
= ioapic_setup_resources();
2711 for (i
= 0; i
< nr_ioapics
; i
++) {
2712 if (smp_found_config
) {
2713 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2715 ioapic_phys
= (unsigned long)
2716 alloc_bootmem_pages(PAGE_SIZE
);
2717 ioapic_phys
= __pa(ioapic_phys
);
2719 set_fixmap_nocache(idx
, ioapic_phys
);
2720 apic_printk(APIC_VERBOSE
,
2721 "mapped IOAPIC to %016lx (%016lx)\n",
2722 __fix_to_virt(idx
), ioapic_phys
);
2725 if (ioapic_res
!= NULL
) {
2726 ioapic_res
->start
= ioapic_phys
;
2727 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
2733 static int __init
ioapic_insert_resources(void)
2736 struct resource
*r
= ioapic_resources
;
2740 "IO APIC resources could be not be allocated.\n");
2744 for (i
= 0; i
< nr_ioapics
; i
++) {
2745 insert_resource(&iomem_resource
, r
);
2752 /* Insert the IO APIC resources after PCI initialization has occured to handle
2753 * IO APICS that are mapped in on a BAR in PCI space. */
2754 late_initcall(ioapic_insert_resources
);