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x86: avoid redundant loop in io_apic_level_ack_pending()
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/nmi.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
51
52 #include <mach_ipi.h>
53 #include <mach_apic.h>
54
55 struct irq_cfg {
56 cpumask_t domain;
57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
59 u8 vector;
60 u8 move_in_progress : 1;
61 };
62
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
81 };
82
83 static int assign_irq_vector(int irq, cpumask_t mask);
84
85 #define __apicdebuginit __init
86
87 int sis_apic_bug; /* not actually supported, dummy for compile */
88
89 static int no_timer_check;
90
91 static int disable_timer_pin_1 __initdata;
92
93 int timer_over_8254 __initdata = 1;
94
95 /* Where if anywhere is the i8259 connect in external int mode */
96 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
97
98 static DEFINE_SPINLOCK(ioapic_lock);
99 DEFINE_SPINLOCK(vector_lock);
100
101 /*
102 * # of IRQ routing registers
103 */
104 int nr_ioapic_registers[MAX_IO_APICS];
105
106 /* I/O APIC entries */
107 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
108 int nr_ioapics;
109
110 /* MP IRQ source entries */
111 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
112
113 /* # of MP IRQ source entries */
114 int mp_irq_entries;
115
116 /*
117 * Rough estimation of how many shared IRQs there are, can
118 * be changed anytime.
119 */
120 #define MAX_PLUS_SHARED_IRQS NR_IRQS
121 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
122
123 /*
124 * This is performance-critical, we want to do it O(1)
125 *
126 * the indexing order of this array favors 1:1 mappings
127 * between pins and IRQs.
128 */
129
130 static struct irq_pin_list {
131 short apic, pin, next;
132 } irq_2_pin[PIN_MAP_SIZE];
133
134 struct io_apic {
135 unsigned int index;
136 unsigned int unused[3];
137 unsigned int data;
138 };
139
140 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
141 {
142 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
143 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
144 }
145
146 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
147 {
148 struct io_apic __iomem *io_apic = io_apic_base(apic);
149 writel(reg, &io_apic->index);
150 return readl(&io_apic->data);
151 }
152
153 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
154 {
155 struct io_apic __iomem *io_apic = io_apic_base(apic);
156 writel(reg, &io_apic->index);
157 writel(value, &io_apic->data);
158 }
159
160 /*
161 * Re-write a value: to be used for read-modify-write
162 * cycles where the read already set up the index register.
163 */
164 static inline void io_apic_modify(unsigned int apic, unsigned int value)
165 {
166 struct io_apic __iomem *io_apic = io_apic_base(apic);
167 writel(value, &io_apic->data);
168 }
169
170 static bool io_apic_level_ack_pending(unsigned int irq)
171 {
172 struct irq_pin_list *entry;
173 unsigned long flags;
174
175 spin_lock_irqsave(&ioapic_lock, flags);
176 entry = irq_2_pin + irq;
177 for (;;) {
178 unsigned int reg;
179 int pin;
180
181 pin = entry->pin;
182 if (pin == -1)
183 break;
184 reg = io_apic_read(entry->apic, 0x10 + pin*2);
185 /* Is the remote IRR bit set? */
186 if ((reg >> 14) & 1) {
187 spin_unlock_irqrestore(&ioapic_lock, flags);
188 return true;
189 }
190 if (!entry->next)
191 break;
192 entry = irq_2_pin + entry->next;
193 }
194 spin_unlock_irqrestore(&ioapic_lock, flags);
195
196 return false;
197 }
198
199 /*
200 * Synchronize the IO-APIC and the CPU by doing
201 * a dummy read from the IO-APIC
202 */
203 static inline void io_apic_sync(unsigned int apic)
204 {
205 struct io_apic __iomem *io_apic = io_apic_base(apic);
206 readl(&io_apic->data);
207 }
208
209 #define __DO_ACTION(R, ACTION, FINAL) \
210 \
211 { \
212 int pin; \
213 struct irq_pin_list *entry = irq_2_pin + irq; \
214 \
215 BUG_ON(irq >= NR_IRQS); \
216 for (;;) { \
217 unsigned int reg; \
218 pin = entry->pin; \
219 if (pin == -1) \
220 break; \
221 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
222 reg ACTION; \
223 io_apic_modify(entry->apic, reg); \
224 FINAL; \
225 if (!entry->next) \
226 break; \
227 entry = irq_2_pin + entry->next; \
228 } \
229 }
230
231 union entry_union {
232 struct { u32 w1, w2; };
233 struct IO_APIC_route_entry entry;
234 };
235
236 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
237 {
238 union entry_union eu;
239 unsigned long flags;
240 spin_lock_irqsave(&ioapic_lock, flags);
241 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
242 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
243 spin_unlock_irqrestore(&ioapic_lock, flags);
244 return eu.entry;
245 }
246
247 /*
248 * When we write a new IO APIC routing entry, we need to write the high
249 * word first! If the mask bit in the low word is clear, we will enable
250 * the interrupt, and we need to make sure the entry is fully populated
251 * before that happens.
252 */
253 static void
254 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
255 {
256 union entry_union eu;
257 eu.entry = e;
258 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
259 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
260 }
261
262 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
263 {
264 unsigned long flags;
265 spin_lock_irqsave(&ioapic_lock, flags);
266 __ioapic_write_entry(apic, pin, e);
267 spin_unlock_irqrestore(&ioapic_lock, flags);
268 }
269
270 /*
271 * When we mask an IO APIC routing entry, we need to write the low
272 * word first, in order to set the mask bit before we change the
273 * high bits!
274 */
275 static void ioapic_mask_entry(int apic, int pin)
276 {
277 unsigned long flags;
278 union entry_union eu = { .entry.mask = 1 };
279
280 spin_lock_irqsave(&ioapic_lock, flags);
281 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
282 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
283 spin_unlock_irqrestore(&ioapic_lock, flags);
284 }
285
286 #ifdef CONFIG_SMP
287 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
288 {
289 int apic, pin;
290 struct irq_pin_list *entry = irq_2_pin + irq;
291
292 BUG_ON(irq >= NR_IRQS);
293 for (;;) {
294 unsigned int reg;
295 apic = entry->apic;
296 pin = entry->pin;
297 if (pin == -1)
298 break;
299 io_apic_write(apic, 0x11 + pin*2, dest);
300 reg = io_apic_read(apic, 0x10 + pin*2);
301 reg &= ~0x000000ff;
302 reg |= vector;
303 io_apic_modify(apic, reg);
304 if (!entry->next)
305 break;
306 entry = irq_2_pin + entry->next;
307 }
308 }
309
310 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
311 {
312 struct irq_cfg *cfg = irq_cfg + irq;
313 unsigned long flags;
314 unsigned int dest;
315 cpumask_t tmp;
316
317 cpus_and(tmp, mask, cpu_online_map);
318 if (cpus_empty(tmp))
319 return;
320
321 if (assign_irq_vector(irq, mask))
322 return;
323
324 cpus_and(tmp, cfg->domain, mask);
325 dest = cpu_mask_to_apicid(tmp);
326
327 /*
328 * Only the high 8 bits are valid.
329 */
330 dest = SET_APIC_LOGICAL_ID(dest);
331
332 spin_lock_irqsave(&ioapic_lock, flags);
333 __target_IO_APIC_irq(irq, dest, cfg->vector);
334 irq_desc[irq].affinity = mask;
335 spin_unlock_irqrestore(&ioapic_lock, flags);
336 }
337 #endif
338
339 /*
340 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
341 * shared ISA-space IRQs, so we have to support them. We are super
342 * fast in the common case, and fast for shared ISA-space IRQs.
343 */
344 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
345 {
346 static int first_free_entry = NR_IRQS;
347 struct irq_pin_list *entry = irq_2_pin + irq;
348
349 BUG_ON(irq >= NR_IRQS);
350 while (entry->next)
351 entry = irq_2_pin + entry->next;
352
353 if (entry->pin != -1) {
354 entry->next = first_free_entry;
355 entry = irq_2_pin + entry->next;
356 if (++first_free_entry >= PIN_MAP_SIZE)
357 panic("io_apic.c: ran out of irq_2_pin entries!");
358 }
359 entry->apic = apic;
360 entry->pin = pin;
361 }
362
363
364 #define DO_ACTION(name,R,ACTION, FINAL) \
365 \
366 static void name##_IO_APIC_irq (unsigned int irq) \
367 __DO_ACTION(R, ACTION, FINAL)
368
369 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
370 /* mask = 1 */
371 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
372 /* mask = 0 */
373
374 static void mask_IO_APIC_irq (unsigned int irq)
375 {
376 unsigned long flags;
377
378 spin_lock_irqsave(&ioapic_lock, flags);
379 __mask_IO_APIC_irq(irq);
380 spin_unlock_irqrestore(&ioapic_lock, flags);
381 }
382
383 static void unmask_IO_APIC_irq (unsigned int irq)
384 {
385 unsigned long flags;
386
387 spin_lock_irqsave(&ioapic_lock, flags);
388 __unmask_IO_APIC_irq(irq);
389 spin_unlock_irqrestore(&ioapic_lock, flags);
390 }
391
392 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
393 {
394 struct IO_APIC_route_entry entry;
395
396 /* Check delivery_mode to be sure we're not clearing an SMI pin */
397 entry = ioapic_read_entry(apic, pin);
398 if (entry.delivery_mode == dest_SMI)
399 return;
400 /*
401 * Disable it in the IO-APIC irq-routing table:
402 */
403 ioapic_mask_entry(apic, pin);
404 }
405
406 static void clear_IO_APIC (void)
407 {
408 int apic, pin;
409
410 for (apic = 0; apic < nr_ioapics; apic++)
411 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
412 clear_IO_APIC_pin(apic, pin);
413 }
414
415 int skip_ioapic_setup;
416 int ioapic_force;
417
418 static int __init parse_noapic(char *str)
419 {
420 disable_ioapic_setup();
421 return 0;
422 }
423 early_param("noapic", parse_noapic);
424
425 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
426 static int __init disable_timer_pin_setup(char *arg)
427 {
428 disable_timer_pin_1 = 1;
429 return 1;
430 }
431 __setup("disable_timer_pin_1", disable_timer_pin_setup);
432
433 static int __init setup_disable_8254_timer(char *s)
434 {
435 timer_over_8254 = -1;
436 return 1;
437 }
438 static int __init setup_enable_8254_timer(char *s)
439 {
440 timer_over_8254 = 2;
441 return 1;
442 }
443
444 __setup("disable_8254_timer", setup_disable_8254_timer);
445 __setup("enable_8254_timer", setup_enable_8254_timer);
446
447
448 /*
449 * Find the IRQ entry number of a certain pin.
450 */
451 static int find_irq_entry(int apic, int pin, int type)
452 {
453 int i;
454
455 for (i = 0; i < mp_irq_entries; i++)
456 if (mp_irqs[i].mpc_irqtype == type &&
457 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
458 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
459 mp_irqs[i].mpc_dstirq == pin)
460 return i;
461
462 return -1;
463 }
464
465 /*
466 * Find the pin to which IRQ[irq] (ISA) is connected
467 */
468 static int __init find_isa_irq_pin(int irq, int type)
469 {
470 int i;
471
472 for (i = 0; i < mp_irq_entries; i++) {
473 int lbus = mp_irqs[i].mpc_srcbus;
474
475 if (test_bit(lbus, mp_bus_not_pci) &&
476 (mp_irqs[i].mpc_irqtype == type) &&
477 (mp_irqs[i].mpc_srcbusirq == irq))
478
479 return mp_irqs[i].mpc_dstirq;
480 }
481 return -1;
482 }
483
484 static int __init find_isa_irq_apic(int irq, int type)
485 {
486 int i;
487
488 for (i = 0; i < mp_irq_entries; i++) {
489 int lbus = mp_irqs[i].mpc_srcbus;
490
491 if (test_bit(lbus, mp_bus_not_pci) &&
492 (mp_irqs[i].mpc_irqtype == type) &&
493 (mp_irqs[i].mpc_srcbusirq == irq))
494 break;
495 }
496 if (i < mp_irq_entries) {
497 int apic;
498 for(apic = 0; apic < nr_ioapics; apic++) {
499 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
500 return apic;
501 }
502 }
503
504 return -1;
505 }
506
507 /*
508 * Find a specific PCI IRQ entry.
509 * Not an __init, possibly needed by modules
510 */
511 static int pin_2_irq(int idx, int apic, int pin);
512
513 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
514 {
515 int apic, i, best_guess = -1;
516
517 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
518 bus, slot, pin);
519 if (mp_bus_id_to_pci_bus[bus] == -1) {
520 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
521 return -1;
522 }
523 for (i = 0; i < mp_irq_entries; i++) {
524 int lbus = mp_irqs[i].mpc_srcbus;
525
526 for (apic = 0; apic < nr_ioapics; apic++)
527 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
528 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
529 break;
530
531 if (!test_bit(lbus, mp_bus_not_pci) &&
532 !mp_irqs[i].mpc_irqtype &&
533 (bus == lbus) &&
534 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
535 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
536
537 if (!(apic || IO_APIC_IRQ(irq)))
538 continue;
539
540 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
541 return irq;
542 /*
543 * Use the first all-but-pin matching entry as a
544 * best-guess fuzzy result for broken mptables.
545 */
546 if (best_guess < 0)
547 best_guess = irq;
548 }
549 }
550 BUG_ON(best_guess >= NR_IRQS);
551 return best_guess;
552 }
553
554 /* ISA interrupts are always polarity zero edge triggered,
555 * when listed as conforming in the MP table. */
556
557 #define default_ISA_trigger(idx) (0)
558 #define default_ISA_polarity(idx) (0)
559
560 /* PCI interrupts are always polarity one level triggered,
561 * when listed as conforming in the MP table. */
562
563 #define default_PCI_trigger(idx) (1)
564 #define default_PCI_polarity(idx) (1)
565
566 static int MPBIOS_polarity(int idx)
567 {
568 int bus = mp_irqs[idx].mpc_srcbus;
569 int polarity;
570
571 /*
572 * Determine IRQ line polarity (high active or low active):
573 */
574 switch (mp_irqs[idx].mpc_irqflag & 3)
575 {
576 case 0: /* conforms, ie. bus-type dependent polarity */
577 if (test_bit(bus, mp_bus_not_pci))
578 polarity = default_ISA_polarity(idx);
579 else
580 polarity = default_PCI_polarity(idx);
581 break;
582 case 1: /* high active */
583 {
584 polarity = 0;
585 break;
586 }
587 case 2: /* reserved */
588 {
589 printk(KERN_WARNING "broken BIOS!!\n");
590 polarity = 1;
591 break;
592 }
593 case 3: /* low active */
594 {
595 polarity = 1;
596 break;
597 }
598 default: /* invalid */
599 {
600 printk(KERN_WARNING "broken BIOS!!\n");
601 polarity = 1;
602 break;
603 }
604 }
605 return polarity;
606 }
607
608 static int MPBIOS_trigger(int idx)
609 {
610 int bus = mp_irqs[idx].mpc_srcbus;
611 int trigger;
612
613 /*
614 * Determine IRQ trigger mode (edge or level sensitive):
615 */
616 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
617 {
618 case 0: /* conforms, ie. bus-type dependent */
619 if (test_bit(bus, mp_bus_not_pci))
620 trigger = default_ISA_trigger(idx);
621 else
622 trigger = default_PCI_trigger(idx);
623 break;
624 case 1: /* edge */
625 {
626 trigger = 0;
627 break;
628 }
629 case 2: /* reserved */
630 {
631 printk(KERN_WARNING "broken BIOS!!\n");
632 trigger = 1;
633 break;
634 }
635 case 3: /* level */
636 {
637 trigger = 1;
638 break;
639 }
640 default: /* invalid */
641 {
642 printk(KERN_WARNING "broken BIOS!!\n");
643 trigger = 0;
644 break;
645 }
646 }
647 return trigger;
648 }
649
650 static inline int irq_polarity(int idx)
651 {
652 return MPBIOS_polarity(idx);
653 }
654
655 static inline int irq_trigger(int idx)
656 {
657 return MPBIOS_trigger(idx);
658 }
659
660 static int pin_2_irq(int idx, int apic, int pin)
661 {
662 int irq, i;
663 int bus = mp_irqs[idx].mpc_srcbus;
664
665 /*
666 * Debugging check, we are in big trouble if this message pops up!
667 */
668 if (mp_irqs[idx].mpc_dstirq != pin)
669 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
670
671 if (test_bit(bus, mp_bus_not_pci)) {
672 irq = mp_irqs[idx].mpc_srcbusirq;
673 } else {
674 /*
675 * PCI IRQs are mapped in order
676 */
677 i = irq = 0;
678 while (i < apic)
679 irq += nr_ioapic_registers[i++];
680 irq += pin;
681 }
682 BUG_ON(irq >= NR_IRQS);
683 return irq;
684 }
685
686 static int __assign_irq_vector(int irq, cpumask_t mask)
687 {
688 /*
689 * NOTE! The local APIC isn't very good at handling
690 * multiple interrupts at the same interrupt level.
691 * As the interrupt level is determined by taking the
692 * vector number and shifting that right by 4, we
693 * want to spread these out a bit so that they don't
694 * all fall in the same interrupt level.
695 *
696 * Also, we've got to be careful not to trash gate
697 * 0x80, because int 0x80 is hm, kind of importantish. ;)
698 */
699 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
700 unsigned int old_vector;
701 int cpu;
702 struct irq_cfg *cfg;
703
704 BUG_ON((unsigned)irq >= NR_IRQS);
705 cfg = &irq_cfg[irq];
706
707 /* Only try and allocate irqs on cpus that are present */
708 cpus_and(mask, mask, cpu_online_map);
709
710 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
711 return -EBUSY;
712
713 old_vector = cfg->vector;
714 if (old_vector) {
715 cpumask_t tmp;
716 cpus_and(tmp, cfg->domain, mask);
717 if (!cpus_empty(tmp))
718 return 0;
719 }
720
721 for_each_cpu_mask(cpu, mask) {
722 cpumask_t domain, new_mask;
723 int new_cpu;
724 int vector, offset;
725
726 domain = vector_allocation_domain(cpu);
727 cpus_and(new_mask, domain, cpu_online_map);
728
729 vector = current_vector;
730 offset = current_offset;
731 next:
732 vector += 8;
733 if (vector >= FIRST_SYSTEM_VECTOR) {
734 /* If we run out of vectors on large boxen, must share them. */
735 offset = (offset + 1) % 8;
736 vector = FIRST_DEVICE_VECTOR + offset;
737 }
738 if (unlikely(current_vector == vector))
739 continue;
740 if (vector == IA32_SYSCALL_VECTOR)
741 goto next;
742 for_each_cpu_mask(new_cpu, new_mask)
743 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
744 goto next;
745 /* Found one! */
746 current_vector = vector;
747 current_offset = offset;
748 if (old_vector) {
749 cfg->move_in_progress = 1;
750 cfg->old_domain = cfg->domain;
751 }
752 for_each_cpu_mask(new_cpu, new_mask)
753 per_cpu(vector_irq, new_cpu)[vector] = irq;
754 cfg->vector = vector;
755 cfg->domain = domain;
756 return 0;
757 }
758 return -ENOSPC;
759 }
760
761 static int assign_irq_vector(int irq, cpumask_t mask)
762 {
763 int err;
764 unsigned long flags;
765
766 spin_lock_irqsave(&vector_lock, flags);
767 err = __assign_irq_vector(irq, mask);
768 spin_unlock_irqrestore(&vector_lock, flags);
769 return err;
770 }
771
772 static void __clear_irq_vector(int irq)
773 {
774 struct irq_cfg *cfg;
775 cpumask_t mask;
776 int cpu, vector;
777
778 BUG_ON((unsigned)irq >= NR_IRQS);
779 cfg = &irq_cfg[irq];
780 BUG_ON(!cfg->vector);
781
782 vector = cfg->vector;
783 cpus_and(mask, cfg->domain, cpu_online_map);
784 for_each_cpu_mask(cpu, mask)
785 per_cpu(vector_irq, cpu)[vector] = -1;
786
787 cfg->vector = 0;
788 cfg->domain = CPU_MASK_NONE;
789 }
790
791 void __setup_vector_irq(int cpu)
792 {
793 /* Initialize vector_irq on a new cpu */
794 /* This function must be called with vector_lock held */
795 int irq, vector;
796
797 /* Mark the inuse vectors */
798 for (irq = 0; irq < NR_IRQS; ++irq) {
799 if (!cpu_isset(cpu, irq_cfg[irq].domain))
800 continue;
801 vector = irq_cfg[irq].vector;
802 per_cpu(vector_irq, cpu)[vector] = irq;
803 }
804 /* Mark the free vectors */
805 for (vector = 0; vector < NR_VECTORS; ++vector) {
806 irq = per_cpu(vector_irq, cpu)[vector];
807 if (irq < 0)
808 continue;
809 if (!cpu_isset(cpu, irq_cfg[irq].domain))
810 per_cpu(vector_irq, cpu)[vector] = -1;
811 }
812 }
813
814
815 static struct irq_chip ioapic_chip;
816
817 static void ioapic_register_intr(int irq, unsigned long trigger)
818 {
819 if (trigger) {
820 irq_desc[irq].status |= IRQ_LEVEL;
821 set_irq_chip_and_handler_name(irq, &ioapic_chip,
822 handle_fasteoi_irq, "fasteoi");
823 } else {
824 irq_desc[irq].status &= ~IRQ_LEVEL;
825 set_irq_chip_and_handler_name(irq, &ioapic_chip,
826 handle_edge_irq, "edge");
827 }
828 }
829
830 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
831 int trigger, int polarity)
832 {
833 struct irq_cfg *cfg = irq_cfg + irq;
834 struct IO_APIC_route_entry entry;
835 cpumask_t mask;
836
837 if (!IO_APIC_IRQ(irq))
838 return;
839
840 mask = TARGET_CPUS;
841 if (assign_irq_vector(irq, mask))
842 return;
843
844 cpus_and(mask, cfg->domain, mask);
845
846 apic_printk(APIC_VERBOSE,KERN_DEBUG
847 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
848 "IRQ %d Mode:%i Active:%i)\n",
849 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
850 irq, trigger, polarity);
851
852 /*
853 * add it to the IO-APIC irq-routing table:
854 */
855 memset(&entry,0,sizeof(entry));
856
857 entry.delivery_mode = INT_DELIVERY_MODE;
858 entry.dest_mode = INT_DEST_MODE;
859 entry.dest = cpu_mask_to_apicid(mask);
860 entry.mask = 0; /* enable IRQ */
861 entry.trigger = trigger;
862 entry.polarity = polarity;
863 entry.vector = cfg->vector;
864
865 /* Mask level triggered irqs.
866 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
867 */
868 if (trigger)
869 entry.mask = 1;
870
871 ioapic_register_intr(irq, trigger);
872 if (irq < 16)
873 disable_8259A_irq(irq);
874
875 ioapic_write_entry(apic, pin, entry);
876 }
877
878 static void __init setup_IO_APIC_irqs(void)
879 {
880 int apic, pin, idx, irq, first_notcon = 1;
881
882 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
883
884 for (apic = 0; apic < nr_ioapics; apic++) {
885 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
886
887 idx = find_irq_entry(apic,pin,mp_INT);
888 if (idx == -1) {
889 if (first_notcon) {
890 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
891 first_notcon = 0;
892 } else
893 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
894 continue;
895 }
896 if (!first_notcon) {
897 apic_printk(APIC_VERBOSE, " not connected.\n");
898 first_notcon = 1;
899 }
900
901 irq = pin_2_irq(idx, apic, pin);
902 add_pin_to_irq(irq, apic, pin);
903
904 setup_IO_APIC_irq(apic, pin, irq,
905 irq_trigger(idx), irq_polarity(idx));
906 }
907 }
908
909 if (!first_notcon)
910 apic_printk(APIC_VERBOSE, " not connected.\n");
911 }
912
913 /*
914 * Set up the 8259A-master output pin as broadcast to all
915 * CPUs.
916 */
917 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
918 {
919 struct IO_APIC_route_entry entry;
920 unsigned long flags;
921
922 memset(&entry,0,sizeof(entry));
923
924 disable_8259A_irq(0);
925
926 /* mask LVT0 */
927 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
928
929 /*
930 * We use logical delivery to get the timer IRQ
931 * to the first CPU.
932 */
933 entry.dest_mode = INT_DEST_MODE;
934 entry.mask = 0; /* unmask IRQ now */
935 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
936 entry.delivery_mode = INT_DELIVERY_MODE;
937 entry.polarity = 0;
938 entry.trigger = 0;
939 entry.vector = vector;
940
941 /*
942 * The timer IRQ doesn't have to know that behind the
943 * scene we have a 8259A-master in AEOI mode ...
944 */
945 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
946
947 /*
948 * Add it to the IO-APIC irq-routing table:
949 */
950 spin_lock_irqsave(&ioapic_lock, flags);
951 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
952 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
953 spin_unlock_irqrestore(&ioapic_lock, flags);
954
955 enable_8259A_irq(0);
956 }
957
958 void __apicdebuginit print_IO_APIC(void)
959 {
960 int apic, i;
961 union IO_APIC_reg_00 reg_00;
962 union IO_APIC_reg_01 reg_01;
963 union IO_APIC_reg_02 reg_02;
964 unsigned long flags;
965
966 if (apic_verbosity == APIC_QUIET)
967 return;
968
969 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
970 for (i = 0; i < nr_ioapics; i++)
971 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
972 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
973
974 /*
975 * We are a bit conservative about what we expect. We have to
976 * know about every hardware change ASAP.
977 */
978 printk(KERN_INFO "testing the IO APIC.......................\n");
979
980 for (apic = 0; apic < nr_ioapics; apic++) {
981
982 spin_lock_irqsave(&ioapic_lock, flags);
983 reg_00.raw = io_apic_read(apic, 0);
984 reg_01.raw = io_apic_read(apic, 1);
985 if (reg_01.bits.version >= 0x10)
986 reg_02.raw = io_apic_read(apic, 2);
987 spin_unlock_irqrestore(&ioapic_lock, flags);
988
989 printk("\n");
990 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
991 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
992 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
993
994 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
995 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
996
997 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
998 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
999
1000 if (reg_01.bits.version >= 0x10) {
1001 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1002 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1003 }
1004
1005 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1006
1007 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1008 " Stat Dmod Deli Vect: \n");
1009
1010 for (i = 0; i <= reg_01.bits.entries; i++) {
1011 struct IO_APIC_route_entry entry;
1012
1013 entry = ioapic_read_entry(apic, i);
1014
1015 printk(KERN_DEBUG " %02x %03X ",
1016 i,
1017 entry.dest
1018 );
1019
1020 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1021 entry.mask,
1022 entry.trigger,
1023 entry.irr,
1024 entry.polarity,
1025 entry.delivery_status,
1026 entry.dest_mode,
1027 entry.delivery_mode,
1028 entry.vector
1029 );
1030 }
1031 }
1032 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1033 for (i = 0; i < NR_IRQS; i++) {
1034 struct irq_pin_list *entry = irq_2_pin + i;
1035 if (entry->pin < 0)
1036 continue;
1037 printk(KERN_DEBUG "IRQ%d ", i);
1038 for (;;) {
1039 printk("-> %d:%d", entry->apic, entry->pin);
1040 if (!entry->next)
1041 break;
1042 entry = irq_2_pin + entry->next;
1043 }
1044 printk("\n");
1045 }
1046
1047 printk(KERN_INFO ".................................... done.\n");
1048
1049 return;
1050 }
1051
1052 #if 0
1053
1054 static __apicdebuginit void print_APIC_bitfield (int base)
1055 {
1056 unsigned int v;
1057 int i, j;
1058
1059 if (apic_verbosity == APIC_QUIET)
1060 return;
1061
1062 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1063 for (i = 0; i < 8; i++) {
1064 v = apic_read(base + i*0x10);
1065 for (j = 0; j < 32; j++) {
1066 if (v & (1<<j))
1067 printk("1");
1068 else
1069 printk("0");
1070 }
1071 printk("\n");
1072 }
1073 }
1074
1075 void __apicdebuginit print_local_APIC(void * dummy)
1076 {
1077 unsigned int v, ver, maxlvt;
1078
1079 if (apic_verbosity == APIC_QUIET)
1080 return;
1081
1082 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1083 smp_processor_id(), hard_smp_processor_id());
1084 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1085 v = apic_read(APIC_LVR);
1086 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1087 ver = GET_APIC_VERSION(v);
1088 maxlvt = lapic_get_maxlvt();
1089
1090 v = apic_read(APIC_TASKPRI);
1091 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1092
1093 v = apic_read(APIC_ARBPRI);
1094 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1095 v & APIC_ARBPRI_MASK);
1096 v = apic_read(APIC_PROCPRI);
1097 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1098
1099 v = apic_read(APIC_EOI);
1100 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1101 v = apic_read(APIC_RRR);
1102 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1103 v = apic_read(APIC_LDR);
1104 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1105 v = apic_read(APIC_DFR);
1106 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1107 v = apic_read(APIC_SPIV);
1108 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1109
1110 printk(KERN_DEBUG "... APIC ISR field:\n");
1111 print_APIC_bitfield(APIC_ISR);
1112 printk(KERN_DEBUG "... APIC TMR field:\n");
1113 print_APIC_bitfield(APIC_TMR);
1114 printk(KERN_DEBUG "... APIC IRR field:\n");
1115 print_APIC_bitfield(APIC_IRR);
1116
1117 v = apic_read(APIC_ESR);
1118 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1119
1120 v = apic_read(APIC_ICR);
1121 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1122 v = apic_read(APIC_ICR2);
1123 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1124
1125 v = apic_read(APIC_LVTT);
1126 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1127
1128 if (maxlvt > 3) { /* PC is LVT#4. */
1129 v = apic_read(APIC_LVTPC);
1130 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1131 }
1132 v = apic_read(APIC_LVT0);
1133 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1134 v = apic_read(APIC_LVT1);
1135 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1136
1137 if (maxlvt > 2) { /* ERR is LVT#3. */
1138 v = apic_read(APIC_LVTERR);
1139 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1140 }
1141
1142 v = apic_read(APIC_TMICT);
1143 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1144 v = apic_read(APIC_TMCCT);
1145 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1146 v = apic_read(APIC_TDCR);
1147 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1148 printk("\n");
1149 }
1150
1151 void print_all_local_APICs (void)
1152 {
1153 on_each_cpu(print_local_APIC, NULL, 1, 1);
1154 }
1155
1156 void __apicdebuginit print_PIC(void)
1157 {
1158 unsigned int v;
1159 unsigned long flags;
1160
1161 if (apic_verbosity == APIC_QUIET)
1162 return;
1163
1164 printk(KERN_DEBUG "\nprinting PIC contents\n");
1165
1166 spin_lock_irqsave(&i8259A_lock, flags);
1167
1168 v = inb(0xa1) << 8 | inb(0x21);
1169 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1170
1171 v = inb(0xa0) << 8 | inb(0x20);
1172 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1173
1174 outb(0x0b,0xa0);
1175 outb(0x0b,0x20);
1176 v = inb(0xa0) << 8 | inb(0x20);
1177 outb(0x0a,0xa0);
1178 outb(0x0a,0x20);
1179
1180 spin_unlock_irqrestore(&i8259A_lock, flags);
1181
1182 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1183
1184 v = inb(0x4d1) << 8 | inb(0x4d0);
1185 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1186 }
1187
1188 #endif /* 0 */
1189
1190 void __init enable_IO_APIC(void)
1191 {
1192 union IO_APIC_reg_01 reg_01;
1193 int i8259_apic, i8259_pin;
1194 int i, apic;
1195 unsigned long flags;
1196
1197 for (i = 0; i < PIN_MAP_SIZE; i++) {
1198 irq_2_pin[i].pin = -1;
1199 irq_2_pin[i].next = 0;
1200 }
1201
1202 /*
1203 * The number of IO-APIC IRQ registers (== #pins):
1204 */
1205 for (apic = 0; apic < nr_ioapics; apic++) {
1206 spin_lock_irqsave(&ioapic_lock, flags);
1207 reg_01.raw = io_apic_read(apic, 1);
1208 spin_unlock_irqrestore(&ioapic_lock, flags);
1209 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1210 }
1211 for(apic = 0; apic < nr_ioapics; apic++) {
1212 int pin;
1213 /* See if any of the pins is in ExtINT mode */
1214 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1215 struct IO_APIC_route_entry entry;
1216 entry = ioapic_read_entry(apic, pin);
1217
1218 /* If the interrupt line is enabled and in ExtInt mode
1219 * I have found the pin where the i8259 is connected.
1220 */
1221 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1222 ioapic_i8259.apic = apic;
1223 ioapic_i8259.pin = pin;
1224 goto found_i8259;
1225 }
1226 }
1227 }
1228 found_i8259:
1229 /* Look to see what if the MP table has reported the ExtINT */
1230 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1231 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1232 /* Trust the MP table if nothing is setup in the hardware */
1233 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1234 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1235 ioapic_i8259.pin = i8259_pin;
1236 ioapic_i8259.apic = i8259_apic;
1237 }
1238 /* Complain if the MP table and the hardware disagree */
1239 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1240 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1241 {
1242 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1243 }
1244
1245 /*
1246 * Do not trust the IO-APIC being empty at bootup
1247 */
1248 clear_IO_APIC();
1249 }
1250
1251 /*
1252 * Not an __init, needed by the reboot code
1253 */
1254 void disable_IO_APIC(void)
1255 {
1256 /*
1257 * Clear the IO-APIC before rebooting:
1258 */
1259 clear_IO_APIC();
1260
1261 /*
1262 * If the i8259 is routed through an IOAPIC
1263 * Put that IOAPIC in virtual wire mode
1264 * so legacy interrupts can be delivered.
1265 */
1266 if (ioapic_i8259.pin != -1) {
1267 struct IO_APIC_route_entry entry;
1268
1269 memset(&entry, 0, sizeof(entry));
1270 entry.mask = 0; /* Enabled */
1271 entry.trigger = 0; /* Edge */
1272 entry.irr = 0;
1273 entry.polarity = 0; /* High */
1274 entry.delivery_status = 0;
1275 entry.dest_mode = 0; /* Physical */
1276 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1277 entry.vector = 0;
1278 entry.dest = GET_APIC_ID(read_apic_id());
1279
1280 /*
1281 * Add it to the IO-APIC irq-routing table:
1282 */
1283 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1284 }
1285
1286 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1287 }
1288
1289 /*
1290 * There is a nasty bug in some older SMP boards, their mptable lies
1291 * about the timer IRQ. We do the following to work around the situation:
1292 *
1293 * - timer IRQ defaults to IO-APIC IRQ
1294 * - if this function detects that timer IRQs are defunct, then we fall
1295 * back to ISA timer IRQs
1296 */
1297 static int __init timer_irq_works(void)
1298 {
1299 unsigned long t1 = jiffies;
1300 unsigned long flags;
1301
1302 local_save_flags(flags);
1303 local_irq_enable();
1304 /* Let ten ticks pass... */
1305 mdelay((10 * 1000) / HZ);
1306 local_irq_restore(flags);
1307
1308 /*
1309 * Expect a few ticks at least, to be sure some possible
1310 * glue logic does not lock up after one or two first
1311 * ticks in a non-ExtINT mode. Also the local APIC
1312 * might have cached one ExtINT interrupt. Finally, at
1313 * least one tick may be lost due to delays.
1314 */
1315
1316 /* jiffies wrap? */
1317 if (time_after(jiffies, t1 + 4))
1318 return 1;
1319 return 0;
1320 }
1321
1322 /*
1323 * In the SMP+IOAPIC case it might happen that there are an unspecified
1324 * number of pending IRQ events unhandled. These cases are very rare,
1325 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1326 * better to do it this way as thus we do not have to be aware of
1327 * 'pending' interrupts in the IRQ path, except at this point.
1328 */
1329 /*
1330 * Edge triggered needs to resend any interrupt
1331 * that was delayed but this is now handled in the device
1332 * independent code.
1333 */
1334
1335 /*
1336 * Starting up a edge-triggered IO-APIC interrupt is
1337 * nasty - we need to make sure that we get the edge.
1338 * If it is already asserted for some reason, we need
1339 * return 1 to indicate that is was pending.
1340 *
1341 * This is not complete - we should be able to fake
1342 * an edge even if it isn't on the 8259A...
1343 */
1344
1345 static unsigned int startup_ioapic_irq(unsigned int irq)
1346 {
1347 int was_pending = 0;
1348 unsigned long flags;
1349
1350 spin_lock_irqsave(&ioapic_lock, flags);
1351 if (irq < 16) {
1352 disable_8259A_irq(irq);
1353 if (i8259A_irq_pending(irq))
1354 was_pending = 1;
1355 }
1356 __unmask_IO_APIC_irq(irq);
1357 spin_unlock_irqrestore(&ioapic_lock, flags);
1358
1359 return was_pending;
1360 }
1361
1362 static int ioapic_retrigger_irq(unsigned int irq)
1363 {
1364 struct irq_cfg *cfg = &irq_cfg[irq];
1365 cpumask_t mask;
1366 unsigned long flags;
1367
1368 spin_lock_irqsave(&vector_lock, flags);
1369 cpus_clear(mask);
1370 cpu_set(first_cpu(cfg->domain), mask);
1371
1372 send_IPI_mask(mask, cfg->vector);
1373 spin_unlock_irqrestore(&vector_lock, flags);
1374
1375 return 1;
1376 }
1377
1378 /*
1379 * Level and edge triggered IO-APIC interrupts need different handling,
1380 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1381 * handled with the level-triggered descriptor, but that one has slightly
1382 * more overhead. Level-triggered interrupts cannot be handled with the
1383 * edge-triggered handler, without risking IRQ storms and other ugly
1384 * races.
1385 */
1386
1387 #ifdef CONFIG_SMP
1388 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1389 {
1390 unsigned vector, me;
1391 ack_APIC_irq();
1392 exit_idle();
1393 irq_enter();
1394
1395 me = smp_processor_id();
1396 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1397 unsigned int irq;
1398 struct irq_desc *desc;
1399 struct irq_cfg *cfg;
1400 irq = __get_cpu_var(vector_irq)[vector];
1401 if (irq >= NR_IRQS)
1402 continue;
1403
1404 desc = irq_desc + irq;
1405 cfg = irq_cfg + irq;
1406 spin_lock(&desc->lock);
1407 if (!cfg->move_cleanup_count)
1408 goto unlock;
1409
1410 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1411 goto unlock;
1412
1413 __get_cpu_var(vector_irq)[vector] = -1;
1414 cfg->move_cleanup_count--;
1415 unlock:
1416 spin_unlock(&desc->lock);
1417 }
1418
1419 irq_exit();
1420 }
1421
1422 static void irq_complete_move(unsigned int irq)
1423 {
1424 struct irq_cfg *cfg = irq_cfg + irq;
1425 unsigned vector, me;
1426
1427 if (likely(!cfg->move_in_progress))
1428 return;
1429
1430 vector = ~get_irq_regs()->orig_ax;
1431 me = smp_processor_id();
1432 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1433 cpumask_t cleanup_mask;
1434
1435 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1436 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1437 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1438 cfg->move_in_progress = 0;
1439 }
1440 }
1441 #else
1442 static inline void irq_complete_move(unsigned int irq) {}
1443 #endif
1444
1445 static void ack_apic_edge(unsigned int irq)
1446 {
1447 irq_complete_move(irq);
1448 move_native_irq(irq);
1449 ack_APIC_irq();
1450 }
1451
1452 static void ack_apic_level(unsigned int irq)
1453 {
1454 int do_unmask_irq = 0;
1455
1456 irq_complete_move(irq);
1457 #ifdef CONFIG_GENERIC_PENDING_IRQ
1458 /* If we are moving the irq we need to mask it */
1459 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1460 do_unmask_irq = 1;
1461 mask_IO_APIC_irq(irq);
1462 }
1463 #endif
1464
1465 /*
1466 * We must acknowledge the irq before we move it or the acknowledge will
1467 * not propagate properly.
1468 */
1469 ack_APIC_irq();
1470
1471 /* Now we can move and renable the irq */
1472 if (unlikely(do_unmask_irq)) {
1473 /* Only migrate the irq if the ack has been received.
1474 *
1475 * On rare occasions the broadcast level triggered ack gets
1476 * delayed going to ioapics, and if we reprogram the
1477 * vector while Remote IRR is still set the irq will never
1478 * fire again.
1479 *
1480 * To prevent this scenario we read the Remote IRR bit
1481 * of the ioapic. This has two effects.
1482 * - On any sane system the read of the ioapic will
1483 * flush writes (and acks) going to the ioapic from
1484 * this cpu.
1485 * - We get to see if the ACK has actually been delivered.
1486 *
1487 * Based on failed experiments of reprogramming the
1488 * ioapic entry from outside of irq context starting
1489 * with masking the ioapic entry and then polling until
1490 * Remote IRR was clear before reprogramming the
1491 * ioapic I don't trust the Remote IRR bit to be
1492 * completey accurate.
1493 *
1494 * However there appears to be no other way to plug
1495 * this race, so if the Remote IRR bit is not
1496 * accurate and is causing problems then it is a hardware bug
1497 * and you can go talk to the chipset vendor about it.
1498 */
1499 if (!io_apic_level_ack_pending(irq))
1500 move_masked_irq(irq);
1501 unmask_IO_APIC_irq(irq);
1502 }
1503 }
1504
1505 static struct irq_chip ioapic_chip __read_mostly = {
1506 .name = "IO-APIC",
1507 .startup = startup_ioapic_irq,
1508 .mask = mask_IO_APIC_irq,
1509 .unmask = unmask_IO_APIC_irq,
1510 .ack = ack_apic_edge,
1511 .eoi = ack_apic_level,
1512 #ifdef CONFIG_SMP
1513 .set_affinity = set_ioapic_affinity_irq,
1514 #endif
1515 .retrigger = ioapic_retrigger_irq,
1516 };
1517
1518 static inline void init_IO_APIC_traps(void)
1519 {
1520 int irq;
1521
1522 /*
1523 * NOTE! The local APIC isn't very good at handling
1524 * multiple interrupts at the same interrupt level.
1525 * As the interrupt level is determined by taking the
1526 * vector number and shifting that right by 4, we
1527 * want to spread these out a bit so that they don't
1528 * all fall in the same interrupt level.
1529 *
1530 * Also, we've got to be careful not to trash gate
1531 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1532 */
1533 for (irq = 0; irq < NR_IRQS ; irq++) {
1534 int tmp = irq;
1535 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1536 /*
1537 * Hmm.. We don't have an entry for this,
1538 * so default to an old-fashioned 8259
1539 * interrupt if we can..
1540 */
1541 if (irq < 16)
1542 make_8259A_irq(irq);
1543 else
1544 /* Strange. Oh, well.. */
1545 irq_desc[irq].chip = &no_irq_chip;
1546 }
1547 }
1548 }
1549
1550 static void enable_lapic_irq (unsigned int irq)
1551 {
1552 unsigned long v;
1553
1554 v = apic_read(APIC_LVT0);
1555 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1556 }
1557
1558 static void disable_lapic_irq (unsigned int irq)
1559 {
1560 unsigned long v;
1561
1562 v = apic_read(APIC_LVT0);
1563 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1564 }
1565
1566 static void ack_lapic_irq (unsigned int irq)
1567 {
1568 ack_APIC_irq();
1569 }
1570
1571 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1572
1573 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1574 .name = "local-APIC",
1575 .typename = "local-APIC-edge",
1576 .startup = NULL, /* startup_irq() not used for IRQ0 */
1577 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1578 .enable = enable_lapic_irq,
1579 .disable = disable_lapic_irq,
1580 .ack = ack_lapic_irq,
1581 .end = end_lapic_irq,
1582 };
1583
1584 static void __init setup_nmi(void)
1585 {
1586 /*
1587 * Dirty trick to enable the NMI watchdog ...
1588 * We put the 8259A master into AEOI mode and
1589 * unmask on all local APICs LVT0 as NMI.
1590 *
1591 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1592 * is from Maciej W. Rozycki - so we do not have to EOI from
1593 * the NMI handler or the timer interrupt.
1594 */
1595 printk(KERN_INFO "activating NMI Watchdog ...");
1596
1597 enable_NMI_through_LVT0();
1598
1599 printk(" done.\n");
1600 }
1601
1602 /*
1603 * This looks a bit hackish but it's about the only one way of sending
1604 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1605 * not support the ExtINT mode, unfortunately. We need to send these
1606 * cycles as some i82489DX-based boards have glue logic that keeps the
1607 * 8259A interrupt line asserted until INTA. --macro
1608 */
1609 static inline void unlock_ExtINT_logic(void)
1610 {
1611 int apic, pin, i;
1612 struct IO_APIC_route_entry entry0, entry1;
1613 unsigned char save_control, save_freq_select;
1614 unsigned long flags;
1615
1616 pin = find_isa_irq_pin(8, mp_INT);
1617 apic = find_isa_irq_apic(8, mp_INT);
1618 if (pin == -1)
1619 return;
1620
1621 spin_lock_irqsave(&ioapic_lock, flags);
1622 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1623 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1624 spin_unlock_irqrestore(&ioapic_lock, flags);
1625 clear_IO_APIC_pin(apic, pin);
1626
1627 memset(&entry1, 0, sizeof(entry1));
1628
1629 entry1.dest_mode = 0; /* physical delivery */
1630 entry1.mask = 0; /* unmask IRQ now */
1631 entry1.dest = hard_smp_processor_id();
1632 entry1.delivery_mode = dest_ExtINT;
1633 entry1.polarity = entry0.polarity;
1634 entry1.trigger = 0;
1635 entry1.vector = 0;
1636
1637 spin_lock_irqsave(&ioapic_lock, flags);
1638 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1639 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1640 spin_unlock_irqrestore(&ioapic_lock, flags);
1641
1642 save_control = CMOS_READ(RTC_CONTROL);
1643 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1644 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1645 RTC_FREQ_SELECT);
1646 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1647
1648 i = 100;
1649 while (i-- > 0) {
1650 mdelay(10);
1651 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1652 i -= 10;
1653 }
1654
1655 CMOS_WRITE(save_control, RTC_CONTROL);
1656 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1657 clear_IO_APIC_pin(apic, pin);
1658
1659 spin_lock_irqsave(&ioapic_lock, flags);
1660 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1661 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1662 spin_unlock_irqrestore(&ioapic_lock, flags);
1663 }
1664
1665 /*
1666 * This code may look a bit paranoid, but it's supposed to cooperate with
1667 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1668 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1669 * fanatically on his truly buggy board.
1670 *
1671 * FIXME: really need to revamp this for modern platforms only.
1672 */
1673 static inline void __init check_timer(void)
1674 {
1675 struct irq_cfg *cfg = irq_cfg + 0;
1676 int apic1, pin1, apic2, pin2;
1677 unsigned long flags;
1678
1679 local_irq_save(flags);
1680
1681 /*
1682 * get/set the timer IRQ vector:
1683 */
1684 disable_8259A_irq(0);
1685 assign_irq_vector(0, TARGET_CPUS);
1686
1687 /*
1688 * Subtle, code in do_timer_interrupt() expects an AEOI
1689 * mode for the 8259A whenever interrupts are routed
1690 * through I/O APICs. Also IRQ0 has to be enabled in
1691 * the 8259A which implies the virtual wire has to be
1692 * disabled in the local APIC.
1693 */
1694 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1695 init_8259A(1);
1696 if (timer_over_8254 > 0)
1697 enable_8259A_irq(0);
1698
1699 pin1 = find_isa_irq_pin(0, mp_INT);
1700 apic1 = find_isa_irq_apic(0, mp_INT);
1701 pin2 = ioapic_i8259.pin;
1702 apic2 = ioapic_i8259.apic;
1703
1704 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1705 cfg->vector, apic1, pin1, apic2, pin2);
1706
1707 if (pin1 != -1) {
1708 /*
1709 * Ok, does IRQ0 through the IOAPIC work?
1710 */
1711 unmask_IO_APIC_irq(0);
1712 if (!no_timer_check && timer_irq_works()) {
1713 nmi_watchdog_default();
1714 if (nmi_watchdog == NMI_IO_APIC) {
1715 disable_8259A_irq(0);
1716 setup_nmi();
1717 enable_8259A_irq(0);
1718 }
1719 if (disable_timer_pin_1 > 0)
1720 clear_IO_APIC_pin(0, pin1);
1721 goto out;
1722 }
1723 clear_IO_APIC_pin(apic1, pin1);
1724 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1725 "connected to IO-APIC\n");
1726 }
1727
1728 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1729 "through the 8259A ... ");
1730 if (pin2 != -1) {
1731 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1732 apic2, pin2);
1733 /*
1734 * legacy devices should be connected to IO APIC #0
1735 */
1736 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1737 if (timer_irq_works()) {
1738 apic_printk(APIC_VERBOSE," works.\n");
1739 nmi_watchdog_default();
1740 if (nmi_watchdog == NMI_IO_APIC) {
1741 setup_nmi();
1742 }
1743 goto out;
1744 }
1745 /*
1746 * Cleanup, just in case ...
1747 */
1748 clear_IO_APIC_pin(apic2, pin2);
1749 }
1750 apic_printk(APIC_VERBOSE," failed.\n");
1751
1752 if (nmi_watchdog == NMI_IO_APIC) {
1753 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1754 nmi_watchdog = 0;
1755 }
1756
1757 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1758
1759 disable_8259A_irq(0);
1760 irq_desc[0].chip = &lapic_irq_type;
1761 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1762 enable_8259A_irq(0);
1763
1764 if (timer_irq_works()) {
1765 apic_printk(APIC_VERBOSE," works.\n");
1766 goto out;
1767 }
1768 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1769 apic_printk(APIC_VERBOSE," failed.\n");
1770
1771 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1772
1773 init_8259A(0);
1774 make_8259A_irq(0);
1775 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1776
1777 unlock_ExtINT_logic();
1778
1779 if (timer_irq_works()) {
1780 apic_printk(APIC_VERBOSE," works.\n");
1781 goto out;
1782 }
1783 apic_printk(APIC_VERBOSE," failed :(.\n");
1784 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1785 out:
1786 local_irq_restore(flags);
1787 }
1788
1789 static int __init notimercheck(char *s)
1790 {
1791 no_timer_check = 1;
1792 return 1;
1793 }
1794 __setup("no_timer_check", notimercheck);
1795
1796 /*
1797 *
1798 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1799 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1800 * Linux doesn't really care, as it's not actually used
1801 * for any interrupt handling anyway.
1802 */
1803 #define PIC_IRQS (1<<2)
1804
1805 void __init setup_IO_APIC(void)
1806 {
1807
1808 /*
1809 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1810 */
1811
1812 if (acpi_ioapic)
1813 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1814 else
1815 io_apic_irqs = ~PIC_IRQS;
1816
1817 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1818
1819 sync_Arb_IDs();
1820 setup_IO_APIC_irqs();
1821 init_IO_APIC_traps();
1822 check_timer();
1823 if (!acpi_ioapic)
1824 print_IO_APIC();
1825 }
1826
1827 struct sysfs_ioapic_data {
1828 struct sys_device dev;
1829 struct IO_APIC_route_entry entry[0];
1830 };
1831 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1832
1833 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1834 {
1835 struct IO_APIC_route_entry *entry;
1836 struct sysfs_ioapic_data *data;
1837 int i;
1838
1839 data = container_of(dev, struct sysfs_ioapic_data, dev);
1840 entry = data->entry;
1841 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1842 *entry = ioapic_read_entry(dev->id, i);
1843
1844 return 0;
1845 }
1846
1847 static int ioapic_resume(struct sys_device *dev)
1848 {
1849 struct IO_APIC_route_entry *entry;
1850 struct sysfs_ioapic_data *data;
1851 unsigned long flags;
1852 union IO_APIC_reg_00 reg_00;
1853 int i;
1854
1855 data = container_of(dev, struct sysfs_ioapic_data, dev);
1856 entry = data->entry;
1857
1858 spin_lock_irqsave(&ioapic_lock, flags);
1859 reg_00.raw = io_apic_read(dev->id, 0);
1860 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1861 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1862 io_apic_write(dev->id, 0, reg_00.raw);
1863 }
1864 spin_unlock_irqrestore(&ioapic_lock, flags);
1865 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1866 ioapic_write_entry(dev->id, i, entry[i]);
1867
1868 return 0;
1869 }
1870
1871 static struct sysdev_class ioapic_sysdev_class = {
1872 .name = "ioapic",
1873 .suspend = ioapic_suspend,
1874 .resume = ioapic_resume,
1875 };
1876
1877 static int __init ioapic_init_sysfs(void)
1878 {
1879 struct sys_device * dev;
1880 int i, size, error;
1881
1882 error = sysdev_class_register(&ioapic_sysdev_class);
1883 if (error)
1884 return error;
1885
1886 for (i = 0; i < nr_ioapics; i++ ) {
1887 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1888 * sizeof(struct IO_APIC_route_entry);
1889 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1890 if (!mp_ioapic_data[i]) {
1891 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1892 continue;
1893 }
1894 dev = &mp_ioapic_data[i]->dev;
1895 dev->id = i;
1896 dev->cls = &ioapic_sysdev_class;
1897 error = sysdev_register(dev);
1898 if (error) {
1899 kfree(mp_ioapic_data[i]);
1900 mp_ioapic_data[i] = NULL;
1901 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1902 continue;
1903 }
1904 }
1905
1906 return 0;
1907 }
1908
1909 device_initcall(ioapic_init_sysfs);
1910
1911 /*
1912 * Dynamic irq allocate and deallocation
1913 */
1914 int create_irq(void)
1915 {
1916 /* Allocate an unused irq */
1917 int irq;
1918 int new;
1919 unsigned long flags;
1920
1921 irq = -ENOSPC;
1922 spin_lock_irqsave(&vector_lock, flags);
1923 for (new = (NR_IRQS - 1); new >= 0; new--) {
1924 if (platform_legacy_irq(new))
1925 continue;
1926 if (irq_cfg[new].vector != 0)
1927 continue;
1928 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1929 irq = new;
1930 break;
1931 }
1932 spin_unlock_irqrestore(&vector_lock, flags);
1933
1934 if (irq >= 0) {
1935 dynamic_irq_init(irq);
1936 }
1937 return irq;
1938 }
1939
1940 void destroy_irq(unsigned int irq)
1941 {
1942 unsigned long flags;
1943
1944 dynamic_irq_cleanup(irq);
1945
1946 spin_lock_irqsave(&vector_lock, flags);
1947 __clear_irq_vector(irq);
1948 spin_unlock_irqrestore(&vector_lock, flags);
1949 }
1950
1951 /*
1952 * MSI message composition
1953 */
1954 #ifdef CONFIG_PCI_MSI
1955 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1956 {
1957 struct irq_cfg *cfg = irq_cfg + irq;
1958 int err;
1959 unsigned dest;
1960 cpumask_t tmp;
1961
1962 tmp = TARGET_CPUS;
1963 err = assign_irq_vector(irq, tmp);
1964 if (!err) {
1965 cpus_and(tmp, cfg->domain, tmp);
1966 dest = cpu_mask_to_apicid(tmp);
1967
1968 msg->address_hi = MSI_ADDR_BASE_HI;
1969 msg->address_lo =
1970 MSI_ADDR_BASE_LO |
1971 ((INT_DEST_MODE == 0) ?
1972 MSI_ADDR_DEST_MODE_PHYSICAL:
1973 MSI_ADDR_DEST_MODE_LOGICAL) |
1974 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1975 MSI_ADDR_REDIRECTION_CPU:
1976 MSI_ADDR_REDIRECTION_LOWPRI) |
1977 MSI_ADDR_DEST_ID(dest);
1978
1979 msg->data =
1980 MSI_DATA_TRIGGER_EDGE |
1981 MSI_DATA_LEVEL_ASSERT |
1982 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1983 MSI_DATA_DELIVERY_FIXED:
1984 MSI_DATA_DELIVERY_LOWPRI) |
1985 MSI_DATA_VECTOR(cfg->vector);
1986 }
1987 return err;
1988 }
1989
1990 #ifdef CONFIG_SMP
1991 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1992 {
1993 struct irq_cfg *cfg = irq_cfg + irq;
1994 struct msi_msg msg;
1995 unsigned int dest;
1996 cpumask_t tmp;
1997
1998 cpus_and(tmp, mask, cpu_online_map);
1999 if (cpus_empty(tmp))
2000 return;
2001
2002 if (assign_irq_vector(irq, mask))
2003 return;
2004
2005 cpus_and(tmp, cfg->domain, mask);
2006 dest = cpu_mask_to_apicid(tmp);
2007
2008 read_msi_msg(irq, &msg);
2009
2010 msg.data &= ~MSI_DATA_VECTOR_MASK;
2011 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2012 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2013 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2014
2015 write_msi_msg(irq, &msg);
2016 irq_desc[irq].affinity = mask;
2017 }
2018 #endif /* CONFIG_SMP */
2019
2020 /*
2021 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2022 * which implement the MSI or MSI-X Capability Structure.
2023 */
2024 static struct irq_chip msi_chip = {
2025 .name = "PCI-MSI",
2026 .unmask = unmask_msi_irq,
2027 .mask = mask_msi_irq,
2028 .ack = ack_apic_edge,
2029 #ifdef CONFIG_SMP
2030 .set_affinity = set_msi_irq_affinity,
2031 #endif
2032 .retrigger = ioapic_retrigger_irq,
2033 };
2034
2035 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2036 {
2037 struct msi_msg msg;
2038 int irq, ret;
2039 irq = create_irq();
2040 if (irq < 0)
2041 return irq;
2042
2043 ret = msi_compose_msg(dev, irq, &msg);
2044 if (ret < 0) {
2045 destroy_irq(irq);
2046 return ret;
2047 }
2048
2049 set_irq_msi(irq, desc);
2050 write_msi_msg(irq, &msg);
2051
2052 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2053
2054 return 0;
2055 }
2056
2057 void arch_teardown_msi_irq(unsigned int irq)
2058 {
2059 destroy_irq(irq);
2060 }
2061
2062 #ifdef CONFIG_DMAR
2063 #ifdef CONFIG_SMP
2064 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2065 {
2066 struct irq_cfg *cfg = irq_cfg + irq;
2067 struct msi_msg msg;
2068 unsigned int dest;
2069 cpumask_t tmp;
2070
2071 cpus_and(tmp, mask, cpu_online_map);
2072 if (cpus_empty(tmp))
2073 return;
2074
2075 if (assign_irq_vector(irq, mask))
2076 return;
2077
2078 cpus_and(tmp, cfg->domain, mask);
2079 dest = cpu_mask_to_apicid(tmp);
2080
2081 dmar_msi_read(irq, &msg);
2082
2083 msg.data &= ~MSI_DATA_VECTOR_MASK;
2084 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2085 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2086 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2087
2088 dmar_msi_write(irq, &msg);
2089 irq_desc[irq].affinity = mask;
2090 }
2091 #endif /* CONFIG_SMP */
2092
2093 struct irq_chip dmar_msi_type = {
2094 .name = "DMAR_MSI",
2095 .unmask = dmar_msi_unmask,
2096 .mask = dmar_msi_mask,
2097 .ack = ack_apic_edge,
2098 #ifdef CONFIG_SMP
2099 .set_affinity = dmar_msi_set_affinity,
2100 #endif
2101 .retrigger = ioapic_retrigger_irq,
2102 };
2103
2104 int arch_setup_dmar_msi(unsigned int irq)
2105 {
2106 int ret;
2107 struct msi_msg msg;
2108
2109 ret = msi_compose_msg(NULL, irq, &msg);
2110 if (ret < 0)
2111 return ret;
2112 dmar_msi_write(irq, &msg);
2113 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2114 "edge");
2115 return 0;
2116 }
2117 #endif
2118
2119 #endif /* CONFIG_PCI_MSI */
2120 /*
2121 * Hypertransport interrupt support
2122 */
2123 #ifdef CONFIG_HT_IRQ
2124
2125 #ifdef CONFIG_SMP
2126
2127 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2128 {
2129 struct ht_irq_msg msg;
2130 fetch_ht_irq_msg(irq, &msg);
2131
2132 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2133 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2134
2135 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2136 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2137
2138 write_ht_irq_msg(irq, &msg);
2139 }
2140
2141 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2142 {
2143 struct irq_cfg *cfg = irq_cfg + irq;
2144 unsigned int dest;
2145 cpumask_t tmp;
2146
2147 cpus_and(tmp, mask, cpu_online_map);
2148 if (cpus_empty(tmp))
2149 return;
2150
2151 if (assign_irq_vector(irq, mask))
2152 return;
2153
2154 cpus_and(tmp, cfg->domain, mask);
2155 dest = cpu_mask_to_apicid(tmp);
2156
2157 target_ht_irq(irq, dest, cfg->vector);
2158 irq_desc[irq].affinity = mask;
2159 }
2160 #endif
2161
2162 static struct irq_chip ht_irq_chip = {
2163 .name = "PCI-HT",
2164 .mask = mask_ht_irq,
2165 .unmask = unmask_ht_irq,
2166 .ack = ack_apic_edge,
2167 #ifdef CONFIG_SMP
2168 .set_affinity = set_ht_irq_affinity,
2169 #endif
2170 .retrigger = ioapic_retrigger_irq,
2171 };
2172
2173 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2174 {
2175 struct irq_cfg *cfg = irq_cfg + irq;
2176 int err;
2177 cpumask_t tmp;
2178
2179 tmp = TARGET_CPUS;
2180 err = assign_irq_vector(irq, tmp);
2181 if (!err) {
2182 struct ht_irq_msg msg;
2183 unsigned dest;
2184
2185 cpus_and(tmp, cfg->domain, tmp);
2186 dest = cpu_mask_to_apicid(tmp);
2187
2188 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2189
2190 msg.address_lo =
2191 HT_IRQ_LOW_BASE |
2192 HT_IRQ_LOW_DEST_ID(dest) |
2193 HT_IRQ_LOW_VECTOR(cfg->vector) |
2194 ((INT_DEST_MODE == 0) ?
2195 HT_IRQ_LOW_DM_PHYSICAL :
2196 HT_IRQ_LOW_DM_LOGICAL) |
2197 HT_IRQ_LOW_RQEOI_EDGE |
2198 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2199 HT_IRQ_LOW_MT_FIXED :
2200 HT_IRQ_LOW_MT_ARBITRATED) |
2201 HT_IRQ_LOW_IRQ_MASKED;
2202
2203 write_ht_irq_msg(irq, &msg);
2204
2205 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2206 handle_edge_irq, "edge");
2207 }
2208 return err;
2209 }
2210 #endif /* CONFIG_HT_IRQ */
2211
2212 /* --------------------------------------------------------------------------
2213 ACPI-based IOAPIC Configuration
2214 -------------------------------------------------------------------------- */
2215
2216 #ifdef CONFIG_ACPI
2217
2218 #define IO_APIC_MAX_ID 0xFE
2219
2220 int __init io_apic_get_redir_entries (int ioapic)
2221 {
2222 union IO_APIC_reg_01 reg_01;
2223 unsigned long flags;
2224
2225 spin_lock_irqsave(&ioapic_lock, flags);
2226 reg_01.raw = io_apic_read(ioapic, 1);
2227 spin_unlock_irqrestore(&ioapic_lock, flags);
2228
2229 return reg_01.bits.entries;
2230 }
2231
2232
2233 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2234 {
2235 if (!IO_APIC_IRQ(irq)) {
2236 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2237 ioapic);
2238 return -EINVAL;
2239 }
2240
2241 /*
2242 * IRQs < 16 are already in the irq_2_pin[] map
2243 */
2244 if (irq >= 16)
2245 add_pin_to_irq(irq, ioapic, pin);
2246
2247 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2248
2249 return 0;
2250 }
2251
2252
2253 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2254 {
2255 int i;
2256
2257 if (skip_ioapic_setup)
2258 return -1;
2259
2260 for (i = 0; i < mp_irq_entries; i++)
2261 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2262 mp_irqs[i].mpc_srcbusirq == bus_irq)
2263 break;
2264 if (i >= mp_irq_entries)
2265 return -1;
2266
2267 *trigger = irq_trigger(i);
2268 *polarity = irq_polarity(i);
2269 return 0;
2270 }
2271
2272 #endif /* CONFIG_ACPI */
2273
2274 /*
2275 * This function currently is only a helper for the i386 smp boot process where
2276 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2277 * so mask in all cases should simply be TARGET_CPUS
2278 */
2279 #ifdef CONFIG_SMP
2280 void __init setup_ioapic_dest(void)
2281 {
2282 int pin, ioapic, irq, irq_entry;
2283
2284 if (skip_ioapic_setup == 1)
2285 return;
2286
2287 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2288 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2289 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2290 if (irq_entry == -1)
2291 continue;
2292 irq = pin_2_irq(irq_entry, ioapic, pin);
2293
2294 /* setup_IO_APIC_irqs could fail to get vector for some device
2295 * when you have too many devices, because at that time only boot
2296 * cpu is online.
2297 */
2298 if (!irq_cfg[irq].vector)
2299 setup_IO_APIC_irq(ioapic, pin, irq,
2300 irq_trigger(irq_entry),
2301 irq_polarity(irq_entry));
2302 else
2303 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2304 }
2305
2306 }
2307 }
2308 #endif
2309
2310 #define IOAPIC_RESOURCE_NAME_SIZE 11
2311
2312 static struct resource *ioapic_resources;
2313
2314 static struct resource * __init ioapic_setup_resources(void)
2315 {
2316 unsigned long n;
2317 struct resource *res;
2318 char *mem;
2319 int i;
2320
2321 if (nr_ioapics <= 0)
2322 return NULL;
2323
2324 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2325 n *= nr_ioapics;
2326
2327 mem = alloc_bootmem(n);
2328 res = (void *)mem;
2329
2330 if (mem != NULL) {
2331 memset(mem, 0, n);
2332 mem += sizeof(struct resource) * nr_ioapics;
2333
2334 for (i = 0; i < nr_ioapics; i++) {
2335 res[i].name = mem;
2336 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2337 sprintf(mem, "IOAPIC %u", i);
2338 mem += IOAPIC_RESOURCE_NAME_SIZE;
2339 }
2340 }
2341
2342 ioapic_resources = res;
2343
2344 return res;
2345 }
2346
2347 void __init ioapic_init_mappings(void)
2348 {
2349 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2350 struct resource *ioapic_res;
2351 int i;
2352
2353 ioapic_res = ioapic_setup_resources();
2354 for (i = 0; i < nr_ioapics; i++) {
2355 if (smp_found_config) {
2356 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2357 } else {
2358 ioapic_phys = (unsigned long)
2359 alloc_bootmem_pages(PAGE_SIZE);
2360 ioapic_phys = __pa(ioapic_phys);
2361 }
2362 set_fixmap_nocache(idx, ioapic_phys);
2363 apic_printk(APIC_VERBOSE,
2364 "mapped IOAPIC to %016lx (%016lx)\n",
2365 __fix_to_virt(idx), ioapic_phys);
2366 idx++;
2367
2368 if (ioapic_res != NULL) {
2369 ioapic_res->start = ioapic_phys;
2370 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2371 ioapic_res++;
2372 }
2373 }
2374 }
2375
2376 static int __init ioapic_insert_resources(void)
2377 {
2378 int i;
2379 struct resource *r = ioapic_resources;
2380
2381 if (!r) {
2382 printk(KERN_ERR
2383 "IO APIC resources could be not be allocated.\n");
2384 return -1;
2385 }
2386
2387 for (i = 0; i < nr_ioapics; i++) {
2388 insert_resource(&iomem_resource, r);
2389 r++;
2390 }
2391
2392 return 0;
2393 }
2394
2395 /* Insert the IO APIC resources after PCI initialization has occured to handle
2396 * IO APICS that are mapped in on a BAR in PCI space. */
2397 late_initcall(ioapic_insert_resources);
2398
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