2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
45 #include <asm/proto.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
53 #include <mach_apic.h>
58 unsigned move_cleanup_count
;
60 u8 move_in_progress
: 1;
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 struct irq_cfg irq_cfg
[NR_IRQS
] __read_mostly
= {
65 [0] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
66 [1] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
67 [2] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
68 [3] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
69 [4] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
70 [5] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
71 [6] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
72 [7] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
73 [8] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
74 [9] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
75 [10] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
76 [11] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
77 [12] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
78 [13] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
79 [14] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
80 [15] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
83 static int assign_irq_vector(int irq
, cpumask_t mask
);
85 #define __apicdebuginit __init
87 int sis_apic_bug
; /* not actually supported, dummy for compile */
89 static int no_timer_check
;
91 static int disable_timer_pin_1 __initdata
;
94 /* Where if anywhere is the i8259 connect in external int mode */
95 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
97 static DEFINE_SPINLOCK(ioapic_lock
);
98 DEFINE_SPINLOCK(vector_lock
);
101 * # of IRQ routing registers
103 int nr_ioapic_registers
[MAX_IO_APICS
];
105 /* I/O APIC entries */
106 struct mpc_config_ioapic mp_ioapics
[MAX_IO_APICS
];
109 /* MP IRQ source entries */
110 struct mpc_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
112 /* # of MP IRQ source entries */
116 * Rough estimation of how many shared IRQs there are, can
117 * be changed anytime.
119 #define MAX_PLUS_SHARED_IRQS NR_IRQS
120 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
123 * This is performance-critical, we want to do it O(1)
125 * the indexing order of this array favors 1:1 mappings
126 * between pins and IRQs.
129 static struct irq_pin_list
{
130 short apic
, pin
, next
;
131 } irq_2_pin
[PIN_MAP_SIZE
];
135 unsigned int unused
[3];
139 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
141 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
142 + (mp_ioapics
[idx
].mpc_apicaddr
& ~PAGE_MASK
);
145 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
147 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
148 writel(reg
, &io_apic
->index
);
149 return readl(&io_apic
->data
);
152 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
154 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
155 writel(reg
, &io_apic
->index
);
156 writel(value
, &io_apic
->data
);
160 * Re-write a value: to be used for read-modify-write
161 * cycles where the read already set up the index register.
163 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
165 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
166 writel(value
, &io_apic
->data
);
169 static bool io_apic_level_ack_pending(unsigned int irq
)
171 struct irq_pin_list
*entry
;
174 spin_lock_irqsave(&ioapic_lock
, flags
);
175 entry
= irq_2_pin
+ irq
;
183 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
184 /* Is the remote IRR bit set? */
185 if ((reg
>> 14) & 1) {
186 spin_unlock_irqrestore(&ioapic_lock
, flags
);
191 entry
= irq_2_pin
+ entry
->next
;
193 spin_unlock_irqrestore(&ioapic_lock
, flags
);
199 * Synchronize the IO-APIC and the CPU by doing
200 * a dummy read from the IO-APIC
202 static inline void io_apic_sync(unsigned int apic
)
204 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
205 readl(&io_apic
->data
);
208 #define __DO_ACTION(R, ACTION, FINAL) \
212 struct irq_pin_list *entry = irq_2_pin + irq; \
214 BUG_ON(irq >= NR_IRQS); \
220 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
222 io_apic_modify(entry->apic, reg); \
226 entry = irq_2_pin + entry->next; \
231 struct { u32 w1
, w2
; };
232 struct IO_APIC_route_entry entry
;
235 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
237 union entry_union eu
;
239 spin_lock_irqsave(&ioapic_lock
, flags
);
240 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
241 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
242 spin_unlock_irqrestore(&ioapic_lock
, flags
);
247 * When we write a new IO APIC routing entry, we need to write the high
248 * word first! If the mask bit in the low word is clear, we will enable
249 * the interrupt, and we need to make sure the entry is fully populated
250 * before that happens.
253 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
255 union entry_union eu
;
257 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
258 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
261 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
264 spin_lock_irqsave(&ioapic_lock
, flags
);
265 __ioapic_write_entry(apic
, pin
, e
);
266 spin_unlock_irqrestore(&ioapic_lock
, flags
);
270 * When we mask an IO APIC routing entry, we need to write the low
271 * word first, in order to set the mask bit before we change the
274 static void ioapic_mask_entry(int apic
, int pin
)
277 union entry_union eu
= { .entry
.mask
= 1 };
279 spin_lock_irqsave(&ioapic_lock
, flags
);
280 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
281 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
282 spin_unlock_irqrestore(&ioapic_lock
, flags
);
286 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
289 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
291 BUG_ON(irq
>= NR_IRQS
);
298 io_apic_write(apic
, 0x11 + pin
*2, dest
);
299 reg
= io_apic_read(apic
, 0x10 + pin
*2);
302 io_apic_modify(apic
, reg
);
305 entry
= irq_2_pin
+ entry
->next
;
309 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
311 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
316 cpus_and(tmp
, mask
, cpu_online_map
);
320 if (assign_irq_vector(irq
, mask
))
323 cpus_and(tmp
, cfg
->domain
, mask
);
324 dest
= cpu_mask_to_apicid(tmp
);
327 * Only the high 8 bits are valid.
329 dest
= SET_APIC_LOGICAL_ID(dest
);
331 spin_lock_irqsave(&ioapic_lock
, flags
);
332 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
333 irq_desc
[irq
].affinity
= mask
;
334 spin_unlock_irqrestore(&ioapic_lock
, flags
);
339 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
340 * shared ISA-space IRQs, so we have to support them. We are super
341 * fast in the common case, and fast for shared ISA-space IRQs.
343 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
345 static int first_free_entry
= NR_IRQS
;
346 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
348 BUG_ON(irq
>= NR_IRQS
);
350 entry
= irq_2_pin
+ entry
->next
;
352 if (entry
->pin
!= -1) {
353 entry
->next
= first_free_entry
;
354 entry
= irq_2_pin
+ entry
->next
;
355 if (++first_free_entry
>= PIN_MAP_SIZE
)
356 panic("io_apic.c: ran out of irq_2_pin entries!");
363 #define DO_ACTION(name,R,ACTION, FINAL) \
365 static void name##_IO_APIC_irq (unsigned int irq) \
366 __DO_ACTION(R, ACTION, FINAL)
368 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
) )
370 DO_ACTION( __unmask
, 0, &= 0xfffeffff, )
373 static void mask_IO_APIC_irq (unsigned int irq
)
377 spin_lock_irqsave(&ioapic_lock
, flags
);
378 __mask_IO_APIC_irq(irq
);
379 spin_unlock_irqrestore(&ioapic_lock
, flags
);
382 static void unmask_IO_APIC_irq (unsigned int irq
)
386 spin_lock_irqsave(&ioapic_lock
, flags
);
387 __unmask_IO_APIC_irq(irq
);
388 spin_unlock_irqrestore(&ioapic_lock
, flags
);
391 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
393 struct IO_APIC_route_entry entry
;
395 /* Check delivery_mode to be sure we're not clearing an SMI pin */
396 entry
= ioapic_read_entry(apic
, pin
);
397 if (entry
.delivery_mode
== dest_SMI
)
400 * Disable it in the IO-APIC irq-routing table:
402 ioapic_mask_entry(apic
, pin
);
405 static void clear_IO_APIC (void)
409 for (apic
= 0; apic
< nr_ioapics
; apic
++)
410 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
411 clear_IO_APIC_pin(apic
, pin
);
414 int skip_ioapic_setup
;
417 static int __init
parse_noapic(char *str
)
419 disable_ioapic_setup();
422 early_param("noapic", parse_noapic
);
424 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
425 static int __init
disable_timer_pin_setup(char *arg
)
427 disable_timer_pin_1
= 1;
430 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
434 * Find the IRQ entry number of a certain pin.
436 static int find_irq_entry(int apic
, int pin
, int type
)
440 for (i
= 0; i
< mp_irq_entries
; i
++)
441 if (mp_irqs
[i
].mpc_irqtype
== type
&&
442 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
443 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
444 mp_irqs
[i
].mpc_dstirq
== pin
)
451 * Find the pin to which IRQ[irq] (ISA) is connected
453 static int __init
find_isa_irq_pin(int irq
, int type
)
457 for (i
= 0; i
< mp_irq_entries
; i
++) {
458 int lbus
= mp_irqs
[i
].mpc_srcbus
;
460 if (test_bit(lbus
, mp_bus_not_pci
) &&
461 (mp_irqs
[i
].mpc_irqtype
== type
) &&
462 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
464 return mp_irqs
[i
].mpc_dstirq
;
469 static int __init
find_isa_irq_apic(int irq
, int type
)
473 for (i
= 0; i
< mp_irq_entries
; i
++) {
474 int lbus
= mp_irqs
[i
].mpc_srcbus
;
476 if (test_bit(lbus
, mp_bus_not_pci
) &&
477 (mp_irqs
[i
].mpc_irqtype
== type
) &&
478 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
481 if (i
< mp_irq_entries
) {
483 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
484 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
493 * Find a specific PCI IRQ entry.
494 * Not an __init, possibly needed by modules
496 static int pin_2_irq(int idx
, int apic
, int pin
);
498 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
500 int apic
, i
, best_guess
= -1;
502 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
504 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
505 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
508 for (i
= 0; i
< mp_irq_entries
; i
++) {
509 int lbus
= mp_irqs
[i
].mpc_srcbus
;
511 for (apic
= 0; apic
< nr_ioapics
; apic
++)
512 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
513 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
516 if (!test_bit(lbus
, mp_bus_not_pci
) &&
517 !mp_irqs
[i
].mpc_irqtype
&&
519 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
520 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
522 if (!(apic
|| IO_APIC_IRQ(irq
)))
525 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
528 * Use the first all-but-pin matching entry as a
529 * best-guess fuzzy result for broken mptables.
535 BUG_ON(best_guess
>= NR_IRQS
);
539 /* ISA interrupts are always polarity zero edge triggered,
540 * when listed as conforming in the MP table. */
542 #define default_ISA_trigger(idx) (0)
543 #define default_ISA_polarity(idx) (0)
545 /* PCI interrupts are always polarity one level triggered,
546 * when listed as conforming in the MP table. */
548 #define default_PCI_trigger(idx) (1)
549 #define default_PCI_polarity(idx) (1)
551 static int MPBIOS_polarity(int idx
)
553 int bus
= mp_irqs
[idx
].mpc_srcbus
;
557 * Determine IRQ line polarity (high active or low active):
559 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
561 case 0: /* conforms, ie. bus-type dependent polarity */
562 if (test_bit(bus
, mp_bus_not_pci
))
563 polarity
= default_ISA_polarity(idx
);
565 polarity
= default_PCI_polarity(idx
);
567 case 1: /* high active */
572 case 2: /* reserved */
574 printk(KERN_WARNING
"broken BIOS!!\n");
578 case 3: /* low active */
583 default: /* invalid */
585 printk(KERN_WARNING
"broken BIOS!!\n");
593 static int MPBIOS_trigger(int idx
)
595 int bus
= mp_irqs
[idx
].mpc_srcbus
;
599 * Determine IRQ trigger mode (edge or level sensitive):
601 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
603 case 0: /* conforms, ie. bus-type dependent */
604 if (test_bit(bus
, mp_bus_not_pci
))
605 trigger
= default_ISA_trigger(idx
);
607 trigger
= default_PCI_trigger(idx
);
614 case 2: /* reserved */
616 printk(KERN_WARNING
"broken BIOS!!\n");
625 default: /* invalid */
627 printk(KERN_WARNING
"broken BIOS!!\n");
635 static inline int irq_polarity(int idx
)
637 return MPBIOS_polarity(idx
);
640 static inline int irq_trigger(int idx
)
642 return MPBIOS_trigger(idx
);
645 static int pin_2_irq(int idx
, int apic
, int pin
)
648 int bus
= mp_irqs
[idx
].mpc_srcbus
;
651 * Debugging check, we are in big trouble if this message pops up!
653 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
654 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
656 if (test_bit(bus
, mp_bus_not_pci
)) {
657 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
660 * PCI IRQs are mapped in order
664 irq
+= nr_ioapic_registers
[i
++];
667 BUG_ON(irq
>= NR_IRQS
);
671 static int __assign_irq_vector(int irq
, cpumask_t mask
)
674 * NOTE! The local APIC isn't very good at handling
675 * multiple interrupts at the same interrupt level.
676 * As the interrupt level is determined by taking the
677 * vector number and shifting that right by 4, we
678 * want to spread these out a bit so that they don't
679 * all fall in the same interrupt level.
681 * Also, we've got to be careful not to trash gate
682 * 0x80, because int 0x80 is hm, kind of importantish. ;)
684 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
685 unsigned int old_vector
;
689 BUG_ON((unsigned)irq
>= NR_IRQS
);
692 /* Only try and allocate irqs on cpus that are present */
693 cpus_and(mask
, mask
, cpu_online_map
);
695 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
698 old_vector
= cfg
->vector
;
701 cpus_and(tmp
, cfg
->domain
, mask
);
702 if (!cpus_empty(tmp
))
706 for_each_cpu_mask(cpu
, mask
) {
707 cpumask_t domain
, new_mask
;
711 domain
= vector_allocation_domain(cpu
);
712 cpus_and(new_mask
, domain
, cpu_online_map
);
714 vector
= current_vector
;
715 offset
= current_offset
;
718 if (vector
>= FIRST_SYSTEM_VECTOR
) {
719 /* If we run out of vectors on large boxen, must share them. */
720 offset
= (offset
+ 1) % 8;
721 vector
= FIRST_DEVICE_VECTOR
+ offset
;
723 if (unlikely(current_vector
== vector
))
725 if (vector
== IA32_SYSCALL_VECTOR
)
727 for_each_cpu_mask(new_cpu
, new_mask
)
728 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
731 current_vector
= vector
;
732 current_offset
= offset
;
734 cfg
->move_in_progress
= 1;
735 cfg
->old_domain
= cfg
->domain
;
737 for_each_cpu_mask(new_cpu
, new_mask
)
738 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
739 cfg
->vector
= vector
;
740 cfg
->domain
= domain
;
746 static int assign_irq_vector(int irq
, cpumask_t mask
)
751 spin_lock_irqsave(&vector_lock
, flags
);
752 err
= __assign_irq_vector(irq
, mask
);
753 spin_unlock_irqrestore(&vector_lock
, flags
);
757 static void __clear_irq_vector(int irq
)
763 BUG_ON((unsigned)irq
>= NR_IRQS
);
765 BUG_ON(!cfg
->vector
);
767 vector
= cfg
->vector
;
768 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
769 for_each_cpu_mask(cpu
, mask
)
770 per_cpu(vector_irq
, cpu
)[vector
] = -1;
773 cpus_clear(cfg
->domain
);
776 void __setup_vector_irq(int cpu
)
778 /* Initialize vector_irq on a new cpu */
779 /* This function must be called with vector_lock held */
782 /* Mark the inuse vectors */
783 for (irq
= 0; irq
< NR_IRQS
; ++irq
) {
784 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
786 vector
= irq_cfg
[irq
].vector
;
787 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
789 /* Mark the free vectors */
790 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
791 irq
= per_cpu(vector_irq
, cpu
)[vector
];
794 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
795 per_cpu(vector_irq
, cpu
)[vector
] = -1;
800 static struct irq_chip ioapic_chip
;
802 static void ioapic_register_intr(int irq
, unsigned long trigger
)
805 irq_desc
[irq
].status
|= IRQ_LEVEL
;
806 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
807 handle_fasteoi_irq
, "fasteoi");
809 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
810 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
811 handle_edge_irq
, "edge");
815 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
816 int trigger
, int polarity
)
818 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
819 struct IO_APIC_route_entry entry
;
822 if (!IO_APIC_IRQ(irq
))
826 if (assign_irq_vector(irq
, mask
))
829 cpus_and(mask
, cfg
->domain
, mask
);
831 apic_printk(APIC_VERBOSE
,KERN_DEBUG
832 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
833 "IRQ %d Mode:%i Active:%i)\n",
834 apic
, mp_ioapics
[apic
].mpc_apicid
, pin
, cfg
->vector
,
835 irq
, trigger
, polarity
);
838 * add it to the IO-APIC irq-routing table:
840 memset(&entry
,0,sizeof(entry
));
842 entry
.delivery_mode
= INT_DELIVERY_MODE
;
843 entry
.dest_mode
= INT_DEST_MODE
;
844 entry
.dest
= cpu_mask_to_apicid(mask
);
845 entry
.mask
= 0; /* enable IRQ */
846 entry
.trigger
= trigger
;
847 entry
.polarity
= polarity
;
848 entry
.vector
= cfg
->vector
;
850 /* Mask level triggered irqs.
851 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
856 ioapic_register_intr(irq
, trigger
);
858 disable_8259A_irq(irq
);
860 ioapic_write_entry(apic
, pin
, entry
);
863 static void __init
setup_IO_APIC_irqs(void)
865 int apic
, pin
, idx
, irq
, first_notcon
= 1;
867 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
869 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
870 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
872 idx
= find_irq_entry(apic
,pin
,mp_INT
);
875 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
878 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
882 apic_printk(APIC_VERBOSE
, " not connected.\n");
886 irq
= pin_2_irq(idx
, apic
, pin
);
887 add_pin_to_irq(irq
, apic
, pin
);
889 setup_IO_APIC_irq(apic
, pin
, irq
,
890 irq_trigger(idx
), irq_polarity(idx
));
895 apic_printk(APIC_VERBOSE
, " not connected.\n");
899 * Set up the 8259A-master output pin as broadcast to all
902 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
904 struct IO_APIC_route_entry entry
;
906 memset(&entry
, 0, sizeof(entry
));
908 disable_8259A_irq(0);
911 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
914 * We use logical delivery to get the timer IRQ
917 entry
.dest_mode
= INT_DEST_MODE
;
918 entry
.mask
= 0; /* unmask IRQ now */
919 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
920 entry
.delivery_mode
= INT_DELIVERY_MODE
;
923 entry
.vector
= vector
;
926 * The timer IRQ doesn't have to know that behind the
927 * scene we have a 8259A-master in AEOI mode ...
929 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
932 * Add it to the IO-APIC irq-routing table:
934 ioapic_write_entry(apic
, pin
, entry
);
939 void __apicdebuginit
print_IO_APIC(void)
942 union IO_APIC_reg_00 reg_00
;
943 union IO_APIC_reg_01 reg_01
;
944 union IO_APIC_reg_02 reg_02
;
947 if (apic_verbosity
== APIC_QUIET
)
950 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
951 for (i
= 0; i
< nr_ioapics
; i
++)
952 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
953 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
956 * We are a bit conservative about what we expect. We have to
957 * know about every hardware change ASAP.
959 printk(KERN_INFO
"testing the IO APIC.......................\n");
961 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
963 spin_lock_irqsave(&ioapic_lock
, flags
);
964 reg_00
.raw
= io_apic_read(apic
, 0);
965 reg_01
.raw
= io_apic_read(apic
, 1);
966 if (reg_01
.bits
.version
>= 0x10)
967 reg_02
.raw
= io_apic_read(apic
, 2);
968 spin_unlock_irqrestore(&ioapic_lock
, flags
);
971 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
972 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
973 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
975 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
976 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
978 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
979 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
981 if (reg_01
.bits
.version
>= 0x10) {
982 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
983 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
986 printk(KERN_DEBUG
".... IRQ redirection table:\n");
988 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
989 " Stat Dmod Deli Vect: \n");
991 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
992 struct IO_APIC_route_entry entry
;
994 entry
= ioapic_read_entry(apic
, i
);
996 printk(KERN_DEBUG
" %02x %03X ",
1001 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1006 entry
.delivery_status
,
1008 entry
.delivery_mode
,
1013 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1014 for (i
= 0; i
< NR_IRQS
; i
++) {
1015 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1018 printk(KERN_DEBUG
"IRQ%d ", i
);
1020 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1023 entry
= irq_2_pin
+ entry
->next
;
1028 printk(KERN_INFO
".................................... done.\n");
1035 static __apicdebuginit
void print_APIC_bitfield (int base
)
1040 if (apic_verbosity
== APIC_QUIET
)
1043 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1044 for (i
= 0; i
< 8; i
++) {
1045 v
= apic_read(base
+ i
*0x10);
1046 for (j
= 0; j
< 32; j
++) {
1056 void __apicdebuginit
print_local_APIC(void * dummy
)
1058 unsigned int v
, ver
, maxlvt
;
1060 if (apic_verbosity
== APIC_QUIET
)
1063 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1064 smp_processor_id(), hard_smp_processor_id());
1065 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(read_apic_id()));
1066 v
= apic_read(APIC_LVR
);
1067 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1068 ver
= GET_APIC_VERSION(v
);
1069 maxlvt
= lapic_get_maxlvt();
1071 v
= apic_read(APIC_TASKPRI
);
1072 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1074 v
= apic_read(APIC_ARBPRI
);
1075 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1076 v
& APIC_ARBPRI_MASK
);
1077 v
= apic_read(APIC_PROCPRI
);
1078 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1080 v
= apic_read(APIC_EOI
);
1081 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1082 v
= apic_read(APIC_RRR
);
1083 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1084 v
= apic_read(APIC_LDR
);
1085 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1086 v
= apic_read(APIC_DFR
);
1087 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1088 v
= apic_read(APIC_SPIV
);
1089 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1091 printk(KERN_DEBUG
"... APIC ISR field:\n");
1092 print_APIC_bitfield(APIC_ISR
);
1093 printk(KERN_DEBUG
"... APIC TMR field:\n");
1094 print_APIC_bitfield(APIC_TMR
);
1095 printk(KERN_DEBUG
"... APIC IRR field:\n");
1096 print_APIC_bitfield(APIC_IRR
);
1098 v
= apic_read(APIC_ESR
);
1099 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1101 v
= apic_read(APIC_ICR
);
1102 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1103 v
= apic_read(APIC_ICR2
);
1104 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1106 v
= apic_read(APIC_LVTT
);
1107 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1109 if (maxlvt
> 3) { /* PC is LVT#4. */
1110 v
= apic_read(APIC_LVTPC
);
1111 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1113 v
= apic_read(APIC_LVT0
);
1114 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1115 v
= apic_read(APIC_LVT1
);
1116 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1118 if (maxlvt
> 2) { /* ERR is LVT#3. */
1119 v
= apic_read(APIC_LVTERR
);
1120 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1123 v
= apic_read(APIC_TMICT
);
1124 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1125 v
= apic_read(APIC_TMCCT
);
1126 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1127 v
= apic_read(APIC_TDCR
);
1128 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1132 void print_all_local_APICs (void)
1134 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1137 void __apicdebuginit
print_PIC(void)
1140 unsigned long flags
;
1142 if (apic_verbosity
== APIC_QUIET
)
1145 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1147 spin_lock_irqsave(&i8259A_lock
, flags
);
1149 v
= inb(0xa1) << 8 | inb(0x21);
1150 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1152 v
= inb(0xa0) << 8 | inb(0x20);
1153 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1157 v
= inb(0xa0) << 8 | inb(0x20);
1161 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1163 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1165 v
= inb(0x4d1) << 8 | inb(0x4d0);
1166 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1171 void __init
enable_IO_APIC(void)
1173 union IO_APIC_reg_01 reg_01
;
1174 int i8259_apic
, i8259_pin
;
1176 unsigned long flags
;
1178 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1179 irq_2_pin
[i
].pin
= -1;
1180 irq_2_pin
[i
].next
= 0;
1184 * The number of IO-APIC IRQ registers (== #pins):
1186 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1187 spin_lock_irqsave(&ioapic_lock
, flags
);
1188 reg_01
.raw
= io_apic_read(apic
, 1);
1189 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1190 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1192 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1194 /* See if any of the pins is in ExtINT mode */
1195 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1196 struct IO_APIC_route_entry entry
;
1197 entry
= ioapic_read_entry(apic
, pin
);
1199 /* If the interrupt line is enabled and in ExtInt mode
1200 * I have found the pin where the i8259 is connected.
1202 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1203 ioapic_i8259
.apic
= apic
;
1204 ioapic_i8259
.pin
= pin
;
1210 /* Look to see what if the MP table has reported the ExtINT */
1211 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1212 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1213 /* Trust the MP table if nothing is setup in the hardware */
1214 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1215 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1216 ioapic_i8259
.pin
= i8259_pin
;
1217 ioapic_i8259
.apic
= i8259_apic
;
1219 /* Complain if the MP table and the hardware disagree */
1220 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1221 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1223 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1227 * Do not trust the IO-APIC being empty at bootup
1233 * Not an __init, needed by the reboot code
1235 void disable_IO_APIC(void)
1238 * Clear the IO-APIC before rebooting:
1243 * If the i8259 is routed through an IOAPIC
1244 * Put that IOAPIC in virtual wire mode
1245 * so legacy interrupts can be delivered.
1247 if (ioapic_i8259
.pin
!= -1) {
1248 struct IO_APIC_route_entry entry
;
1250 memset(&entry
, 0, sizeof(entry
));
1251 entry
.mask
= 0; /* Enabled */
1252 entry
.trigger
= 0; /* Edge */
1254 entry
.polarity
= 0; /* High */
1255 entry
.delivery_status
= 0;
1256 entry
.dest_mode
= 0; /* Physical */
1257 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1259 entry
.dest
= GET_APIC_ID(read_apic_id());
1262 * Add it to the IO-APIC irq-routing table:
1264 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1267 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1271 * There is a nasty bug in some older SMP boards, their mptable lies
1272 * about the timer IRQ. We do the following to work around the situation:
1274 * - timer IRQ defaults to IO-APIC IRQ
1275 * - if this function detects that timer IRQs are defunct, then we fall
1276 * back to ISA timer IRQs
1278 static int __init
timer_irq_works(void)
1280 unsigned long t1
= jiffies
;
1281 unsigned long flags
;
1283 local_save_flags(flags
);
1285 /* Let ten ticks pass... */
1286 mdelay((10 * 1000) / HZ
);
1287 local_irq_restore(flags
);
1290 * Expect a few ticks at least, to be sure some possible
1291 * glue logic does not lock up after one or two first
1292 * ticks in a non-ExtINT mode. Also the local APIC
1293 * might have cached one ExtINT interrupt. Finally, at
1294 * least one tick may be lost due to delays.
1298 if (time_after(jiffies
, t1
+ 4))
1304 * In the SMP+IOAPIC case it might happen that there are an unspecified
1305 * number of pending IRQ events unhandled. These cases are very rare,
1306 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1307 * better to do it this way as thus we do not have to be aware of
1308 * 'pending' interrupts in the IRQ path, except at this point.
1311 * Edge triggered needs to resend any interrupt
1312 * that was delayed but this is now handled in the device
1317 * Starting up a edge-triggered IO-APIC interrupt is
1318 * nasty - we need to make sure that we get the edge.
1319 * If it is already asserted for some reason, we need
1320 * return 1 to indicate that is was pending.
1322 * This is not complete - we should be able to fake
1323 * an edge even if it isn't on the 8259A...
1326 static unsigned int startup_ioapic_irq(unsigned int irq
)
1328 int was_pending
= 0;
1329 unsigned long flags
;
1331 spin_lock_irqsave(&ioapic_lock
, flags
);
1333 disable_8259A_irq(irq
);
1334 if (i8259A_irq_pending(irq
))
1337 __unmask_IO_APIC_irq(irq
);
1338 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1343 static int ioapic_retrigger_irq(unsigned int irq
)
1345 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
1347 unsigned long flags
;
1349 spin_lock_irqsave(&vector_lock
, flags
);
1350 mask
= cpumask_of_cpu(first_cpu(cfg
->domain
));
1351 send_IPI_mask(mask
, cfg
->vector
);
1352 spin_unlock_irqrestore(&vector_lock
, flags
);
1358 * Level and edge triggered IO-APIC interrupts need different handling,
1359 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1360 * handled with the level-triggered descriptor, but that one has slightly
1361 * more overhead. Level-triggered interrupts cannot be handled with the
1362 * edge-triggered handler, without risking IRQ storms and other ugly
1367 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1369 unsigned vector
, me
;
1374 me
= smp_processor_id();
1375 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1377 struct irq_desc
*desc
;
1378 struct irq_cfg
*cfg
;
1379 irq
= __get_cpu_var(vector_irq
)[vector
];
1383 desc
= irq_desc
+ irq
;
1384 cfg
= irq_cfg
+ irq
;
1385 spin_lock(&desc
->lock
);
1386 if (!cfg
->move_cleanup_count
)
1389 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1392 __get_cpu_var(vector_irq
)[vector
] = -1;
1393 cfg
->move_cleanup_count
--;
1395 spin_unlock(&desc
->lock
);
1401 static void irq_complete_move(unsigned int irq
)
1403 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1404 unsigned vector
, me
;
1406 if (likely(!cfg
->move_in_progress
))
1409 vector
= ~get_irq_regs()->orig_ax
;
1410 me
= smp_processor_id();
1411 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1412 cpumask_t cleanup_mask
;
1414 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1415 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1416 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1417 cfg
->move_in_progress
= 0;
1421 static inline void irq_complete_move(unsigned int irq
) {}
1424 static void ack_apic_edge(unsigned int irq
)
1426 irq_complete_move(irq
);
1427 move_native_irq(irq
);
1431 static void ack_apic_level(unsigned int irq
)
1433 int do_unmask_irq
= 0;
1435 irq_complete_move(irq
);
1436 #ifdef CONFIG_GENERIC_PENDING_IRQ
1437 /* If we are moving the irq we need to mask it */
1438 if (unlikely(irq_desc
[irq
].status
& IRQ_MOVE_PENDING
)) {
1440 mask_IO_APIC_irq(irq
);
1445 * We must acknowledge the irq before we move it or the acknowledge will
1446 * not propagate properly.
1450 /* Now we can move and renable the irq */
1451 if (unlikely(do_unmask_irq
)) {
1452 /* Only migrate the irq if the ack has been received.
1454 * On rare occasions the broadcast level triggered ack gets
1455 * delayed going to ioapics, and if we reprogram the
1456 * vector while Remote IRR is still set the irq will never
1459 * To prevent this scenario we read the Remote IRR bit
1460 * of the ioapic. This has two effects.
1461 * - On any sane system the read of the ioapic will
1462 * flush writes (and acks) going to the ioapic from
1464 * - We get to see if the ACK has actually been delivered.
1466 * Based on failed experiments of reprogramming the
1467 * ioapic entry from outside of irq context starting
1468 * with masking the ioapic entry and then polling until
1469 * Remote IRR was clear before reprogramming the
1470 * ioapic I don't trust the Remote IRR bit to be
1471 * completey accurate.
1473 * However there appears to be no other way to plug
1474 * this race, so if the Remote IRR bit is not
1475 * accurate and is causing problems then it is a hardware bug
1476 * and you can go talk to the chipset vendor about it.
1478 if (!io_apic_level_ack_pending(irq
))
1479 move_masked_irq(irq
);
1480 unmask_IO_APIC_irq(irq
);
1484 static struct irq_chip ioapic_chip __read_mostly
= {
1486 .startup
= startup_ioapic_irq
,
1487 .mask
= mask_IO_APIC_irq
,
1488 .unmask
= unmask_IO_APIC_irq
,
1489 .ack
= ack_apic_edge
,
1490 .eoi
= ack_apic_level
,
1492 .set_affinity
= set_ioapic_affinity_irq
,
1494 .retrigger
= ioapic_retrigger_irq
,
1497 static inline void init_IO_APIC_traps(void)
1502 * NOTE! The local APIC isn't very good at handling
1503 * multiple interrupts at the same interrupt level.
1504 * As the interrupt level is determined by taking the
1505 * vector number and shifting that right by 4, we
1506 * want to spread these out a bit so that they don't
1507 * all fall in the same interrupt level.
1509 * Also, we've got to be careful not to trash gate
1510 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1512 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1513 if (IO_APIC_IRQ(irq
) && !irq_cfg
[irq
].vector
) {
1515 * Hmm.. We don't have an entry for this,
1516 * so default to an old-fashioned 8259
1517 * interrupt if we can..
1520 make_8259A_irq(irq
);
1522 /* Strange. Oh, well.. */
1523 irq_desc
[irq
].chip
= &no_irq_chip
;
1528 static void enable_lapic_irq (unsigned int irq
)
1532 v
= apic_read(APIC_LVT0
);
1533 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1536 static void disable_lapic_irq (unsigned int irq
)
1540 v
= apic_read(APIC_LVT0
);
1541 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1544 static void ack_lapic_irq (unsigned int irq
)
1549 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1551 static struct hw_interrupt_type lapic_irq_type __read_mostly
= {
1552 .name
= "local-APIC",
1553 .typename
= "local-APIC-edge",
1554 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
1555 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
1556 .enable
= enable_lapic_irq
,
1557 .disable
= disable_lapic_irq
,
1558 .ack
= ack_lapic_irq
,
1559 .end
= end_lapic_irq
,
1562 static void __init
setup_nmi(void)
1565 * Dirty trick to enable the NMI watchdog ...
1566 * We put the 8259A master into AEOI mode and
1567 * unmask on all local APICs LVT0 as NMI.
1569 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1570 * is from Maciej W. Rozycki - so we do not have to EOI from
1571 * the NMI handler or the timer interrupt.
1573 printk(KERN_INFO
"activating NMI Watchdog ...");
1575 enable_NMI_through_LVT0();
1581 * This looks a bit hackish but it's about the only one way of sending
1582 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1583 * not support the ExtINT mode, unfortunately. We need to send these
1584 * cycles as some i82489DX-based boards have glue logic that keeps the
1585 * 8259A interrupt line asserted until INTA. --macro
1587 static inline void __init
unlock_ExtINT_logic(void)
1590 struct IO_APIC_route_entry entry0
, entry1
;
1591 unsigned char save_control
, save_freq_select
;
1593 pin
= find_isa_irq_pin(8, mp_INT
);
1594 apic
= find_isa_irq_apic(8, mp_INT
);
1598 entry0
= ioapic_read_entry(apic
, pin
);
1600 clear_IO_APIC_pin(apic
, pin
);
1602 memset(&entry1
, 0, sizeof(entry1
));
1604 entry1
.dest_mode
= 0; /* physical delivery */
1605 entry1
.mask
= 0; /* unmask IRQ now */
1606 entry1
.dest
= hard_smp_processor_id();
1607 entry1
.delivery_mode
= dest_ExtINT
;
1608 entry1
.polarity
= entry0
.polarity
;
1612 ioapic_write_entry(apic
, pin
, entry1
);
1614 save_control
= CMOS_READ(RTC_CONTROL
);
1615 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1616 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1618 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1623 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1627 CMOS_WRITE(save_control
, RTC_CONTROL
);
1628 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1629 clear_IO_APIC_pin(apic
, pin
);
1631 ioapic_write_entry(apic
, pin
, entry0
);
1635 * This code may look a bit paranoid, but it's supposed to cooperate with
1636 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1637 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1638 * fanatically on his truly buggy board.
1640 * FIXME: really need to revamp this for modern platforms only.
1642 static inline void __init
check_timer(void)
1644 struct irq_cfg
*cfg
= irq_cfg
+ 0;
1645 int apic1
, pin1
, apic2
, pin2
;
1646 unsigned long flags
;
1648 local_irq_save(flags
);
1651 * get/set the timer IRQ vector:
1653 disable_8259A_irq(0);
1654 assign_irq_vector(0, TARGET_CPUS
);
1657 * As IRQ0 is to be enabled in the 8259A, the virtual
1658 * wire has to be disabled in the local APIC.
1660 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1663 pin1
= find_isa_irq_pin(0, mp_INT
);
1664 apic1
= find_isa_irq_apic(0, mp_INT
);
1665 pin2
= ioapic_i8259
.pin
;
1666 apic2
= ioapic_i8259
.apic
;
1668 apic_printk(APIC_VERBOSE
,KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1669 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
1673 * Ok, does IRQ0 through the IOAPIC work?
1675 unmask_IO_APIC_irq(0);
1676 if (!no_timer_check
&& timer_irq_works()) {
1677 nmi_watchdog_default();
1678 if (nmi_watchdog
== NMI_IO_APIC
) {
1680 enable_8259A_irq(0);
1682 if (disable_timer_pin_1
> 0)
1683 clear_IO_APIC_pin(0, pin1
);
1686 clear_IO_APIC_pin(apic1
, pin1
);
1687 apic_printk(APIC_QUIET
,KERN_ERR
"..MP-BIOS bug: 8254 timer not "
1688 "connected to IO-APIC\n");
1691 apic_printk(APIC_VERBOSE
,KERN_INFO
"...trying to set up timer (IRQ0) "
1692 "through the 8259A ... ");
1694 apic_printk(APIC_VERBOSE
,"\n..... (found apic %d pin %d) ...",
1697 * legacy devices should be connected to IO APIC #0
1699 setup_ExtINT_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
1700 enable_8259A_irq(0);
1701 if (timer_irq_works()) {
1702 apic_printk(APIC_VERBOSE
," works.\n");
1703 nmi_watchdog_default();
1704 if (nmi_watchdog
== NMI_IO_APIC
) {
1710 * Cleanup, just in case ...
1712 disable_8259A_irq(0);
1713 clear_IO_APIC_pin(apic2
, pin2
);
1715 apic_printk(APIC_VERBOSE
," failed.\n");
1717 if (nmi_watchdog
== NMI_IO_APIC
) {
1718 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1722 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
1724 irq_desc
[0].chip
= &lapic_irq_type
;
1725 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
1726 enable_8259A_irq(0);
1728 if (timer_irq_works()) {
1729 apic_printk(APIC_VERBOSE
," works.\n");
1732 disable_8259A_irq(0);
1733 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
1734 apic_printk(APIC_VERBOSE
," failed.\n");
1736 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
1740 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1742 unlock_ExtINT_logic();
1744 if (timer_irq_works()) {
1745 apic_printk(APIC_VERBOSE
," works.\n");
1748 apic_printk(APIC_VERBOSE
," failed :(.\n");
1749 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1751 local_irq_restore(flags
);
1754 static int __init
notimercheck(char *s
)
1759 __setup("no_timer_check", notimercheck
);
1763 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1764 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1765 * Linux doesn't really care, as it's not actually used
1766 * for any interrupt handling anyway.
1768 #define PIC_IRQS (1<<2)
1770 void __init
setup_IO_APIC(void)
1774 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1778 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
1780 io_apic_irqs
= ~PIC_IRQS
;
1782 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
1785 setup_IO_APIC_irqs();
1786 init_IO_APIC_traps();
1792 struct sysfs_ioapic_data
{
1793 struct sys_device dev
;
1794 struct IO_APIC_route_entry entry
[0];
1796 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
1798 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1800 struct IO_APIC_route_entry
*entry
;
1801 struct sysfs_ioapic_data
*data
;
1804 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
1805 entry
= data
->entry
;
1806 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
1807 *entry
= ioapic_read_entry(dev
->id
, i
);
1812 static int ioapic_resume(struct sys_device
*dev
)
1814 struct IO_APIC_route_entry
*entry
;
1815 struct sysfs_ioapic_data
*data
;
1816 unsigned long flags
;
1817 union IO_APIC_reg_00 reg_00
;
1820 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
1821 entry
= data
->entry
;
1823 spin_lock_irqsave(&ioapic_lock
, flags
);
1824 reg_00
.raw
= io_apic_read(dev
->id
, 0);
1825 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
1826 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
1827 io_apic_write(dev
->id
, 0, reg_00
.raw
);
1829 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1830 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
1831 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
1836 static struct sysdev_class ioapic_sysdev_class
= {
1838 .suspend
= ioapic_suspend
,
1839 .resume
= ioapic_resume
,
1842 static int __init
ioapic_init_sysfs(void)
1844 struct sys_device
* dev
;
1847 error
= sysdev_class_register(&ioapic_sysdev_class
);
1851 for (i
= 0; i
< nr_ioapics
; i
++ ) {
1852 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
1853 * sizeof(struct IO_APIC_route_entry
);
1854 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
1855 if (!mp_ioapic_data
[i
]) {
1856 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
1859 dev
= &mp_ioapic_data
[i
]->dev
;
1861 dev
->cls
= &ioapic_sysdev_class
;
1862 error
= sysdev_register(dev
);
1864 kfree(mp_ioapic_data
[i
]);
1865 mp_ioapic_data
[i
] = NULL
;
1866 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
1874 device_initcall(ioapic_init_sysfs
);
1877 * Dynamic irq allocate and deallocation
1879 int create_irq(void)
1881 /* Allocate an unused irq */
1884 unsigned long flags
;
1887 spin_lock_irqsave(&vector_lock
, flags
);
1888 for (new = (NR_IRQS
- 1); new >= 0; new--) {
1889 if (platform_legacy_irq(new))
1891 if (irq_cfg
[new].vector
!= 0)
1893 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
1897 spin_unlock_irqrestore(&vector_lock
, flags
);
1900 dynamic_irq_init(irq
);
1905 void destroy_irq(unsigned int irq
)
1907 unsigned long flags
;
1909 dynamic_irq_cleanup(irq
);
1911 spin_lock_irqsave(&vector_lock
, flags
);
1912 __clear_irq_vector(irq
);
1913 spin_unlock_irqrestore(&vector_lock
, flags
);
1917 * MSI message composition
1919 #ifdef CONFIG_PCI_MSI
1920 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
1922 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1928 err
= assign_irq_vector(irq
, tmp
);
1930 cpus_and(tmp
, cfg
->domain
, tmp
);
1931 dest
= cpu_mask_to_apicid(tmp
);
1933 msg
->address_hi
= MSI_ADDR_BASE_HI
;
1936 ((INT_DEST_MODE
== 0) ?
1937 MSI_ADDR_DEST_MODE_PHYSICAL
:
1938 MSI_ADDR_DEST_MODE_LOGICAL
) |
1939 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
1940 MSI_ADDR_REDIRECTION_CPU
:
1941 MSI_ADDR_REDIRECTION_LOWPRI
) |
1942 MSI_ADDR_DEST_ID(dest
);
1945 MSI_DATA_TRIGGER_EDGE
|
1946 MSI_DATA_LEVEL_ASSERT
|
1947 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
1948 MSI_DATA_DELIVERY_FIXED
:
1949 MSI_DATA_DELIVERY_LOWPRI
) |
1950 MSI_DATA_VECTOR(cfg
->vector
);
1956 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
1958 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1963 cpus_and(tmp
, mask
, cpu_online_map
);
1964 if (cpus_empty(tmp
))
1967 if (assign_irq_vector(irq
, mask
))
1970 cpus_and(tmp
, cfg
->domain
, mask
);
1971 dest
= cpu_mask_to_apicid(tmp
);
1973 read_msi_msg(irq
, &msg
);
1975 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
1976 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
1977 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
1978 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
1980 write_msi_msg(irq
, &msg
);
1981 irq_desc
[irq
].affinity
= mask
;
1983 #endif /* CONFIG_SMP */
1986 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1987 * which implement the MSI or MSI-X Capability Structure.
1989 static struct irq_chip msi_chip
= {
1991 .unmask
= unmask_msi_irq
,
1992 .mask
= mask_msi_irq
,
1993 .ack
= ack_apic_edge
,
1995 .set_affinity
= set_msi_irq_affinity
,
1997 .retrigger
= ioapic_retrigger_irq
,
2000 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2008 ret
= msi_compose_msg(dev
, irq
, &msg
);
2014 set_irq_msi(irq
, desc
);
2015 write_msi_msg(irq
, &msg
);
2017 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2022 void arch_teardown_msi_irq(unsigned int irq
)
2029 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
2031 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2036 cpus_and(tmp
, mask
, cpu_online_map
);
2037 if (cpus_empty(tmp
))
2040 if (assign_irq_vector(irq
, mask
))
2043 cpus_and(tmp
, cfg
->domain
, mask
);
2044 dest
= cpu_mask_to_apicid(tmp
);
2046 dmar_msi_read(irq
, &msg
);
2048 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2049 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2050 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2051 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2053 dmar_msi_write(irq
, &msg
);
2054 irq_desc
[irq
].affinity
= mask
;
2056 #endif /* CONFIG_SMP */
2058 struct irq_chip dmar_msi_type
= {
2060 .unmask
= dmar_msi_unmask
,
2061 .mask
= dmar_msi_mask
,
2062 .ack
= ack_apic_edge
,
2064 .set_affinity
= dmar_msi_set_affinity
,
2066 .retrigger
= ioapic_retrigger_irq
,
2069 int arch_setup_dmar_msi(unsigned int irq
)
2074 ret
= msi_compose_msg(NULL
, irq
, &msg
);
2077 dmar_msi_write(irq
, &msg
);
2078 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
2084 #endif /* CONFIG_PCI_MSI */
2086 * Hypertransport interrupt support
2088 #ifdef CONFIG_HT_IRQ
2092 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2094 struct ht_irq_msg msg
;
2095 fetch_ht_irq_msg(irq
, &msg
);
2097 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2098 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2100 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2101 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2103 write_ht_irq_msg(irq
, &msg
);
2106 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2108 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2112 cpus_and(tmp
, mask
, cpu_online_map
);
2113 if (cpus_empty(tmp
))
2116 if (assign_irq_vector(irq
, mask
))
2119 cpus_and(tmp
, cfg
->domain
, mask
);
2120 dest
= cpu_mask_to_apicid(tmp
);
2122 target_ht_irq(irq
, dest
, cfg
->vector
);
2123 irq_desc
[irq
].affinity
= mask
;
2127 static struct irq_chip ht_irq_chip
= {
2129 .mask
= mask_ht_irq
,
2130 .unmask
= unmask_ht_irq
,
2131 .ack
= ack_apic_edge
,
2133 .set_affinity
= set_ht_irq_affinity
,
2135 .retrigger
= ioapic_retrigger_irq
,
2138 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2140 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2145 err
= assign_irq_vector(irq
, tmp
);
2147 struct ht_irq_msg msg
;
2150 cpus_and(tmp
, cfg
->domain
, tmp
);
2151 dest
= cpu_mask_to_apicid(tmp
);
2153 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2157 HT_IRQ_LOW_DEST_ID(dest
) |
2158 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2159 ((INT_DEST_MODE
== 0) ?
2160 HT_IRQ_LOW_DM_PHYSICAL
:
2161 HT_IRQ_LOW_DM_LOGICAL
) |
2162 HT_IRQ_LOW_RQEOI_EDGE
|
2163 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2164 HT_IRQ_LOW_MT_FIXED
:
2165 HT_IRQ_LOW_MT_ARBITRATED
) |
2166 HT_IRQ_LOW_IRQ_MASKED
;
2168 write_ht_irq_msg(irq
, &msg
);
2170 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2171 handle_edge_irq
, "edge");
2175 #endif /* CONFIG_HT_IRQ */
2177 /* --------------------------------------------------------------------------
2178 ACPI-based IOAPIC Configuration
2179 -------------------------------------------------------------------------- */
2183 #define IO_APIC_MAX_ID 0xFE
2185 int __init
io_apic_get_redir_entries (int ioapic
)
2187 union IO_APIC_reg_01 reg_01
;
2188 unsigned long flags
;
2190 spin_lock_irqsave(&ioapic_lock
, flags
);
2191 reg_01
.raw
= io_apic_read(ioapic
, 1);
2192 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2194 return reg_01
.bits
.entries
;
2198 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2200 if (!IO_APIC_IRQ(irq
)) {
2201 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2207 * IRQs < 16 are already in the irq_2_pin[] map
2210 add_pin_to_irq(irq
, ioapic
, pin
);
2212 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2218 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2222 if (skip_ioapic_setup
)
2225 for (i
= 0; i
< mp_irq_entries
; i
++)
2226 if (mp_irqs
[i
].mpc_irqtype
== mp_INT
&&
2227 mp_irqs
[i
].mpc_srcbusirq
== bus_irq
)
2229 if (i
>= mp_irq_entries
)
2232 *trigger
= irq_trigger(i
);
2233 *polarity
= irq_polarity(i
);
2237 #endif /* CONFIG_ACPI */
2240 * This function currently is only a helper for the i386 smp boot process where
2241 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2242 * so mask in all cases should simply be TARGET_CPUS
2245 void __init
setup_ioapic_dest(void)
2247 int pin
, ioapic
, irq
, irq_entry
;
2249 if (skip_ioapic_setup
== 1)
2252 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2253 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2254 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2255 if (irq_entry
== -1)
2257 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2259 /* setup_IO_APIC_irqs could fail to get vector for some device
2260 * when you have too many devices, because at that time only boot
2263 if (!irq_cfg
[irq
].vector
)
2264 setup_IO_APIC_irq(ioapic
, pin
, irq
,
2265 irq_trigger(irq_entry
),
2266 irq_polarity(irq_entry
));
2268 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2275 #define IOAPIC_RESOURCE_NAME_SIZE 11
2277 static struct resource
*ioapic_resources
;
2279 static struct resource
* __init
ioapic_setup_resources(void)
2282 struct resource
*res
;
2286 if (nr_ioapics
<= 0)
2289 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
2292 mem
= alloc_bootmem(n
);
2296 mem
+= sizeof(struct resource
) * nr_ioapics
;
2298 for (i
= 0; i
< nr_ioapics
; i
++) {
2300 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
2301 sprintf(mem
, "IOAPIC %u", i
);
2302 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
2306 ioapic_resources
= res
;
2311 void __init
ioapic_init_mappings(void)
2313 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2314 struct resource
*ioapic_res
;
2317 ioapic_res
= ioapic_setup_resources();
2318 for (i
= 0; i
< nr_ioapics
; i
++) {
2319 if (smp_found_config
) {
2320 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
2322 ioapic_phys
= (unsigned long)
2323 alloc_bootmem_pages(PAGE_SIZE
);
2324 ioapic_phys
= __pa(ioapic_phys
);
2326 set_fixmap_nocache(idx
, ioapic_phys
);
2327 apic_printk(APIC_VERBOSE
,
2328 "mapped IOAPIC to %016lx (%016lx)\n",
2329 __fix_to_virt(idx
), ioapic_phys
);
2332 if (ioapic_res
!= NULL
) {
2333 ioapic_res
->start
= ioapic_phys
;
2334 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
2340 static int __init
ioapic_insert_resources(void)
2343 struct resource
*r
= ioapic_resources
;
2347 "IO APIC resources could be not be allocated.\n");
2351 for (i
= 0; i
< nr_ioapics
; i
++) {
2352 insert_resource(&iomem_resource
, r
);
2359 /* Insert the IO APIC resources after PCI initialization has occured to handle
2360 * IO APICS that are mapped in on a BAR in PCI space. */
2361 late_initcall(ioapic_insert_resources
);