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1 /*
2 * Common interrupt code for 32 and 64 bit
3 */
4 #include <linux/cpu.h>
5 #include <linux/interrupt.h>
6 #include <linux/kernel_stat.h>
7 #include <linux/of.h>
8 #include <linux/seq_file.h>
9 #include <linux/smp.h>
10 #include <linux/ftrace.h>
11 #include <linux/delay.h>
12 #include <linux/export.h>
13
14 #include <asm/apic.h>
15 #include <asm/io_apic.h>
16 #include <asm/irq.h>
17 #include <asm/mce.h>
18 #include <asm/hw_irq.h>
19 #include <asm/desc.h>
20
21 #define CREATE_TRACE_POINTS
22 #include <asm/trace/irq_vectors.h>
23
24 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
25 EXPORT_PER_CPU_SYMBOL(irq_stat);
26
27 DEFINE_PER_CPU(struct pt_regs *, irq_regs);
28 EXPORT_PER_CPU_SYMBOL(irq_regs);
29
30 atomic_t irq_err_count;
31
32 /* Function pointer for generic interrupt vector handling */
33 void (*x86_platform_ipi_callback)(void) = NULL;
34
35 /*
36 * 'what should we do if we get a hw irq event on an illegal vector'.
37 * each architecture has to answer this themselves.
38 */
39 void ack_bad_irq(unsigned int irq)
40 {
41 if (printk_ratelimit())
42 pr_err("unexpected IRQ trap at vector %02x\n", irq);
43
44 /*
45 * Currently unexpected vectors happen only on SMP and APIC.
46 * We _must_ ack these because every local APIC has only N
47 * irq slots per priority level, and a 'hanging, unacked' IRQ
48 * holds up an irq slot - in excessive cases (when multiple
49 * unexpected vectors occur) that might lock up the APIC
50 * completely.
51 * But only ack when the APIC is enabled -AK
52 */
53 ack_APIC_irq();
54 }
55
56 #define irq_stats(x) (&per_cpu(irq_stat, x))
57 /*
58 * /proc/interrupts printing for arch specific interrupts
59 */
60 int arch_show_interrupts(struct seq_file *p, int prec)
61 {
62 int j;
63
64 seq_printf(p, "%*s: ", prec, "NMI");
65 for_each_online_cpu(j)
66 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
67 seq_puts(p, " Non-maskable interrupts\n");
68 #ifdef CONFIG_X86_LOCAL_APIC
69 seq_printf(p, "%*s: ", prec, "LOC");
70 for_each_online_cpu(j)
71 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
72 seq_puts(p, " Local timer interrupts\n");
73
74 seq_printf(p, "%*s: ", prec, "SPU");
75 for_each_online_cpu(j)
76 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
77 seq_puts(p, " Spurious interrupts\n");
78 seq_printf(p, "%*s: ", prec, "PMI");
79 for_each_online_cpu(j)
80 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
81 seq_puts(p, " Performance monitoring interrupts\n");
82 seq_printf(p, "%*s: ", prec, "IWI");
83 for_each_online_cpu(j)
84 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
85 seq_puts(p, " IRQ work interrupts\n");
86 seq_printf(p, "%*s: ", prec, "RTR");
87 for_each_online_cpu(j)
88 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
89 seq_puts(p, " APIC ICR read retries\n");
90 #endif
91 if (x86_platform_ipi_callback) {
92 seq_printf(p, "%*s: ", prec, "PLT");
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
95 seq_puts(p, " Platform interrupts\n");
96 }
97 #ifdef CONFIG_SMP
98 seq_printf(p, "%*s: ", prec, "RES");
99 for_each_online_cpu(j)
100 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
101 seq_puts(p, " Rescheduling interrupts\n");
102 seq_printf(p, "%*s: ", prec, "CAL");
103 for_each_online_cpu(j)
104 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
105 seq_puts(p, " Function call interrupts\n");
106 seq_printf(p, "%*s: ", prec, "TLB");
107 for_each_online_cpu(j)
108 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
109 seq_puts(p, " TLB shootdowns\n");
110 #endif
111 #ifdef CONFIG_X86_THERMAL_VECTOR
112 seq_printf(p, "%*s: ", prec, "TRM");
113 for_each_online_cpu(j)
114 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
115 seq_puts(p, " Thermal event interrupts\n");
116 #endif
117 #ifdef CONFIG_X86_MCE_THRESHOLD
118 seq_printf(p, "%*s: ", prec, "THR");
119 for_each_online_cpu(j)
120 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
121 seq_puts(p, " Threshold APIC interrupts\n");
122 #endif
123 #ifdef CONFIG_X86_MCE_AMD
124 seq_printf(p, "%*s: ", prec, "DFR");
125 for_each_online_cpu(j)
126 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
127 seq_puts(p, " Deferred Error APIC interrupts\n");
128 #endif
129 #ifdef CONFIG_X86_MCE
130 seq_printf(p, "%*s: ", prec, "MCE");
131 for_each_online_cpu(j)
132 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
133 seq_puts(p, " Machine check exceptions\n");
134 seq_printf(p, "%*s: ", prec, "MCP");
135 for_each_online_cpu(j)
136 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
137 seq_puts(p, " Machine check polls\n");
138 #endif
139 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
140 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) {
141 seq_printf(p, "%*s: ", prec, "HYP");
142 for_each_online_cpu(j)
143 seq_printf(p, "%10u ",
144 irq_stats(j)->irq_hv_callback_count);
145 seq_puts(p, " Hypervisor callback interrupts\n");
146 }
147 #endif
148 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
149 #if defined(CONFIG_X86_IO_APIC)
150 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
151 #endif
152 #ifdef CONFIG_HAVE_KVM
153 seq_printf(p, "%*s: ", prec, "PIN");
154 for_each_online_cpu(j)
155 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
156 seq_puts(p, " Posted-interrupt notification event\n");
157
158 seq_printf(p, "%*s: ", prec, "PIW");
159 for_each_online_cpu(j)
160 seq_printf(p, "%10u ",
161 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
162 seq_puts(p, " Posted-interrupt wakeup event\n");
163 #endif
164 return 0;
165 }
166
167 /*
168 * /proc/stat helpers
169 */
170 u64 arch_irq_stat_cpu(unsigned int cpu)
171 {
172 u64 sum = irq_stats(cpu)->__nmi_count;
173
174 #ifdef CONFIG_X86_LOCAL_APIC
175 sum += irq_stats(cpu)->apic_timer_irqs;
176 sum += irq_stats(cpu)->irq_spurious_count;
177 sum += irq_stats(cpu)->apic_perf_irqs;
178 sum += irq_stats(cpu)->apic_irq_work_irqs;
179 sum += irq_stats(cpu)->icr_read_retry_count;
180 #endif
181 if (x86_platform_ipi_callback)
182 sum += irq_stats(cpu)->x86_platform_ipis;
183 #ifdef CONFIG_SMP
184 sum += irq_stats(cpu)->irq_resched_count;
185 sum += irq_stats(cpu)->irq_call_count;
186 #endif
187 #ifdef CONFIG_X86_THERMAL_VECTOR
188 sum += irq_stats(cpu)->irq_thermal_count;
189 #endif
190 #ifdef CONFIG_X86_MCE_THRESHOLD
191 sum += irq_stats(cpu)->irq_threshold_count;
192 #endif
193 #ifdef CONFIG_X86_MCE
194 sum += per_cpu(mce_exception_count, cpu);
195 sum += per_cpu(mce_poll_count, cpu);
196 #endif
197 return sum;
198 }
199
200 u64 arch_irq_stat(void)
201 {
202 u64 sum = atomic_read(&irq_err_count);
203 return sum;
204 }
205
206
207 /*
208 * do_IRQ handles all normal device IRQ's (the special
209 * SMP cross-CPU interrupts have their own specific
210 * handlers).
211 */
212 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
213 {
214 struct pt_regs *old_regs = set_irq_regs(regs);
215 struct irq_desc * desc;
216 /* high bit used in ret_from_ code */
217 unsigned vector = ~regs->orig_ax;
218
219 /*
220 * NB: Unlike exception entries, IRQ entries do not reliably
221 * handle context tracking in the low-level entry code. This is
222 * because syscall entries execute briefly with IRQs on before
223 * updating context tracking state, so we can take an IRQ from
224 * kernel mode with CONTEXT_USER. The low-level entry code only
225 * updates the context if we came from user mode, so we won't
226 * switch to CONTEXT_KERNEL. We'll fix that once the syscall
227 * code is cleaned up enough that we can cleanly defer enabling
228 * IRQs.
229 */
230
231 entering_irq();
232
233 /* entering_irq() tells RCU that we're not quiescent. Check it. */
234 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
235
236 desc = __this_cpu_read(vector_irq[vector]);
237
238 if (!handle_irq(desc, regs)) {
239 ack_APIC_irq();
240
241 if (desc != VECTOR_RETRIGGERED) {
242 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
243 __func__, smp_processor_id(),
244 vector);
245 } else {
246 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
247 }
248 }
249
250 exiting_irq();
251
252 set_irq_regs(old_regs);
253 return 1;
254 }
255
256 /*
257 * Handler for X86_PLATFORM_IPI_VECTOR.
258 */
259 void __smp_x86_platform_ipi(void)
260 {
261 inc_irq_stat(x86_platform_ipis);
262
263 if (x86_platform_ipi_callback)
264 x86_platform_ipi_callback();
265 }
266
267 __visible void __irq_entry smp_x86_platform_ipi(struct pt_regs *regs)
268 {
269 struct pt_regs *old_regs = set_irq_regs(regs);
270
271 entering_ack_irq();
272 __smp_x86_platform_ipi();
273 exiting_irq();
274 set_irq_regs(old_regs);
275 }
276
277 #ifdef CONFIG_HAVE_KVM
278 static void dummy_handler(void) {}
279 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
280
281 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
282 {
283 if (handler)
284 kvm_posted_intr_wakeup_handler = handler;
285 else
286 kvm_posted_intr_wakeup_handler = dummy_handler;
287 }
288 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
289
290 /*
291 * Handler for POSTED_INTERRUPT_VECTOR.
292 */
293 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
294 {
295 struct pt_regs *old_regs = set_irq_regs(regs);
296
297 entering_ack_irq();
298 inc_irq_stat(kvm_posted_intr_ipis);
299 exiting_irq();
300 set_irq_regs(old_regs);
301 }
302
303 /*
304 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
305 */
306 __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
307 {
308 struct pt_regs *old_regs = set_irq_regs(regs);
309
310 entering_ack_irq();
311 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
312 kvm_posted_intr_wakeup_handler();
313 exiting_irq();
314 set_irq_regs(old_regs);
315 }
316 #endif
317
318 __visible void __irq_entry smp_trace_x86_platform_ipi(struct pt_regs *regs)
319 {
320 struct pt_regs *old_regs = set_irq_regs(regs);
321
322 entering_ack_irq();
323 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
324 __smp_x86_platform_ipi();
325 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
326 exiting_irq();
327 set_irq_regs(old_regs);
328 }
329
330 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
331
332 #ifdef CONFIG_HOTPLUG_CPU
333
334 /* These two declarations are only used in check_irq_vectors_for_cpu_disable()
335 * below, which is protected by stop_machine(). Putting them on the stack
336 * results in a stack frame overflow. Dynamically allocating could result in a
337 * failure so declare these two cpumasks as global.
338 */
339 static struct cpumask affinity_new, online_new;
340
341 /*
342 * This cpu is going to be removed and its vectors migrated to the remaining
343 * online cpus. Check to see if there are enough vectors in the remaining cpus.
344 * This function is protected by stop_machine().
345 */
346 int check_irq_vectors_for_cpu_disable(void)
347 {
348 unsigned int this_cpu, vector, this_count, count;
349 struct irq_desc *desc;
350 struct irq_data *data;
351 int cpu;
352
353 this_cpu = smp_processor_id();
354 cpumask_copy(&online_new, cpu_online_mask);
355 cpumask_clear_cpu(this_cpu, &online_new);
356
357 this_count = 0;
358 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
359 desc = __this_cpu_read(vector_irq[vector]);
360 if (IS_ERR_OR_NULL(desc))
361 continue;
362 /*
363 * Protect against concurrent action removal, affinity
364 * changes etc.
365 */
366 raw_spin_lock(&desc->lock);
367 data = irq_desc_get_irq_data(desc);
368 cpumask_copy(&affinity_new,
369 irq_data_get_affinity_mask(data));
370 cpumask_clear_cpu(this_cpu, &affinity_new);
371
372 /* Do not count inactive or per-cpu irqs. */
373 if (!irq_desc_has_action(desc) || irqd_is_per_cpu(data)) {
374 raw_spin_unlock(&desc->lock);
375 continue;
376 }
377
378 raw_spin_unlock(&desc->lock);
379 /*
380 * A single irq may be mapped to multiple cpu's
381 * vector_irq[] (for example IOAPIC cluster mode). In
382 * this case we have two possibilities:
383 *
384 * 1) the resulting affinity mask is empty; that is
385 * this the down'd cpu is the last cpu in the irq's
386 * affinity mask, or
387 *
388 * 2) the resulting affinity mask is no longer a
389 * subset of the online cpus but the affinity mask is
390 * not zero; that is the down'd cpu is the last online
391 * cpu in a user set affinity mask.
392 */
393 if (cpumask_empty(&affinity_new) ||
394 !cpumask_subset(&affinity_new, &online_new))
395 this_count++;
396 }
397 /* No need to check any further. */
398 if (!this_count)
399 return 0;
400
401 count = 0;
402 for_each_online_cpu(cpu) {
403 if (cpu == this_cpu)
404 continue;
405 /*
406 * We scan from FIRST_EXTERNAL_VECTOR to first system
407 * vector. If the vector is marked in the used vectors
408 * bitmap or an irq is assigned to it, we don't count
409 * it as available.
410 *
411 * As this is an inaccurate snapshot anyway, we can do
412 * this w/o holding vector_lock.
413 */
414 for (vector = FIRST_EXTERNAL_VECTOR;
415 vector < first_system_vector; vector++) {
416 if (!test_bit(vector, used_vectors) &&
417 IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector])) {
418 if (++count == this_count)
419 return 0;
420 }
421 }
422 }
423
424 if (count < this_count) {
425 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
426 this_cpu, this_count, count);
427 return -ERANGE;
428 }
429 return 0;
430 }
431
432 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
433 void fixup_irqs(void)
434 {
435 unsigned int irr, vector;
436 struct irq_desc *desc;
437 struct irq_data *data;
438 struct irq_chip *chip;
439
440 irq_migrate_all_off_this_cpu();
441
442 /*
443 * We can remove mdelay() and then send spuriuous interrupts to
444 * new cpu targets for all the irqs that were handled previously by
445 * this cpu. While it works, I have seen spurious interrupt messages
446 * (nothing wrong but still...).
447 *
448 * So for now, retain mdelay(1) and check the IRR and then send those
449 * interrupts to new targets as this cpu is already offlined...
450 */
451 mdelay(1);
452
453 /*
454 * We can walk the vector array of this cpu without holding
455 * vector_lock because the cpu is already marked !online, so
456 * nothing else will touch it.
457 */
458 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
459 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
460 continue;
461
462 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
463 if (irr & (1 << (vector % 32))) {
464 desc = __this_cpu_read(vector_irq[vector]);
465
466 raw_spin_lock(&desc->lock);
467 data = irq_desc_get_irq_data(desc);
468 chip = irq_data_get_irq_chip(data);
469 if (chip->irq_retrigger) {
470 chip->irq_retrigger(data);
471 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
472 }
473 raw_spin_unlock(&desc->lock);
474 }
475 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
476 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
477 }
478 }
479 #endif