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1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
24
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
31
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38
39 /*
40 * Various Linux-internal data structures created from the
41 * MP-table.
42 */
43 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
44 int mp_bus_id_to_type[MAX_MP_BUSSES];
45 #endif
46 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
47 int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
48 static int mp_current_pci_id;
49
50 int pic_mode;
51
52 /*
53 * Intel MP BIOS table parsing routines:
54 */
55
56 /*
57 * Checksum an MP configuration block.
58 */
59
60 static int __init mpf_checksum(unsigned char *mp, int len)
61 {
62 int sum = 0;
63
64 while (len--)
65 sum += *mp++;
66
67 return sum & 0xFF;
68 }
69
70 #ifdef CONFIG_X86_NUMAQ
71 /*
72 * Have to match translation table entries to main table entries by counter
73 * hence the mpc_record variable .... can't see a less disgusting way of
74 * doing this ....
75 */
76
77 static int mpc_record;
78 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY]
79 __cpuinitdata;
80 #endif
81
82 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
83 {
84 int apicid;
85 char *bootup_cpu = "";
86
87 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
88 disabled_cpus++;
89 return;
90 }
91 #ifdef CONFIG_X86_NUMAQ
92 apicid = mpc_apic_id(m, translation_table[mpc_record]);
93 #else
94 apicid = m->mpc_apicid;
95 #endif
96 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
97 bootup_cpu = " (Bootup-CPU)";
98 boot_cpu_physical_apicid = m->mpc_apicid;
99 }
100
101 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
102 generic_processor_info(apicid, m->mpc_apicver);
103 }
104
105 static void __init MP_bus_info(struct mpc_config_bus *m)
106 {
107 char str[7];
108
109 memcpy(str, m->mpc_bustype, 6);
110 str[6] = 0;
111
112 #ifdef CONFIG_X86_NUMAQ
113 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
114 #else
115 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
116 #endif
117
118 #if MAX_MP_BUSSES < 256
119 if (m->mpc_busid >= MAX_MP_BUSSES) {
120 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
121 " is too large, max. supported is %d\n",
122 m->mpc_busid, str, MAX_MP_BUSSES - 1);
123 return;
124 }
125 #endif
126
127 set_bit(m->mpc_busid, mp_bus_not_pci);
128 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
129 #ifdef CONFIG_X86_NUMAQ
130 mpc_oem_pci_bus(m, translation_table[mpc_record]);
131 #endif
132 clear_bit(m->mpc_busid, mp_bus_not_pci);
133 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
134 mp_current_pci_id++;
135 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
136 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
137 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) {
138 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
139 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
140 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
141 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) {
142 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
143 } else {
144 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
145 #endif
146 }
147 }
148
149 #ifdef CONFIG_X86_IO_APIC
150
151 static int bad_ioapic(unsigned long address)
152 {
153 if (nr_ioapics >= MAX_IO_APICS) {
154 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
155 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
156 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
157 }
158 if (!address) {
159 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
160 " found in table, skipping!\n");
161 return 1;
162 }
163 return 0;
164 }
165
166 static void __init MP_ioapic_info(struct mpc_config_ioapic *m)
167 {
168 if (!(m->mpc_flags & MPC_APIC_USABLE))
169 return;
170
171 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
172 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
173
174 if (bad_ioapic(m->mpc_apicaddr))
175 return;
176
177 mp_ioapics[nr_ioapics] = *m;
178 nr_ioapics++;
179 }
180
181 static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
182 {
183 mp_irqs[mp_irq_entries] = *m;
184 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
185 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
186 m->mpc_irqtype, m->mpc_irqflag & 3,
187 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
188 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
189 if (++mp_irq_entries == MAX_IRQ_SOURCES)
190 panic("Max # of irq sources exceeded!!\n");
191 }
192
193 #endif
194
195 static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m)
196 {
197 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
198 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
199 m->mpc_irqtype, m->mpc_irqflag & 3,
200 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid,
201 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
202 }
203
204 #ifdef CONFIG_X86_NUMAQ
205 static void __init MP_translation_info(struct mpc_config_translation *m)
206 {
207 printk(KERN_INFO
208 "Translation: record %d, type %d, quad %d, global %d, local %d\n",
209 mpc_record, m->trans_type, m->trans_quad, m->trans_global,
210 m->trans_local);
211
212 if (mpc_record >= MAX_MPC_ENTRY)
213 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
214 else
215 translation_table[mpc_record] = m; /* stash this for later */
216 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
217 node_set_online(m->trans_quad);
218 }
219
220 /*
221 * Read/parse the MPC oem tables
222 */
223
224 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable,
225 unsigned short oemsize)
226 {
227 int count = sizeof(*oemtable); /* the header size */
228 unsigned char *oemptr = ((unsigned char *)oemtable) + count;
229
230 mpc_record = 0;
231 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n",
232 oemtable);
233 if (memcmp(oemtable->oem_signature, MPC_OEM_SIGNATURE, 4)) {
234 printk(KERN_WARNING
235 "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
236 oemtable->oem_signature[0], oemtable->oem_signature[1],
237 oemtable->oem_signature[2], oemtable->oem_signature[3]);
238 return;
239 }
240 if (mpf_checksum((unsigned char *)oemtable, oemtable->oem_length)) {
241 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
242 return;
243 }
244 while (count < oemtable->oem_length) {
245 switch (*oemptr) {
246 case MP_TRANSLATION:
247 {
248 struct mpc_config_translation *m =
249 (struct mpc_config_translation *)oemptr;
250 MP_translation_info(m);
251 oemptr += sizeof(*m);
252 count += sizeof(*m);
253 ++mpc_record;
254 break;
255 }
256 default:
257 {
258 printk(KERN_WARNING
259 "Unrecognised OEM table entry type! - %d\n",
260 (int)*oemptr);
261 return;
262 }
263 }
264 }
265 }
266
267 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
268 char *productid)
269 {
270 if (strncmp(oem, "IBM NUMA", 8))
271 printk("Warning! May not be a NUMA-Q system!\n");
272 if (mpc->mpc_oemptr)
273 smp_read_mpc_oem((struct mp_config_oemtable *)mpc->mpc_oemptr,
274 mpc->mpc_oemsize);
275 }
276 #endif /* CONFIG_X86_NUMAQ */
277
278 /*
279 * Read/parse the MPC
280 */
281
282 static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
283 {
284 char str[16];
285 char oem[10];
286 int count = sizeof(*mpc);
287 unsigned char *mpt = ((unsigned char *)mpc) + count;
288
289 if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) {
290 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
291 *(u32 *) mpc->mpc_signature);
292 return 0;
293 }
294 if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) {
295 printk(KERN_ERR "SMP mptable: checksum error!\n");
296 return 0;
297 }
298 if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) {
299 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
300 mpc->mpc_spec);
301 return 0;
302 }
303 if (!mpc->mpc_lapic) {
304 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
305 return 0;
306 }
307 memcpy(oem, mpc->mpc_oem, 8);
308 oem[8] = 0;
309 printk(KERN_INFO "OEM ID: %s ", oem);
310
311 memcpy(str, mpc->mpc_productid, 12);
312 str[12] = 0;
313 printk("Product ID: %s ", str);
314
315 mps_oem_check(mpc, oem, str);
316
317 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
318
319 /*
320 * Save the local APIC address (it might be non-default) -- but only
321 * if we're not using ACPI.
322 */
323 if (!acpi_lapic)
324 mp_lapic_addr = mpc->mpc_lapic;
325
326 if (early)
327 return 1;
328
329 /*
330 * Now process the configuration blocks.
331 */
332 #ifdef CONFIG_X86_NUMAQ
333 mpc_record = 0;
334 #endif
335 while (count < mpc->mpc_length) {
336 switch (*mpt) {
337 case MP_PROCESSOR:
338 {
339 struct mpc_config_processor *m =
340 (struct mpc_config_processor *)mpt;
341 /* ACPI may have already provided this data */
342 if (!acpi_lapic)
343 MP_processor_info(m);
344 mpt += sizeof(*m);
345 count += sizeof(*m);
346 break;
347 }
348 case MP_BUS:
349 {
350 struct mpc_config_bus *m =
351 (struct mpc_config_bus *)mpt;
352 MP_bus_info(m);
353 mpt += sizeof(*m);
354 count += sizeof(*m);
355 break;
356 }
357 case MP_IOAPIC:
358 {
359 #ifdef CONFIG_X86_IO_APIC
360 struct mpc_config_ioapic *m =
361 (struct mpc_config_ioapic *)mpt;
362 MP_ioapic_info(m);
363 #endif
364 mpt += sizeof(struct mpc_config_ioapic);
365 count += sizeof(struct mpc_config_ioapic);
366 break;
367 }
368 case MP_INTSRC:
369 {
370 #ifdef CONFIG_X86_IO_APIC
371 struct mpc_config_intsrc *m =
372 (struct mpc_config_intsrc *)mpt;
373
374 MP_intsrc_info(m);
375 #endif
376 mpt += sizeof(struct mpc_config_intsrc);
377 count += sizeof(struct mpc_config_intsrc);
378 break;
379 }
380 case MP_LINTSRC:
381 {
382 struct mpc_config_lintsrc *m =
383 (struct mpc_config_lintsrc *)mpt;
384 MP_lintsrc_info(m);
385 mpt += sizeof(*m);
386 count += sizeof(*m);
387 break;
388 }
389 default:
390 {
391 count = mpc->mpc_length;
392 break;
393 }
394 }
395 #ifdef CONFIG_X86_NUMAQ
396 ++mpc_record;
397 #endif
398 }
399 setup_apic_routing();
400 if (!num_processors)
401 printk(KERN_ERR "SMP mptable: no processors registered!\n");
402 return num_processors;
403 }
404
405 #ifdef CONFIG_X86_IO_APIC
406
407 static int __init ELCR_trigger(unsigned int irq)
408 {
409 unsigned int port;
410
411 port = 0x4d0 + (irq >> 3);
412 return (inb(port) >> (irq & 7)) & 1;
413 }
414
415 static void __init construct_default_ioirq_mptable(int mpc_default_type)
416 {
417 struct mpc_config_intsrc intsrc;
418 int i;
419 int ELCR_fallback = 0;
420
421 intsrc.mpc_type = MP_INTSRC;
422 intsrc.mpc_irqflag = 0; /* conforming */
423 intsrc.mpc_srcbus = 0;
424 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
425
426 intsrc.mpc_irqtype = mp_INT;
427
428 /*
429 * If true, we have an ISA/PCI system with no IRQ entries
430 * in the MP table. To prevent the PCI interrupts from being set up
431 * incorrectly, we try to use the ELCR. The sanity check to see if
432 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
433 * never be level sensitive, so we simply see if the ELCR agrees.
434 * If it does, we assume it's valid.
435 */
436 if (mpc_default_type == 5) {
437 printk(KERN_INFO
438 "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
439
440 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2)
441 || ELCR_trigger(13))
442 printk(KERN_WARNING
443 "ELCR contains invalid data... not using ELCR\n");
444 else {
445 printk(KERN_INFO
446 "Using ELCR to identify PCI interrupts\n");
447 ELCR_fallback = 1;
448 }
449 }
450
451 for (i = 0; i < 16; i++) {
452 switch (mpc_default_type) {
453 case 2:
454 if (i == 0 || i == 13)
455 continue; /* IRQ0 & IRQ13 not connected */
456 /* fall through */
457 default:
458 if (i == 2)
459 continue; /* IRQ2 is never connected */
460 }
461
462 if (ELCR_fallback) {
463 /*
464 * If the ELCR indicates a level-sensitive interrupt, we
465 * copy that information over to the MP table in the
466 * irqflag field (level sensitive, active high polarity).
467 */
468 if (ELCR_trigger(i))
469 intsrc.mpc_irqflag = 13;
470 else
471 intsrc.mpc_irqflag = 0;
472 }
473
474 intsrc.mpc_srcbusirq = i;
475 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
476 MP_intsrc_info(&intsrc);
477 }
478
479 intsrc.mpc_irqtype = mp_ExtINT;
480 intsrc.mpc_srcbusirq = 0;
481 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
482 MP_intsrc_info(&intsrc);
483 }
484
485 #endif
486
487 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
488 {
489 struct mpc_config_processor processor;
490 struct mpc_config_bus bus;
491 #ifdef CONFIG_X86_IO_APIC
492 struct mpc_config_ioapic ioapic;
493 #endif
494 struct mpc_config_lintsrc lintsrc;
495 int linttypes[2] = { mp_ExtINT, mp_NMI };
496 int i;
497
498 /*
499 * local APIC has default address
500 */
501 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
502
503 /*
504 * 2 CPUs, numbered 0 & 1.
505 */
506 processor.mpc_type = MP_PROCESSOR;
507 /* Either an integrated APIC or a discrete 82489DX. */
508 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
509 processor.mpc_cpuflag = CPU_ENABLED;
510 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
511 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
512 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
513 processor.mpc_reserved[0] = 0;
514 processor.mpc_reserved[1] = 0;
515 for (i = 0; i < 2; i++) {
516 processor.mpc_apicid = i;
517 MP_processor_info(&processor);
518 }
519
520 bus.mpc_type = MP_BUS;
521 bus.mpc_busid = 0;
522 switch (mpc_default_type) {
523 default:
524 printk("???\n");
525 printk(KERN_ERR "Unknown standard configuration %d\n",
526 mpc_default_type);
527 /* fall through */
528 case 1:
529 case 5:
530 memcpy(bus.mpc_bustype, "ISA ", 6);
531 break;
532 case 2:
533 case 6:
534 case 3:
535 memcpy(bus.mpc_bustype, "EISA ", 6);
536 break;
537 case 4:
538 case 7:
539 memcpy(bus.mpc_bustype, "MCA ", 6);
540 }
541 MP_bus_info(&bus);
542 if (mpc_default_type > 4) {
543 bus.mpc_busid = 1;
544 memcpy(bus.mpc_bustype, "PCI ", 6);
545 MP_bus_info(&bus);
546 }
547
548 #ifdef CONFIG_X86_IO_APIC
549 ioapic.mpc_type = MP_IOAPIC;
550 ioapic.mpc_apicid = 2;
551 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
552 ioapic.mpc_flags = MPC_APIC_USABLE;
553 ioapic.mpc_apicaddr = 0xFEC00000;
554 MP_ioapic_info(&ioapic);
555
556 /*
557 * We set up most of the low 16 IO-APIC pins according to MPS rules.
558 */
559 construct_default_ioirq_mptable(mpc_default_type);
560 #endif
561 lintsrc.mpc_type = MP_LINTSRC;
562 lintsrc.mpc_irqflag = 0; /* conforming */
563 lintsrc.mpc_srcbusid = 0;
564 lintsrc.mpc_srcbusirq = 0;
565 lintsrc.mpc_destapic = MP_APIC_ALL;
566 for (i = 0; i < 2; i++) {
567 lintsrc.mpc_irqtype = linttypes[i];
568 lintsrc.mpc_destapiclint = i;
569 MP_lintsrc_info(&lintsrc);
570 }
571 }
572
573 static struct intel_mp_floating *mpf_found;
574
575 /*
576 * Scan the memory blocks for an SMP configuration block.
577 */
578 static void __init __get_smp_config(unsigned early)
579 {
580 struct intel_mp_floating *mpf = mpf_found;
581
582 if (acpi_lapic && early)
583 return;
584
585 /*
586 * ACPI supports both logical (e.g. Hyper-Threading) and physical
587 * processors, where MPS only supports physical.
588 */
589 if (acpi_lapic && acpi_ioapic) {
590 printk(KERN_INFO
591 "Using ACPI (MADT) for SMP configuration information\n");
592 return;
593 } else if (acpi_lapic)
594 printk(KERN_INFO
595 "Using ACPI for processor (LAPIC) configuration information\n");
596
597 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
598 mpf->mpf_specification);
599 if (mpf->mpf_feature2 & (1 << 7)) {
600 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
601 pic_mode = 1;
602 } else {
603 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
604 pic_mode = 0;
605 }
606
607 /*
608 * Now see if we need to read further.
609 */
610 if (mpf->mpf_feature1 != 0) {
611 if (early) {
612 /*
613 * local APIC has default address
614 */
615 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
616 return;
617 }
618
619 printk(KERN_INFO "Default MP configuration #%d\n",
620 mpf->mpf_feature1);
621 construct_default_ISA_mptable(mpf->mpf_feature1);
622
623 } else if (mpf->mpf_physptr) {
624
625 /*
626 * Read the physical hardware table. Anything here will
627 * override the defaults.
628 */
629 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) {
630 smp_found_config = 0;
631 printk(KERN_ERR
632 "BIOS bug, MP table errors detected!...\n");
633 printk(KERN_ERR
634 "... disabling SMP support. (tell your hw vendor)\n");
635 return;
636 }
637
638 if (early)
639 return;
640 #ifdef CONFIG_X86_IO_APIC
641 /*
642 * If there are no explicit MP IRQ entries, then we are
643 * broken. We set up most of the low 16 IO-APIC pins to
644 * ISA defaults and hope it will work.
645 */
646 if (!mp_irq_entries) {
647 struct mpc_config_bus bus;
648
649 printk(KERN_ERR
650 "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
651
652 bus.mpc_type = MP_BUS;
653 bus.mpc_busid = 0;
654 memcpy(bus.mpc_bustype, "ISA ", 6);
655 MP_bus_info(&bus);
656
657 construct_default_ioirq_mptable(0);
658 }
659 #endif
660 } else
661 BUG();
662
663 if (!early)
664 printk(KERN_INFO "Processors: %d\n", num_processors);
665 /*
666 * Only use the first configuration found.
667 */
668 }
669
670 void __init early_get_smp_config(void)
671 {
672 __get_smp_config(1);
673 }
674
675 void __init get_smp_config(void)
676 {
677 __get_smp_config(0);
678 }
679
680 static int __init smp_scan_config(unsigned long base, unsigned long length,
681 unsigned reserve)
682 {
683 unsigned long *bp = phys_to_virt(base);
684 struct intel_mp_floating *mpf;
685
686 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp, length);
687 if (sizeof(*mpf) != 16)
688 printk("Error: MPF size\n");
689
690 while (length > 0) {
691 mpf = (struct intel_mp_floating *)bp;
692 if ((*bp == SMP_MAGIC_IDENT) &&
693 (mpf->mpf_length == 1) &&
694 !mpf_checksum((unsigned char *)bp, 16) &&
695 ((mpf->mpf_specification == 1)
696 || (mpf->mpf_specification == 4))) {
697
698 smp_found_config = 1;
699 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
700 mpf, virt_to_phys(mpf));
701 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
702 BOOTMEM_DEFAULT);
703 if (mpf->mpf_physptr) {
704 /*
705 * We cannot access to MPC table to compute
706 * table size yet, as only few megabytes from
707 * the bottom is mapped now.
708 * PC-9800's MPC table places on the very last
709 * of physical memory; so that simply reserving
710 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
711 * in reserve_bootmem.
712 */
713 unsigned long size = PAGE_SIZE;
714 unsigned long end = max_low_pfn * PAGE_SIZE;
715 if (mpf->mpf_physptr + size > end)
716 size = end - mpf->mpf_physptr;
717 reserve_bootmem(mpf->mpf_physptr, size,
718 BOOTMEM_DEFAULT);
719 }
720
721 mpf_found = mpf;
722 return 1;
723 }
724 bp += 4;
725 length -= 16;
726 }
727 return 0;
728 }
729
730 static void __init __find_smp_config(unsigned reserve)
731 {
732 unsigned int address;
733
734 /*
735 * FIXME: Linux assumes you have 640K of base ram..
736 * this continues the error...
737 *
738 * 1) Scan the bottom 1K for a signature
739 * 2) Scan the top 1K of base RAM
740 * 3) Scan the 64K of bios
741 */
742 if (smp_scan_config(0x0, 0x400, reserve) ||
743 smp_scan_config(639 * 0x400, 0x400, reserve) ||
744 smp_scan_config(0xF0000, 0x10000, reserve))
745 return;
746 /*
747 * If it is an SMP machine we should know now, unless the
748 * configuration is in an EISA/MCA bus machine with an
749 * extended bios data area.
750 *
751 * there is a real-mode segmented pointer pointing to the
752 * 4K EBDA area at 0x40E, calculate and scan it here.
753 *
754 * NOTE! There are Linux loaders that will corrupt the EBDA
755 * area, and as such this kind of SMP config may be less
756 * trustworthy, simply because the SMP table may have been
757 * stomped on during early boot. These loaders are buggy and
758 * should be fixed.
759 *
760 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
761 */
762
763 address = get_bios_ebda();
764 if (address)
765 smp_scan_config(address, 0x400, reserve);
766 }
767
768 void __init early_find_smp_config(void)
769 {
770 __find_smp_config(0);
771 }
772
773 void __init find_smp_config(void)
774 {
775 __find_smp_config(1);
776 }
777
778 /* --------------------------------------------------------------------------
779 ACPI-based MP Configuration
780 -------------------------------------------------------------------------- */
781
782 #ifdef CONFIG_ACPI
783
784 #ifdef CONFIG_X86_IO_APIC
785
786 #define MP_ISA_BUS 0
787 #define MP_MAX_IOAPIC_PIN 127
788
789 extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
790
791 static int mp_find_ioapic(int gsi)
792 {
793 int i = 0;
794
795 /* Find the IOAPIC that manages this GSI. */
796 for (i = 0; i < nr_ioapics; i++) {
797 if ((gsi >= mp_ioapic_routing[i].gsi_base)
798 && (gsi <= mp_ioapic_routing[i].gsi_end))
799 return i;
800 }
801
802 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
803
804 return -1;
805 }
806
807 static u8 uniq_ioapic_id(u8 id)
808 {
809 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
810 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
811 return io_apic_get_unique_id(nr_ioapics, id);
812 else
813 return id;
814 }
815
816 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
817 {
818 int idx = 0;
819
820 if (bad_ioapic(address))
821 return;
822
823 idx = nr_ioapics;
824
825 mp_ioapics[idx].mpc_type = MP_IOAPIC;
826 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
827 mp_ioapics[idx].mpc_apicaddr = address;
828
829 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
830 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
831 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
832
833 /*
834 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
835 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
836 */
837 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
838 mp_ioapic_routing[idx].gsi_base = gsi_base;
839 mp_ioapic_routing[idx].gsi_end = gsi_base +
840 io_apic_get_redir_entries(idx);
841
842 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
843 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
844 mp_ioapics[idx].mpc_apicver,
845 mp_ioapics[idx].mpc_apicaddr,
846 mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
847
848 nr_ioapics++;
849 }
850
851 void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
852 {
853 struct mpc_config_intsrc intsrc;
854 int ioapic = -1;
855 int pin = -1;
856
857 /*
858 * Convert 'gsi' to 'ioapic.pin'.
859 */
860 ioapic = mp_find_ioapic(gsi);
861 if (ioapic < 0)
862 return;
863 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
864
865 /*
866 * TBD: This check is for faulty timer entries, where the override
867 * erroneously sets the trigger to level, resulting in a HUGE
868 * increase of timer interrupts!
869 */
870 if ((bus_irq == 0) && (trigger == 3))
871 trigger = 1;
872
873 intsrc.mpc_type = MP_INTSRC;
874 intsrc.mpc_irqtype = mp_INT;
875 intsrc.mpc_irqflag = (trigger << 2) | polarity;
876 intsrc.mpc_srcbus = MP_ISA_BUS;
877 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
878 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
879 intsrc.mpc_dstirq = pin; /* INTIN# */
880
881 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
882 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
883 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
884 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
885
886 mp_irqs[mp_irq_entries] = intsrc;
887 if (++mp_irq_entries == MAX_IRQ_SOURCES)
888 panic("Max # of irq sources exceeded!\n");
889 }
890
891 int es7000_plat;
892
893 void __init mp_config_acpi_legacy_irqs(void)
894 {
895 struct mpc_config_intsrc intsrc;
896 int i = 0;
897 int ioapic = -1;
898
899 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
900 /*
901 * Fabricate the legacy ISA bus (bus #31).
902 */
903 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
904 #endif
905 set_bit(MP_ISA_BUS, mp_bus_not_pci);
906 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
907
908 /*
909 * Older generations of ES7000 have no legacy identity mappings
910 */
911 if (es7000_plat == 1)
912 return;
913
914 /*
915 * Locate the IOAPIC that manages the ISA IRQs (0-15).
916 */
917 ioapic = mp_find_ioapic(0);
918 if (ioapic < 0)
919 return;
920
921 intsrc.mpc_type = MP_INTSRC;
922 intsrc.mpc_irqflag = 0; /* Conforming */
923 intsrc.mpc_srcbus = MP_ISA_BUS;
924 #ifdef CONFIG_X86_IO_APIC
925 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
926 #endif
927 /*
928 * Use the default configuration for the IRQs 0-15. Unless
929 * overridden by (MADT) interrupt source override entries.
930 */
931 for (i = 0; i < 16; i++) {
932 int idx;
933
934 for (idx = 0; idx < mp_irq_entries; idx++) {
935 struct mpc_config_intsrc *irq = mp_irqs + idx;
936
937 /* Do we already have a mapping for this ISA IRQ? */
938 if (irq->mpc_srcbus == MP_ISA_BUS
939 && irq->mpc_srcbusirq == i)
940 break;
941
942 /* Do we already have a mapping for this IOAPIC pin */
943 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
944 (irq->mpc_dstirq == i))
945 break;
946 }
947
948 if (idx != mp_irq_entries) {
949 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
950 continue; /* IRQ already used */
951 }
952
953 intsrc.mpc_irqtype = mp_INT;
954 intsrc.mpc_srcbusirq = i; /* Identity mapped */
955 intsrc.mpc_dstirq = i;
956
957 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
958 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
959 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
960 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
961 intsrc.mpc_dstirq);
962
963 mp_irqs[mp_irq_entries] = intsrc;
964 if (++mp_irq_entries == MAX_IRQ_SOURCES)
965 panic("Max # of irq sources exceeded!\n");
966 }
967 }
968
969 #define MAX_GSI_NUM 4096
970 #define IRQ_COMPRESSION_START 64
971
972 int mp_register_gsi(u32 gsi, int triggering, int polarity)
973 {
974 int ioapic = -1;
975 int ioapic_pin = 0;
976 int idx, bit = 0;
977 static int pci_irq = IRQ_COMPRESSION_START;
978 /*
979 * Mapping between Global System Interrupts, which
980 * represent all possible interrupts, and IRQs
981 * assigned to actual devices.
982 */
983 static int gsi_to_irq[MAX_GSI_NUM];
984
985 /* Don't set up the ACPI SCI because it's already set up */
986 if (acpi_gbl_FADT.sci_interrupt == gsi)
987 return gsi;
988
989 ioapic = mp_find_ioapic(gsi);
990 if (ioapic < 0) {
991 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
992 return gsi;
993 }
994
995 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
996
997 if (ioapic_renumber_irq)
998 gsi = ioapic_renumber_irq(ioapic, gsi);
999
1000 /*
1001 * Avoid pin reprogramming. PRTs typically include entries
1002 * with redundant pin->gsi mappings (but unique PCI devices);
1003 * we only program the IOAPIC on the first.
1004 */
1005 bit = ioapic_pin % 32;
1006 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1007 if (idx > 3) {
1008 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1009 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1010 ioapic_pin);
1011 return gsi;
1012 }
1013 if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1014 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1015 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1016 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1017 }
1018
1019 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit);
1020
1021 /*
1022 * For GSI >= 64, use IRQ compression
1023 */
1024 if ((gsi >= IRQ_COMPRESSION_START)
1025 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1026 /*
1027 * For PCI devices assign IRQs in order, avoiding gaps
1028 * due to unused I/O APIC pins.
1029 */
1030 int irq = gsi;
1031 if (gsi < MAX_GSI_NUM) {
1032 /*
1033 * Retain the VIA chipset work-around (gsi > 15), but
1034 * avoid a problem where the 8254 timer (IRQ0) is setup
1035 * via an override (so it's not on pin 0 of the ioapic),
1036 * and at the same time, the pin 0 interrupt is a PCI
1037 * type. The gsi > 15 test could cause these two pins
1038 * to be shared as IRQ0, and they are not shareable.
1039 * So test for this condition, and if necessary, avoid
1040 * the pin collision.
1041 */
1042 gsi = pci_irq++;
1043 /*
1044 * Don't assign IRQ used by ACPI SCI
1045 */
1046 if (gsi == acpi_gbl_FADT.sci_interrupt)
1047 gsi = pci_irq++;
1048 gsi_to_irq[irq] = gsi;
1049 } else {
1050 printk(KERN_ERR "GSI %u is too high\n", gsi);
1051 return gsi;
1052 }
1053 }
1054
1055 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1056 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1057 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1058 return gsi;
1059 }
1060
1061 #endif /* CONFIG_X86_IO_APIC */
1062 #endif /* CONFIG_ACPI */
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