2 * Derived from arch/powerpc/kernel/iommu.c
4 * Copyright IBM Corporation, 2006-2007
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #define pr_fmt(fmt) "Calgary: " fmt
27 #include <linux/kernel.h>
28 #include <linux/init.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33 #include <linux/string.h>
34 #include <linux/crash_dump.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/bitmap.h>
37 #include <linux/pci_ids.h>
38 #include <linux/pci.h>
39 #include <linux/delay.h>
40 #include <linux/scatterlist.h>
41 #include <linux/iommu-helper.h>
43 #include <asm/iommu.h>
44 #include <asm/calgary.h>
46 #include <asm/pci-direct.h>
49 #include <asm/bios_ebda.h>
50 #include <asm/x86_init.h>
51 #include <asm/iommu_table.h>
53 #define CALGARY_MAPPING_ERROR 0
55 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
56 int use_calgary __read_mostly
= 1;
58 int use_calgary __read_mostly
= 0;
59 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
61 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
62 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
64 /* register offsets inside the host bridge space */
65 #define CALGARY_CONFIG_REG 0x0108
66 #define PHB_CSR_OFFSET 0x0110 /* Channel Status */
67 #define PHB_PLSSR_OFFSET 0x0120
68 #define PHB_CONFIG_RW_OFFSET 0x0160
69 #define PHB_IOBASE_BAR_LOW 0x0170
70 #define PHB_IOBASE_BAR_HIGH 0x0180
71 #define PHB_MEM_1_LOW 0x0190
72 #define PHB_MEM_1_HIGH 0x01A0
73 #define PHB_IO_ADDR_SIZE 0x01B0
74 #define PHB_MEM_1_SIZE 0x01C0
75 #define PHB_MEM_ST_OFFSET 0x01D0
76 #define PHB_AER_OFFSET 0x0200
77 #define PHB_CONFIG_0_HIGH 0x0220
78 #define PHB_CONFIG_0_LOW 0x0230
79 #define PHB_CONFIG_0_END 0x0240
80 #define PHB_MEM_2_LOW 0x02B0
81 #define PHB_MEM_2_HIGH 0x02C0
82 #define PHB_MEM_2_SIZE_HIGH 0x02D0
83 #define PHB_MEM_2_SIZE_LOW 0x02E0
84 #define PHB_DOSHOLE_OFFSET 0x08E0
86 /* CalIOC2 specific */
87 #define PHB_SAVIOR_L2 0x0DB0
88 #define PHB_PAGE_MIG_CTRL 0x0DA8
89 #define PHB_PAGE_MIG_DEBUG 0x0DA0
90 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
93 #define PHB_TCE_ENABLE 0x20000000
94 #define PHB_SLOT_DISABLE 0x1C000000
95 #define PHB_DAC_DISABLE 0x01000000
96 #define PHB_MEM2_ENABLE 0x00400000
97 #define PHB_MCSR_ENABLE 0x00100000
98 /* TAR (Table Address Register) */
99 #define TAR_SW_BITS 0x0000ffffffff800fUL
100 #define TAR_VALID 0x0000000000000008UL
101 /* CSR (Channel/DMA Status Register) */
102 #define CSR_AGENT_MASK 0xffe0ffff
103 /* CCR (Calgary Configuration Register) */
104 #define CCR_2SEC_TIMEOUT 0x000000000000000EUL
105 /* PMCR/PMDR (Page Migration Control/Debug Registers */
106 #define PMR_SOFTSTOP 0x80000000
107 #define PMR_SOFTSTOPFAULT 0x40000000
108 #define PMR_HARDSTOP 0x20000000
111 * The maximum PHB bus number.
112 * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
113 * x3950M2: 4 chassis, 48 PHBs per chassis = 192
114 * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
115 * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
117 #define MAX_PHB_BUS_NUM 256
119 #define PHBS_PER_CALGARY 4
121 /* register offsets in Calgary's internal register space */
122 static const unsigned long tar_offsets
[] = {
129 static const unsigned long split_queue_offsets
[] = {
130 0x4870 /* SPLIT QUEUE 0 */,
131 0x5870 /* SPLIT QUEUE 1 */,
132 0x6870 /* SPLIT QUEUE 2 */,
133 0x7870 /* SPLIT QUEUE 3 */
136 static const unsigned long phb_offsets
[] = {
143 /* PHB debug registers */
145 static const unsigned long phb_debug_offsets
[] = {
146 0x4000 /* PHB 0 DEBUG */,
147 0x5000 /* PHB 1 DEBUG */,
148 0x6000 /* PHB 2 DEBUG */,
149 0x7000 /* PHB 3 DEBUG */
153 * STUFF register for each debug PHB,
154 * byte 1 = start bus number, byte 2 = end bus number
157 #define PHB_DEBUG_STUFF_OFFSET 0x0020
159 #define EMERGENCY_PAGES 32 /* = 128KB */
161 unsigned int specified_table_size
= TCE_TABLE_SIZE_UNSPECIFIED
;
162 static int translate_empty_slots __read_mostly
= 0;
163 static int calgary_detected __read_mostly
= 0;
165 static struct rio_table_hdr
*rio_table_hdr __initdata
;
166 static struct scal_detail
*scal_devs
[MAX_NUMNODES
] __initdata
;
167 static struct rio_detail
*rio_devs
[MAX_NUMNODES
* 4] __initdata
;
169 struct calgary_bus_info
{
171 unsigned char translation_disabled
;
176 static void calgary_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
);
177 static void calgary_tce_cache_blast(struct iommu_table
*tbl
);
178 static void calgary_dump_error_regs(struct iommu_table
*tbl
);
179 static void calioc2_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
);
180 static void calioc2_tce_cache_blast(struct iommu_table
*tbl
);
181 static void calioc2_dump_error_regs(struct iommu_table
*tbl
);
182 static void calgary_init_bitmap_from_tce_table(struct iommu_table
*tbl
);
183 static void get_tce_space_from_tar(void);
185 static const struct cal_chipset_ops calgary_chip_ops
= {
186 .handle_quirks
= calgary_handle_quirks
,
187 .tce_cache_blast
= calgary_tce_cache_blast
,
188 .dump_error_regs
= calgary_dump_error_regs
191 static const struct cal_chipset_ops calioc2_chip_ops
= {
192 .handle_quirks
= calioc2_handle_quirks
,
193 .tce_cache_blast
= calioc2_tce_cache_blast
,
194 .dump_error_regs
= calioc2_dump_error_regs
197 static struct calgary_bus_info bus_info
[MAX_PHB_BUS_NUM
] = { { NULL
, 0, 0 }, };
199 static inline int translation_enabled(struct iommu_table
*tbl
)
201 /* only PHBs with translation enabled have an IOMMU table */
202 return (tbl
!= NULL
);
205 static void iommu_range_reserve(struct iommu_table
*tbl
,
206 unsigned long start_addr
, unsigned int npages
)
212 index
= start_addr
>> PAGE_SHIFT
;
214 /* bail out if we're asked to reserve a region we don't cover */
215 if (index
>= tbl
->it_size
)
218 end
= index
+ npages
;
219 if (end
> tbl
->it_size
) /* don't go off the table */
222 spin_lock_irqsave(&tbl
->it_lock
, flags
);
224 bitmap_set(tbl
->it_map
, index
, npages
);
226 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
229 static unsigned long iommu_range_alloc(struct device
*dev
,
230 struct iommu_table
*tbl
,
234 unsigned long offset
;
235 unsigned long boundary_size
;
237 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
238 PAGE_SIZE
) >> PAGE_SHIFT
;
242 spin_lock_irqsave(&tbl
->it_lock
, flags
);
244 offset
= iommu_area_alloc(tbl
->it_map
, tbl
->it_size
, tbl
->it_hint
,
245 npages
, 0, boundary_size
, 0);
246 if (offset
== ~0UL) {
247 tbl
->chip_ops
->tce_cache_blast(tbl
);
249 offset
= iommu_area_alloc(tbl
->it_map
, tbl
->it_size
, 0,
250 npages
, 0, boundary_size
, 0);
251 if (offset
== ~0UL) {
252 pr_warn("IOMMU full\n");
253 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
254 if (panic_on_overflow
)
255 panic("Calgary: fix the allocator.\n");
257 return CALGARY_MAPPING_ERROR
;
261 tbl
->it_hint
= offset
+ npages
;
262 BUG_ON(tbl
->it_hint
> tbl
->it_size
);
264 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
269 static dma_addr_t
iommu_alloc(struct device
*dev
, struct iommu_table
*tbl
,
270 void *vaddr
, unsigned int npages
, int direction
)
275 entry
= iommu_range_alloc(dev
, tbl
, npages
);
277 if (unlikely(entry
== CALGARY_MAPPING_ERROR
)) {
278 pr_warn("failed to allocate %u pages in iommu %p\n",
280 return CALGARY_MAPPING_ERROR
;
283 /* set the return dma address */
284 ret
= (entry
<< PAGE_SHIFT
) | ((unsigned long)vaddr
& ~PAGE_MASK
);
286 /* put the TCEs in the HW table */
287 tce_build(tbl
, entry
, npages
, (unsigned long)vaddr
& PAGE_MASK
,
292 static void iommu_free(struct iommu_table
*tbl
, dma_addr_t dma_addr
,
296 unsigned long badend
;
299 /* were we called with bad_dma_address? */
300 badend
= CALGARY_MAPPING_ERROR
+ (EMERGENCY_PAGES
* PAGE_SIZE
);
301 if (unlikely(dma_addr
< badend
)) {
302 WARN(1, KERN_ERR
"Calgary: driver tried unmapping bad DMA "
303 "address 0x%Lx\n", dma_addr
);
307 entry
= dma_addr
>> PAGE_SHIFT
;
309 BUG_ON(entry
+ npages
> tbl
->it_size
);
311 tce_free(tbl
, entry
, npages
);
313 spin_lock_irqsave(&tbl
->it_lock
, flags
);
315 bitmap_clear(tbl
->it_map
, entry
, npages
);
317 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
320 static inline struct iommu_table
*find_iommu_table(struct device
*dev
)
322 struct pci_dev
*pdev
;
323 struct pci_bus
*pbus
;
324 struct iommu_table
*tbl
;
326 pdev
= to_pci_dev(dev
);
328 /* search up the device tree for an iommu */
331 tbl
= pci_iommu(pbus
);
332 if (tbl
&& tbl
->it_busno
== pbus
->number
)
338 BUG_ON(tbl
&& (tbl
->it_busno
!= pbus
->number
));
343 static void calgary_unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
344 int nelems
,enum dma_data_direction dir
,
347 struct iommu_table
*tbl
= find_iommu_table(dev
);
348 struct scatterlist
*s
;
351 if (!translation_enabled(tbl
))
354 for_each_sg(sglist
, s
, nelems
, i
) {
356 dma_addr_t dma
= s
->dma_address
;
357 unsigned int dmalen
= s
->dma_length
;
362 npages
= iommu_num_pages(dma
, dmalen
, PAGE_SIZE
);
363 iommu_free(tbl
, dma
, npages
);
367 static int calgary_map_sg(struct device
*dev
, struct scatterlist
*sg
,
368 int nelems
, enum dma_data_direction dir
,
371 struct iommu_table
*tbl
= find_iommu_table(dev
);
372 struct scatterlist
*s
;
378 for_each_sg(sg
, s
, nelems
, i
) {
381 vaddr
= (unsigned long) sg_virt(s
);
382 npages
= iommu_num_pages(vaddr
, s
->length
, PAGE_SIZE
);
384 entry
= iommu_range_alloc(dev
, tbl
, npages
);
385 if (entry
== CALGARY_MAPPING_ERROR
) {
386 /* makes sure unmap knows to stop */
391 s
->dma_address
= (entry
<< PAGE_SHIFT
) | s
->offset
;
393 /* insert into HW table */
394 tce_build(tbl
, entry
, npages
, vaddr
& PAGE_MASK
, dir
);
396 s
->dma_length
= s
->length
;
401 calgary_unmap_sg(dev
, sg
, nelems
, dir
, 0);
402 for_each_sg(sg
, s
, nelems
, i
) {
403 sg
->dma_address
= CALGARY_MAPPING_ERROR
;
409 static dma_addr_t
calgary_map_page(struct device
*dev
, struct page
*page
,
410 unsigned long offset
, size_t size
,
411 enum dma_data_direction dir
,
414 void *vaddr
= page_address(page
) + offset
;
417 struct iommu_table
*tbl
= find_iommu_table(dev
);
419 uaddr
= (unsigned long)vaddr
;
420 npages
= iommu_num_pages(uaddr
, size
, PAGE_SIZE
);
422 return iommu_alloc(dev
, tbl
, vaddr
, npages
, dir
);
425 static void calgary_unmap_page(struct device
*dev
, dma_addr_t dma_addr
,
426 size_t size
, enum dma_data_direction dir
,
429 struct iommu_table
*tbl
= find_iommu_table(dev
);
432 npages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
433 iommu_free(tbl
, dma_addr
, npages
);
436 static void* calgary_alloc_coherent(struct device
*dev
, size_t size
,
437 dma_addr_t
*dma_handle
, gfp_t flag
, unsigned long attrs
)
441 unsigned int npages
, order
;
442 struct iommu_table
*tbl
= find_iommu_table(dev
);
444 size
= PAGE_ALIGN(size
); /* size rounded up to full pages */
445 npages
= size
>> PAGE_SHIFT
;
446 order
= get_order(size
);
448 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
450 /* alloc enough pages (and possibly more) */
451 ret
= (void *)__get_free_pages(flag
, order
);
454 memset(ret
, 0, size
);
456 /* set up tces to cover the allocated range */
457 mapping
= iommu_alloc(dev
, tbl
, ret
, npages
, DMA_BIDIRECTIONAL
);
458 if (mapping
== CALGARY_MAPPING_ERROR
)
460 *dma_handle
= mapping
;
463 free_pages((unsigned long)ret
, get_order(size
));
469 static void calgary_free_coherent(struct device
*dev
, size_t size
,
470 void *vaddr
, dma_addr_t dma_handle
,
474 struct iommu_table
*tbl
= find_iommu_table(dev
);
476 size
= PAGE_ALIGN(size
);
477 npages
= size
>> PAGE_SHIFT
;
479 iommu_free(tbl
, dma_handle
, npages
);
480 free_pages((unsigned long)vaddr
, get_order(size
));
483 static int calgary_mapping_error(struct device
*dev
, dma_addr_t dma_addr
)
485 return dma_addr
== CALGARY_MAPPING_ERROR
;
488 static const struct dma_map_ops calgary_dma_ops
= {
489 .alloc
= calgary_alloc_coherent
,
490 .free
= calgary_free_coherent
,
491 .map_sg
= calgary_map_sg
,
492 .unmap_sg
= calgary_unmap_sg
,
493 .map_page
= calgary_map_page
,
494 .unmap_page
= calgary_unmap_page
,
495 .mapping_error
= calgary_mapping_error
,
496 .dma_supported
= x86_dma_supported
,
499 static inline void __iomem
* busno_to_bbar(unsigned char num
)
501 return bus_info
[num
].bbar
;
504 static inline int busno_to_phbid(unsigned char num
)
506 return bus_info
[num
].phbid
;
509 static inline unsigned long split_queue_offset(unsigned char num
)
511 size_t idx
= busno_to_phbid(num
);
513 return split_queue_offsets
[idx
];
516 static inline unsigned long tar_offset(unsigned char num
)
518 size_t idx
= busno_to_phbid(num
);
520 return tar_offsets
[idx
];
523 static inline unsigned long phb_offset(unsigned char num
)
525 size_t idx
= busno_to_phbid(num
);
527 return phb_offsets
[idx
];
530 static inline void __iomem
* calgary_reg(void __iomem
*bar
, unsigned long offset
)
532 unsigned long target
= ((unsigned long)bar
) | offset
;
533 return (void __iomem
*)target
;
536 static inline int is_calioc2(unsigned short device
)
538 return (device
== PCI_DEVICE_ID_IBM_CALIOC2
);
541 static inline int is_calgary(unsigned short device
)
543 return (device
== PCI_DEVICE_ID_IBM_CALGARY
);
546 static inline int is_cal_pci_dev(unsigned short device
)
548 return (is_calgary(device
) || is_calioc2(device
));
551 static void calgary_tce_cache_blast(struct iommu_table
*tbl
)
556 void __iomem
*bbar
= tbl
->bbar
;
557 void __iomem
*target
;
559 /* disable arbitration on the bus */
560 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_AER_OFFSET
);
564 /* read plssr to ensure it got there */
565 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_PLSSR_OFFSET
);
568 /* poll split queues until all DMA activity is done */
569 target
= calgary_reg(bbar
, split_queue_offset(tbl
->it_busno
));
573 } while ((val
& 0xff) != 0xff && i
< 100);
575 pr_warn("PCI bus not quiesced, continuing anyway\n");
577 /* invalidate TCE cache */
578 target
= calgary_reg(bbar
, tar_offset(tbl
->it_busno
));
579 writeq(tbl
->tar_val
, target
);
581 /* enable arbitration */
582 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_AER_OFFSET
);
584 (void)readl(target
); /* flush */
587 static void calioc2_tce_cache_blast(struct iommu_table
*tbl
)
589 void __iomem
*bbar
= tbl
->bbar
;
590 void __iomem
*target
;
595 unsigned char bus
= tbl
->it_busno
;
598 printk(KERN_DEBUG
"Calgary: CalIOC2 bus 0x%x entering tce cache blast "
599 "sequence - count %d\n", bus
, count
);
601 /* 1. using the Page Migration Control reg set SoftStop */
602 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
603 val
= be32_to_cpu(readl(target
));
604 printk(KERN_DEBUG
"1a. read 0x%x [LE] from %p\n", val
, target
);
606 printk(KERN_DEBUG
"1b. writing 0x%x [LE] to %p\n", val
, target
);
607 writel(cpu_to_be32(val
), target
);
609 /* 2. poll split queues until all DMA activity is done */
610 printk(KERN_DEBUG
"2a. starting to poll split queues\n");
611 target
= calgary_reg(bbar
, split_queue_offset(bus
));
613 val64
= readq(target
);
615 } while ((val64
& 0xff) != 0xff && i
< 100);
617 pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n");
619 /* 3. poll Page Migration DEBUG for SoftStopFault */
620 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_DEBUG
);
621 val
= be32_to_cpu(readl(target
));
622 printk(KERN_DEBUG
"3. read 0x%x [LE] from %p\n", val
, target
);
624 /* 4. if SoftStopFault - goto (1) */
625 if (val
& PMR_SOFTSTOPFAULT
) {
629 pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n");
630 return; /* pray for the best */
634 /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
635 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
636 printk(KERN_DEBUG
"5a. slamming into HardStop by reading %p\n", target
);
637 val
= be32_to_cpu(readl(target
));
638 printk(KERN_DEBUG
"5b. read 0x%x [LE] from %p\n", val
, target
);
639 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_DEBUG
);
640 val
= be32_to_cpu(readl(target
));
641 printk(KERN_DEBUG
"5c. read 0x%x [LE] from %p (debug)\n", val
, target
);
643 /* 6. invalidate TCE cache */
644 printk(KERN_DEBUG
"6. invalidating TCE cache\n");
645 target
= calgary_reg(bbar
, tar_offset(bus
));
646 writeq(tbl
->tar_val
, target
);
648 /* 7. Re-read PMCR */
649 printk(KERN_DEBUG
"7a. Re-reading PMCR\n");
650 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
651 val
= be32_to_cpu(readl(target
));
652 printk(KERN_DEBUG
"7b. read 0x%x [LE] from %p\n", val
, target
);
654 /* 8. Remove HardStop */
655 printk(KERN_DEBUG
"8a. removing HardStop from PMCR\n");
656 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
658 printk(KERN_DEBUG
"8b. writing 0x%x [LE] to %p\n", val
, target
);
659 writel(cpu_to_be32(val
), target
);
660 val
= be32_to_cpu(readl(target
));
661 printk(KERN_DEBUG
"8c. read 0x%x [LE] from %p\n", val
, target
);
664 static void __init
calgary_reserve_mem_region(struct pci_dev
*dev
, u64 start
,
667 unsigned int numpages
;
669 limit
= limit
| 0xfffff;
672 numpages
= ((limit
- start
) >> PAGE_SHIFT
);
673 iommu_range_reserve(pci_iommu(dev
->bus
), start
, numpages
);
676 static void __init
calgary_reserve_peripheral_mem_1(struct pci_dev
*dev
)
678 void __iomem
*target
;
679 u64 low
, high
, sizelow
;
681 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
682 unsigned char busnum
= dev
->bus
->number
;
683 void __iomem
*bbar
= tbl
->bbar
;
685 /* peripheral MEM_1 region */
686 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_1_LOW
);
687 low
= be32_to_cpu(readl(target
));
688 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_1_HIGH
);
689 high
= be32_to_cpu(readl(target
));
690 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_1_SIZE
);
691 sizelow
= be32_to_cpu(readl(target
));
693 start
= (high
<< 32) | low
;
696 calgary_reserve_mem_region(dev
, start
, limit
);
699 static void __init
calgary_reserve_peripheral_mem_2(struct pci_dev
*dev
)
701 void __iomem
*target
;
703 u64 low
, high
, sizelow
, sizehigh
;
705 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
706 unsigned char busnum
= dev
->bus
->number
;
707 void __iomem
*bbar
= tbl
->bbar
;
710 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_CONFIG_RW_OFFSET
);
711 val32
= be32_to_cpu(readl(target
));
712 if (!(val32
& PHB_MEM2_ENABLE
))
715 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_LOW
);
716 low
= be32_to_cpu(readl(target
));
717 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_HIGH
);
718 high
= be32_to_cpu(readl(target
));
719 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_SIZE_LOW
);
720 sizelow
= be32_to_cpu(readl(target
));
721 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_SIZE_HIGH
);
722 sizehigh
= be32_to_cpu(readl(target
));
724 start
= (high
<< 32) | low
;
725 limit
= (sizehigh
<< 32) | sizelow
;
727 calgary_reserve_mem_region(dev
, start
, limit
);
731 * some regions of the IO address space do not get translated, so we
732 * must not give devices IO addresses in those regions. The regions
733 * are the 640KB-1MB region and the two PCI peripheral memory holes.
734 * Reserve all of them in the IOMMU bitmap to avoid giving them out
737 static void __init
calgary_reserve_regions(struct pci_dev
*dev
)
741 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
743 /* reserve EMERGENCY_PAGES from bad_dma_address and up */
744 iommu_range_reserve(tbl
, CALGARY_MAPPING_ERROR
, EMERGENCY_PAGES
);
746 /* avoid the BIOS/VGA first 640KB-1MB region */
747 /* for CalIOC2 - avoid the entire first MB */
748 if (is_calgary(dev
->device
)) {
749 start
= (640 * 1024);
750 npages
= ((1024 - 640) * 1024) >> PAGE_SHIFT
;
751 } else { /* calioc2 */
753 npages
= (1 * 1024 * 1024) >> PAGE_SHIFT
;
755 iommu_range_reserve(tbl
, start
, npages
);
757 /* reserve the two PCI peripheral memory regions in IO space */
758 calgary_reserve_peripheral_mem_1(dev
);
759 calgary_reserve_peripheral_mem_2(dev
);
762 static int __init
calgary_setup_tar(struct pci_dev
*dev
, void __iomem
*bbar
)
766 void __iomem
*target
;
768 struct iommu_table
*tbl
;
770 /* build TCE tables for each PHB */
771 ret
= build_tce_table(dev
, bbar
);
775 tbl
= pci_iommu(dev
->bus
);
776 tbl
->it_base
= (unsigned long)bus_info
[dev
->bus
->number
].tce_space
;
778 if (is_kdump_kernel())
779 calgary_init_bitmap_from_tce_table(tbl
);
781 tce_free(tbl
, 0, tbl
->it_size
);
783 if (is_calgary(dev
->device
))
784 tbl
->chip_ops
= &calgary_chip_ops
;
785 else if (is_calioc2(dev
->device
))
786 tbl
->chip_ops
= &calioc2_chip_ops
;
790 calgary_reserve_regions(dev
);
792 /* set TARs for each PHB */
793 target
= calgary_reg(bbar
, tar_offset(dev
->bus
->number
));
794 val64
= be64_to_cpu(readq(target
));
796 /* zero out all TAR bits under sw control */
797 val64
&= ~TAR_SW_BITS
;
798 table_phys
= (u64
)__pa(tbl
->it_base
);
802 BUG_ON(specified_table_size
> TCE_TABLE_SIZE_8M
);
803 val64
|= (u64
) specified_table_size
;
805 tbl
->tar_val
= cpu_to_be64(val64
);
807 writeq(tbl
->tar_val
, target
);
808 readq(target
); /* flush */
813 static void __init
calgary_free_bus(struct pci_dev
*dev
)
816 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
817 void __iomem
*target
;
818 unsigned int bitmapsz
;
820 target
= calgary_reg(tbl
->bbar
, tar_offset(dev
->bus
->number
));
821 val64
= be64_to_cpu(readq(target
));
822 val64
&= ~TAR_SW_BITS
;
823 writeq(cpu_to_be64(val64
), target
);
824 readq(target
); /* flush */
826 bitmapsz
= tbl
->it_size
/ BITS_PER_BYTE
;
827 free_pages((unsigned long)tbl
->it_map
, get_order(bitmapsz
));
832 set_pci_iommu(dev
->bus
, NULL
);
834 /* Can't free bootmem allocated memory after system is up :-( */
835 bus_info
[dev
->bus
->number
].tce_space
= NULL
;
838 static void calgary_dump_error_regs(struct iommu_table
*tbl
)
840 void __iomem
*bbar
= tbl
->bbar
;
841 void __iomem
*target
;
844 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_CSR_OFFSET
);
845 csr
= be32_to_cpu(readl(target
));
847 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_PLSSR_OFFSET
);
848 plssr
= be32_to_cpu(readl(target
));
850 /* If no error, the agent ID in the CSR is not valid */
851 pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n",
852 tbl
->it_busno
, csr
, plssr
);
855 static void calioc2_dump_error_regs(struct iommu_table
*tbl
)
857 void __iomem
*bbar
= tbl
->bbar
;
858 u32 csr
, csmr
, plssr
, mck
, rcstat
;
859 void __iomem
*target
;
860 unsigned long phboff
= phb_offset(tbl
->it_busno
);
861 unsigned long erroff
;
866 target
= calgary_reg(bbar
, phboff
| PHB_CSR_OFFSET
);
867 csr
= be32_to_cpu(readl(target
));
869 target
= calgary_reg(bbar
, phboff
| PHB_PLSSR_OFFSET
);
870 plssr
= be32_to_cpu(readl(target
));
872 target
= calgary_reg(bbar
, phboff
| 0x290);
873 csmr
= be32_to_cpu(readl(target
));
875 target
= calgary_reg(bbar
, phboff
| 0x800);
876 mck
= be32_to_cpu(readl(target
));
878 pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl
->it_busno
);
880 pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
881 csr
, plssr
, csmr
, mck
);
883 /* dump rest of error regs */
885 for (i
= 0; i
< ARRAY_SIZE(errregs
); i
++) {
886 /* err regs are at 0x810 - 0x870 */
887 erroff
= (0x810 + (i
* 0x10));
888 target
= calgary_reg(bbar
, phboff
| erroff
);
889 errregs
[i
] = be32_to_cpu(readl(target
));
890 pr_cont("0x%08x@0x%lx ", errregs
[i
], erroff
);
894 /* root complex status */
895 target
= calgary_reg(bbar
, phboff
| PHB_ROOT_COMPLEX_STATUS
);
896 rcstat
= be32_to_cpu(readl(target
));
897 printk(KERN_EMERG
"Calgary: 0x%08x@0x%x\n", rcstat
,
898 PHB_ROOT_COMPLEX_STATUS
);
901 static void calgary_watchdog(unsigned long data
)
903 struct pci_dev
*dev
= (struct pci_dev
*)data
;
904 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
905 void __iomem
*bbar
= tbl
->bbar
;
907 void __iomem
*target
;
909 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_CSR_OFFSET
);
910 val32
= be32_to_cpu(readl(target
));
912 /* If no error, the agent ID in the CSR is not valid */
913 if (val32
& CSR_AGENT_MASK
) {
914 tbl
->chip_ops
->dump_error_regs(tbl
);
919 /* Disable bus that caused the error */
920 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) |
921 PHB_CONFIG_RW_OFFSET
);
922 val32
= be32_to_cpu(readl(target
));
923 val32
|= PHB_SLOT_DISABLE
;
924 writel(cpu_to_be32(val32
), target
);
925 readl(target
); /* flush */
927 /* Reset the timer */
928 mod_timer(&tbl
->watchdog_timer
, jiffies
+ 2 * HZ
);
932 static void __init
calgary_set_split_completion_timeout(void __iomem
*bbar
,
933 unsigned char busnum
, unsigned long timeout
)
936 void __iomem
*target
;
937 unsigned int phb_shift
= ~0; /* silence gcc */
940 switch (busno_to_phbid(busnum
)) {
941 case 0: phb_shift
= (63 - 19);
943 case 1: phb_shift
= (63 - 23);
945 case 2: phb_shift
= (63 - 27);
947 case 3: phb_shift
= (63 - 35);
950 BUG_ON(busno_to_phbid(busnum
));
953 target
= calgary_reg(bbar
, CALGARY_CONFIG_REG
);
954 val64
= be64_to_cpu(readq(target
));
956 /* zero out this PHB's timer bits */
957 mask
= ~(0xFUL
<< phb_shift
);
959 val64
|= (timeout
<< phb_shift
);
960 writeq(cpu_to_be64(val64
), target
);
961 readq(target
); /* flush */
964 static void __init
calioc2_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
)
966 unsigned char busnum
= dev
->bus
->number
;
967 void __iomem
*bbar
= tbl
->bbar
;
968 void __iomem
*target
;
972 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
974 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_SAVIOR_L2
);
975 val
= cpu_to_be32(readl(target
));
977 writel(cpu_to_be32(val
), target
);
980 static void __init
calgary_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
)
982 unsigned char busnum
= dev
->bus
->number
;
985 * Give split completion a longer timeout on bus 1 for aic94xx
986 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
988 if (is_calgary(dev
->device
) && (busnum
== 1))
989 calgary_set_split_completion_timeout(tbl
->bbar
, busnum
,
993 static void __init
calgary_enable_translation(struct pci_dev
*dev
)
996 unsigned char busnum
;
997 void __iomem
*target
;
999 struct iommu_table
*tbl
;
1001 busnum
= dev
->bus
->number
;
1002 tbl
= pci_iommu(dev
->bus
);
1005 /* enable TCE in PHB Config Register */
1006 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_CONFIG_RW_OFFSET
);
1007 val32
= be32_to_cpu(readl(target
));
1008 val32
|= PHB_TCE_ENABLE
| PHB_DAC_DISABLE
| PHB_MCSR_ENABLE
;
1010 printk(KERN_INFO
"Calgary: enabling translation on %s PHB %#x\n",
1011 (dev
->device
== PCI_DEVICE_ID_IBM_CALGARY
) ?
1012 "Calgary" : "CalIOC2", busnum
);
1013 printk(KERN_INFO
"Calgary: errant DMAs will now be prevented on this "
1016 writel(cpu_to_be32(val32
), target
);
1017 readl(target
); /* flush */
1019 setup_timer(&tbl
->watchdog_timer
, &calgary_watchdog
,
1020 (unsigned long)dev
);
1021 mod_timer(&tbl
->watchdog_timer
, jiffies
);
1024 static void __init
calgary_disable_translation(struct pci_dev
*dev
)
1027 unsigned char busnum
;
1028 void __iomem
*target
;
1030 struct iommu_table
*tbl
;
1032 busnum
= dev
->bus
->number
;
1033 tbl
= pci_iommu(dev
->bus
);
1036 /* disable TCE in PHB Config Register */
1037 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_CONFIG_RW_OFFSET
);
1038 val32
= be32_to_cpu(readl(target
));
1039 val32
&= ~(PHB_TCE_ENABLE
| PHB_DAC_DISABLE
| PHB_MCSR_ENABLE
);
1041 printk(KERN_INFO
"Calgary: disabling translation on PHB %#x!\n", busnum
);
1042 writel(cpu_to_be32(val32
), target
);
1043 readl(target
); /* flush */
1045 del_timer_sync(&tbl
->watchdog_timer
);
1048 static void __init
calgary_init_one_nontraslated(struct pci_dev
*dev
)
1051 set_pci_iommu(dev
->bus
, NULL
);
1053 /* is the device behind a bridge? */
1054 if (dev
->bus
->parent
)
1055 dev
->bus
->parent
->self
= dev
;
1057 dev
->bus
->self
= dev
;
1060 static int __init
calgary_init_one(struct pci_dev
*dev
)
1063 struct iommu_table
*tbl
;
1066 bbar
= busno_to_bbar(dev
->bus
->number
);
1067 ret
= calgary_setup_tar(dev
, bbar
);
1073 if (dev
->bus
->parent
) {
1074 if (dev
->bus
->parent
->self
)
1075 printk(KERN_WARNING
"Calgary: IEEEE, dev %p has "
1076 "bus->parent->self!\n", dev
);
1077 dev
->bus
->parent
->self
= dev
;
1079 dev
->bus
->self
= dev
;
1081 tbl
= pci_iommu(dev
->bus
);
1082 tbl
->chip_ops
->handle_quirks(tbl
, dev
);
1084 calgary_enable_translation(dev
);
1092 static int __init
calgary_locate_bbars(void)
1095 int rioidx
, phb
, bus
;
1097 void __iomem
*target
;
1098 unsigned long offset
;
1099 u8 start_bus
, end_bus
;
1103 for (rioidx
= 0; rioidx
< rio_table_hdr
->num_rio_dev
; rioidx
++) {
1104 struct rio_detail
*rio
= rio_devs
[rioidx
];
1106 if ((rio
->type
!= COMPAT_CALGARY
) && (rio
->type
!= ALT_CALGARY
))
1109 /* map entire 1MB of Calgary config space */
1110 bbar
= ioremap_nocache(rio
->BBAR
, 1024 * 1024);
1114 for (phb
= 0; phb
< PHBS_PER_CALGARY
; phb
++) {
1115 offset
= phb_debug_offsets
[phb
] | PHB_DEBUG_STUFF_OFFSET
;
1116 target
= calgary_reg(bbar
, offset
);
1118 val
= be32_to_cpu(readl(target
));
1120 start_bus
= (u8
)((val
& 0x00FF0000) >> 16);
1121 end_bus
= (u8
)((val
& 0x0000FF00) >> 8);
1124 for (bus
= start_bus
; bus
<= end_bus
; bus
++) {
1125 bus_info
[bus
].bbar
= bbar
;
1126 bus_info
[bus
].phbid
= phb
;
1129 bus_info
[start_bus
].bbar
= bbar
;
1130 bus_info
[start_bus
].phbid
= phb
;
1138 /* scan bus_info and iounmap any bbars we previously ioremap'd */
1139 for (bus
= 0; bus
< ARRAY_SIZE(bus_info
); bus
++)
1140 if (bus_info
[bus
].bbar
)
1141 iounmap(bus_info
[bus
].bbar
);
1146 static int __init
calgary_init(void)
1149 struct pci_dev
*dev
= NULL
;
1150 struct calgary_bus_info
*info
;
1152 ret
= calgary_locate_bbars();
1156 /* Purely for kdump kernel case */
1157 if (is_kdump_kernel())
1158 get_tce_space_from_tar();
1161 dev
= pci_get_device(PCI_VENDOR_ID_IBM
, PCI_ANY_ID
, dev
);
1164 if (!is_cal_pci_dev(dev
->device
))
1167 info
= &bus_info
[dev
->bus
->number
];
1168 if (info
->translation_disabled
) {
1169 calgary_init_one_nontraslated(dev
);
1173 if (!info
->tce_space
&& !translate_empty_slots
)
1176 ret
= calgary_init_one(dev
);
1182 for_each_pci_dev(dev
) {
1183 struct iommu_table
*tbl
;
1185 tbl
= find_iommu_table(&dev
->dev
);
1187 if (translation_enabled(tbl
))
1188 dev
->dev
.dma_ops
= &calgary_dma_ops
;
1195 dev
= pci_get_device(PCI_VENDOR_ID_IBM
, PCI_ANY_ID
, dev
);
1198 if (!is_cal_pci_dev(dev
->device
))
1201 info
= &bus_info
[dev
->bus
->number
];
1202 if (info
->translation_disabled
) {
1206 if (!info
->tce_space
&& !translate_empty_slots
)
1209 calgary_disable_translation(dev
);
1210 calgary_free_bus(dev
);
1211 pci_dev_put(dev
); /* Undo calgary_init_one()'s pci_dev_get() */
1212 dev
->dev
.dma_ops
= NULL
;
1218 static inline int __init
determine_tce_table_size(void)
1222 if (specified_table_size
!= TCE_TABLE_SIZE_UNSPECIFIED
)
1223 return specified_table_size
;
1225 if (is_kdump_kernel() && saved_max_pfn
) {
1227 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1228 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1229 * larger table size has twice as many entries, so shift the
1230 * max ram address by 13 to divide by 8K and then look at the
1231 * order of the result to choose between 0-7.
1233 ret
= get_order((saved_max_pfn
* PAGE_SIZE
) >> 13);
1234 if (ret
> TCE_TABLE_SIZE_8M
)
1235 ret
= TCE_TABLE_SIZE_8M
;
1238 * Use 8M by default (suggested by Muli) if it's not
1239 * kdump kernel and saved_max_pfn isn't set.
1241 ret
= TCE_TABLE_SIZE_8M
;
1247 static int __init
build_detail_arrays(void)
1250 unsigned numnodes
, i
;
1251 int scal_detail_size
, rio_detail_size
;
1253 numnodes
= rio_table_hdr
->num_scal_dev
;
1254 if (numnodes
> MAX_NUMNODES
){
1256 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1257 "but system has %d nodes.\n",
1258 MAX_NUMNODES
, numnodes
);
1262 switch (rio_table_hdr
->version
){
1264 scal_detail_size
= 11;
1265 rio_detail_size
= 13;
1268 scal_detail_size
= 12;
1269 rio_detail_size
= 15;
1273 "Calgary: Invalid Rio Grande Table Version: %d\n",
1274 rio_table_hdr
->version
);
1278 ptr
= ((unsigned long)rio_table_hdr
) + 3;
1279 for (i
= 0; i
< numnodes
; i
++, ptr
+= scal_detail_size
)
1280 scal_devs
[i
] = (struct scal_detail
*)ptr
;
1282 for (i
= 0; i
< rio_table_hdr
->num_rio_dev
;
1283 i
++, ptr
+= rio_detail_size
)
1284 rio_devs
[i
] = (struct rio_detail
*)ptr
;
1289 static int __init
calgary_bus_has_devices(int bus
, unsigned short pci_dev
)
1294 if (pci_dev
== PCI_DEVICE_ID_IBM_CALIOC2
) {
1296 * FIXME: properly scan for devices across the
1297 * PCI-to-PCI bridge on every CalIOC2 port.
1302 for (dev
= 1; dev
< 8; dev
++) {
1303 val
= read_pci_config(bus
, dev
, 0, 0);
1304 if (val
!= 0xffffffff)
1307 return (val
!= 0xffffffff);
1311 * calgary_init_bitmap_from_tce_table():
1312 * Function for kdump case. In the second/kdump kernel initialize
1313 * the bitmap based on the tce table entries obtained from first kernel
1315 static void calgary_init_bitmap_from_tce_table(struct iommu_table
*tbl
)
1319 tp
= ((u64
*)tbl
->it_base
);
1320 for (index
= 0 ; index
< tbl
->it_size
; index
++) {
1322 set_bit(index
, tbl
->it_map
);
1328 * get_tce_space_from_tar():
1329 * Function for kdump case. Get the tce tables from first kernel
1330 * by reading the contents of the base address register of calgary iommu
1332 static void __init
get_tce_space_from_tar(void)
1335 void __iomem
*target
;
1336 unsigned long tce_space
;
1338 for (bus
= 0; bus
< MAX_PHB_BUS_NUM
; bus
++) {
1339 struct calgary_bus_info
*info
= &bus_info
[bus
];
1340 unsigned short pci_device
;
1343 val
= read_pci_config(bus
, 0, 0, 0);
1344 pci_device
= (val
& 0xFFFF0000) >> 16;
1346 if (!is_cal_pci_dev(pci_device
))
1348 if (info
->translation_disabled
)
1351 if (calgary_bus_has_devices(bus
, pci_device
) ||
1352 translate_empty_slots
) {
1353 target
= calgary_reg(bus_info
[bus
].bbar
,
1355 tce_space
= be64_to_cpu(readq(target
));
1356 tce_space
= tce_space
& TAR_SW_BITS
;
1358 tce_space
= tce_space
& (~specified_table_size
);
1359 info
->tce_space
= (u64
*)__va(tce_space
);
1365 static int __init
calgary_iommu_init(void)
1369 /* ok, we're trying to use Calgary - let's roll */
1370 printk(KERN_INFO
"PCI-DMA: Using Calgary IOMMU\n");
1372 ret
= calgary_init();
1374 printk(KERN_ERR
"PCI-DMA: Calgary init failed %d, "
1375 "falling back to no_iommu\n", ret
);
1382 int __init
detect_calgary(void)
1386 int calgary_found
= 0;
1388 unsigned int offset
, prev_offset
;
1392 * if the user specified iommu=off or iommu=soft or we found
1393 * another HW IOMMU already, bail out.
1395 if (no_iommu
|| iommu_detected
)
1401 if (!early_pci_allowed())
1404 printk(KERN_DEBUG
"Calgary: detecting Calgary via BIOS EBDA area\n");
1406 ptr
= (unsigned long)phys_to_virt(get_bios_ebda());
1408 rio_table_hdr
= NULL
;
1412 * The next offset is stored in the 1st word.
1413 * Only parse up until the offset increases:
1415 while (offset
> prev_offset
) {
1416 /* The block id is stored in the 2nd word */
1417 if (*((unsigned short *)(ptr
+ offset
+ 2)) == 0x4752){
1418 /* set the pointer past the offset & block id */
1419 rio_table_hdr
= (struct rio_table_hdr
*)(ptr
+ offset
+ 4);
1422 prev_offset
= offset
;
1423 offset
= *((unsigned short *)(ptr
+ offset
));
1425 if (!rio_table_hdr
) {
1426 printk(KERN_DEBUG
"Calgary: Unable to locate Rio Grande table "
1427 "in EBDA - bailing!\n");
1431 ret
= build_detail_arrays();
1433 printk(KERN_DEBUG
"Calgary: build_detail_arrays ret %d\n", ret
);
1437 specified_table_size
= determine_tce_table_size();
1439 for (bus
= 0; bus
< MAX_PHB_BUS_NUM
; bus
++) {
1440 struct calgary_bus_info
*info
= &bus_info
[bus
];
1441 unsigned short pci_device
;
1444 val
= read_pci_config(bus
, 0, 0, 0);
1445 pci_device
= (val
& 0xFFFF0000) >> 16;
1447 if (!is_cal_pci_dev(pci_device
))
1450 if (info
->translation_disabled
)
1453 if (calgary_bus_has_devices(bus
, pci_device
) ||
1454 translate_empty_slots
) {
1456 * If it is kdump kernel, find and use tce tables
1457 * from first kernel, else allocate tce tables here
1459 if (!is_kdump_kernel()) {
1460 tbl
= alloc_tce_table();
1463 info
->tce_space
= tbl
;
1469 printk(KERN_DEBUG
"Calgary: finished detection, Calgary %s\n",
1470 calgary_found
? "found" : "not found");
1472 if (calgary_found
) {
1474 calgary_detected
= 1;
1475 printk(KERN_INFO
"PCI-DMA: Calgary IOMMU detected.\n");
1476 printk(KERN_INFO
"PCI-DMA: Calgary TCE table spec is %d\n",
1477 specified_table_size
);
1479 x86_init
.iommu
.iommu_init
= calgary_iommu_init
;
1481 return calgary_found
;
1484 for (--bus
; bus
>= 0; --bus
) {
1485 struct calgary_bus_info
*info
= &bus_info
[bus
];
1487 if (info
->tce_space
)
1488 free_tce_table(info
->tce_space
);
1493 static int __init
calgary_parse_options(char *p
)
1495 unsigned int bridge
;
1501 if (!strncmp(p
, "64k", 3))
1502 specified_table_size
= TCE_TABLE_SIZE_64K
;
1503 else if (!strncmp(p
, "128k", 4))
1504 specified_table_size
= TCE_TABLE_SIZE_128K
;
1505 else if (!strncmp(p
, "256k", 4))
1506 specified_table_size
= TCE_TABLE_SIZE_256K
;
1507 else if (!strncmp(p
, "512k", 4))
1508 specified_table_size
= TCE_TABLE_SIZE_512K
;
1509 else if (!strncmp(p
, "1M", 2))
1510 specified_table_size
= TCE_TABLE_SIZE_1M
;
1511 else if (!strncmp(p
, "2M", 2))
1512 specified_table_size
= TCE_TABLE_SIZE_2M
;
1513 else if (!strncmp(p
, "4M", 2))
1514 specified_table_size
= TCE_TABLE_SIZE_4M
;
1515 else if (!strncmp(p
, "8M", 2))
1516 specified_table_size
= TCE_TABLE_SIZE_8M
;
1518 len
= strlen("translate_empty_slots");
1519 if (!strncmp(p
, "translate_empty_slots", len
))
1520 translate_empty_slots
= 1;
1522 len
= strlen("disable");
1523 if (!strncmp(p
, "disable", len
)) {
1529 ret
= kstrtoul(p
, 0, &val
);
1534 if (bridge
< MAX_PHB_BUS_NUM
) {
1535 printk(KERN_INFO
"Calgary: disabling "
1536 "translation for PHB %#x\n", bridge
);
1537 bus_info
[bridge
].translation_disabled
= 1;
1541 p
= strpbrk(p
, ",");
1549 __setup("calgary=", calgary_parse_options
);
1551 static void __init
calgary_fixup_one_tce_space(struct pci_dev
*dev
)
1553 struct iommu_table
*tbl
;
1554 unsigned int npages
;
1557 tbl
= pci_iommu(dev
->bus
);
1559 for (i
= 0; i
< 4; i
++) {
1560 struct resource
*r
= &dev
->resource
[PCI_BRIDGE_RESOURCES
+ i
];
1562 /* Don't give out TCEs that map MEM resources */
1563 if (!(r
->flags
& IORESOURCE_MEM
))
1566 /* 0-based? we reserve the whole 1st MB anyway */
1570 /* cover the whole region */
1571 npages
= resource_size(r
) >> PAGE_SHIFT
;
1574 iommu_range_reserve(tbl
, r
->start
, npages
);
1578 static int __init
calgary_fixup_tce_spaces(void)
1580 struct pci_dev
*dev
= NULL
;
1581 struct calgary_bus_info
*info
;
1583 if (no_iommu
|| swiotlb
|| !calgary_detected
)
1586 printk(KERN_DEBUG
"Calgary: fixing up tce spaces\n");
1589 dev
= pci_get_device(PCI_VENDOR_ID_IBM
, PCI_ANY_ID
, dev
);
1592 if (!is_cal_pci_dev(dev
->device
))
1595 info
= &bus_info
[dev
->bus
->number
];
1596 if (info
->translation_disabled
)
1599 if (!info
->tce_space
)
1602 calgary_fixup_one_tce_space(dev
);
1610 * We need to be call after pcibios_assign_resources (fs_initcall level)
1611 * and before device_initcall.
1613 rootfs_initcall(calgary_fixup_tce_spaces
);
1615 IOMMU_INIT_POST(detect_calgary
);