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x86, cpu: Clean up AMD erratum 400 workaround
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1 #include <linux/errno.h>
2 #include <linux/kernel.h>
3 #include <linux/mm.h>
4 #include <linux/smp.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
9 #include <linux/pm.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <linux/user-return-notifier.h>
13 #include <linux/dmi.h>
14 #include <linux/utsname.h>
15 #include <trace/events/power.h>
16 #include <linux/hw_breakpoint.h>
17 #include <asm/system.h>
18 #include <asm/apic.h>
19 #include <asm/syscalls.h>
20 #include <asm/idle.h>
21 #include <asm/uaccess.h>
22 #include <asm/i387.h>
23 #include <asm/debugreg.h>
24
25 unsigned long idle_halt;
26 EXPORT_SYMBOL(idle_halt);
27 unsigned long idle_nomwait;
28 EXPORT_SYMBOL(idle_nomwait);
29
30 struct kmem_cache *task_xstate_cachep;
31
32 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
33 {
34 int ret;
35
36 *dst = *src;
37 if (fpu_allocated(&src->thread.fpu)) {
38 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
39 ret = fpu_alloc(&dst->thread.fpu);
40 if (ret)
41 return ret;
42 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
43 }
44 return 0;
45 }
46
47 void free_thread_xstate(struct task_struct *tsk)
48 {
49 fpu_free(&tsk->thread.fpu);
50 }
51
52 void free_thread_info(struct thread_info *ti)
53 {
54 free_thread_xstate(ti->task);
55 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
56 }
57
58 void arch_task_cache_init(void)
59 {
60 task_xstate_cachep =
61 kmem_cache_create("task_xstate", xstate_size,
62 __alignof__(union thread_xstate),
63 SLAB_PANIC | SLAB_NOTRACK, NULL);
64 }
65
66 /*
67 * Free current thread data structures etc..
68 */
69 void exit_thread(void)
70 {
71 struct task_struct *me = current;
72 struct thread_struct *t = &me->thread;
73 unsigned long *bp = t->io_bitmap_ptr;
74
75 if (bp) {
76 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
77
78 t->io_bitmap_ptr = NULL;
79 clear_thread_flag(TIF_IO_BITMAP);
80 /*
81 * Careful, clear this in the TSS too:
82 */
83 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
84 t->io_bitmap_max = 0;
85 put_cpu();
86 kfree(bp);
87 }
88 }
89
90 void show_regs(struct pt_regs *regs)
91 {
92 show_registers(regs);
93 show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs),
94 regs->bp);
95 }
96
97 void show_regs_common(void)
98 {
99 const char *board, *product;
100
101 board = dmi_get_system_info(DMI_BOARD_NAME);
102 if (!board)
103 board = "";
104 product = dmi_get_system_info(DMI_PRODUCT_NAME);
105 if (!product)
106 product = "";
107
108 printk(KERN_CONT "\n");
109 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
110 current->pid, current->comm, print_tainted(),
111 init_utsname()->release,
112 (int)strcspn(init_utsname()->version, " "),
113 init_utsname()->version, board, product);
114 }
115
116 void flush_thread(void)
117 {
118 struct task_struct *tsk = current;
119
120 flush_ptrace_hw_breakpoint(tsk);
121 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
122 /*
123 * Forget coprocessor state..
124 */
125 tsk->fpu_counter = 0;
126 clear_fpu(tsk);
127 clear_used_math();
128 }
129
130 static void hard_disable_TSC(void)
131 {
132 write_cr4(read_cr4() | X86_CR4_TSD);
133 }
134
135 void disable_TSC(void)
136 {
137 preempt_disable();
138 if (!test_and_set_thread_flag(TIF_NOTSC))
139 /*
140 * Must flip the CPU state synchronously with
141 * TIF_NOTSC in the current running context.
142 */
143 hard_disable_TSC();
144 preempt_enable();
145 }
146
147 static void hard_enable_TSC(void)
148 {
149 write_cr4(read_cr4() & ~X86_CR4_TSD);
150 }
151
152 static void enable_TSC(void)
153 {
154 preempt_disable();
155 if (test_and_clear_thread_flag(TIF_NOTSC))
156 /*
157 * Must flip the CPU state synchronously with
158 * TIF_NOTSC in the current running context.
159 */
160 hard_enable_TSC();
161 preempt_enable();
162 }
163
164 int get_tsc_mode(unsigned long adr)
165 {
166 unsigned int val;
167
168 if (test_thread_flag(TIF_NOTSC))
169 val = PR_TSC_SIGSEGV;
170 else
171 val = PR_TSC_ENABLE;
172
173 return put_user(val, (unsigned int __user *)adr);
174 }
175
176 int set_tsc_mode(unsigned int val)
177 {
178 if (val == PR_TSC_SIGSEGV)
179 disable_TSC();
180 else if (val == PR_TSC_ENABLE)
181 enable_TSC();
182 else
183 return -EINVAL;
184
185 return 0;
186 }
187
188 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
189 struct tss_struct *tss)
190 {
191 struct thread_struct *prev, *next;
192
193 prev = &prev_p->thread;
194 next = &next_p->thread;
195
196 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
197 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
198 unsigned long debugctl = get_debugctlmsr();
199
200 debugctl &= ~DEBUGCTLMSR_BTF;
201 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
202 debugctl |= DEBUGCTLMSR_BTF;
203
204 update_debugctlmsr(debugctl);
205 }
206
207 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
208 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
209 /* prev and next are different */
210 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
211 hard_disable_TSC();
212 else
213 hard_enable_TSC();
214 }
215
216 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
217 /*
218 * Copy the relevant range of the IO bitmap.
219 * Normally this is 128 bytes or less:
220 */
221 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
222 max(prev->io_bitmap_max, next->io_bitmap_max));
223 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
224 /*
225 * Clear any possible leftover bits:
226 */
227 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
228 }
229 propagate_user_return_notify(prev_p, next_p);
230 }
231
232 int sys_fork(struct pt_regs *regs)
233 {
234 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
235 }
236
237 /*
238 * This is trivial, and on the face of it looks like it
239 * could equally well be done in user mode.
240 *
241 * Not so, for quite unobvious reasons - register pressure.
242 * In user mode vfork() cannot have a stack frame, and if
243 * done by calling the "clone()" system call directly, you
244 * do not have enough call-clobbered registers to hold all
245 * the information you need.
246 */
247 int sys_vfork(struct pt_regs *regs)
248 {
249 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
250 NULL, NULL);
251 }
252
253 long
254 sys_clone(unsigned long clone_flags, unsigned long newsp,
255 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
256 {
257 if (!newsp)
258 newsp = regs->sp;
259 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
260 }
261
262 /*
263 * This gets run with %si containing the
264 * function to call, and %di containing
265 * the "args".
266 */
267 extern void kernel_thread_helper(void);
268
269 /*
270 * Create a kernel thread
271 */
272 int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
273 {
274 struct pt_regs regs;
275
276 memset(&regs, 0, sizeof(regs));
277
278 regs.si = (unsigned long) fn;
279 regs.di = (unsigned long) arg;
280
281 #ifdef CONFIG_X86_32
282 regs.ds = __USER_DS;
283 regs.es = __USER_DS;
284 regs.fs = __KERNEL_PERCPU;
285 regs.gs = __KERNEL_STACK_CANARY;
286 #else
287 regs.ss = __KERNEL_DS;
288 #endif
289
290 regs.orig_ax = -1;
291 regs.ip = (unsigned long) kernel_thread_helper;
292 regs.cs = __KERNEL_CS | get_kernel_rpl();
293 regs.flags = X86_EFLAGS_IF | 0x2;
294
295 /* Ok, create the new process.. */
296 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
297 }
298 EXPORT_SYMBOL(kernel_thread);
299
300 /*
301 * sys_execve() executes a new program.
302 */
303 long sys_execve(char __user *name, char __user * __user *argv,
304 char __user * __user *envp, struct pt_regs *regs)
305 {
306 long error;
307 char *filename;
308
309 filename = getname(name);
310 error = PTR_ERR(filename);
311 if (IS_ERR(filename))
312 return error;
313 error = do_execve(filename, argv, envp, regs);
314
315 #ifdef CONFIG_X86_32
316 if (error == 0) {
317 /* Make sure we don't return using sysenter.. */
318 set_thread_flag(TIF_IRET);
319 }
320 #endif
321
322 putname(filename);
323 return error;
324 }
325
326 /*
327 * Idle related variables and functions
328 */
329 unsigned long boot_option_idle_override = 0;
330 EXPORT_SYMBOL(boot_option_idle_override);
331
332 /*
333 * Powermanagement idle function, if any..
334 */
335 void (*pm_idle)(void);
336 EXPORT_SYMBOL(pm_idle);
337
338 #ifdef CONFIG_X86_32
339 /*
340 * This halt magic was a workaround for ancient floppy DMA
341 * wreckage. It should be safe to remove.
342 */
343 static int hlt_counter;
344 void disable_hlt(void)
345 {
346 hlt_counter++;
347 }
348 EXPORT_SYMBOL(disable_hlt);
349
350 void enable_hlt(void)
351 {
352 hlt_counter--;
353 }
354 EXPORT_SYMBOL(enable_hlt);
355
356 static inline int hlt_use_halt(void)
357 {
358 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
359 }
360 #else
361 static inline int hlt_use_halt(void)
362 {
363 return 1;
364 }
365 #endif
366
367 /*
368 * We use this if we don't have any better
369 * idle routine..
370 */
371 void default_idle(void)
372 {
373 if (hlt_use_halt()) {
374 trace_power_start(POWER_CSTATE, 1);
375 current_thread_info()->status &= ~TS_POLLING;
376 /*
377 * TS_POLLING-cleared state must be visible before we
378 * test NEED_RESCHED:
379 */
380 smp_mb();
381
382 if (!need_resched())
383 safe_halt(); /* enables interrupts racelessly */
384 else
385 local_irq_enable();
386 current_thread_info()->status |= TS_POLLING;
387 } else {
388 local_irq_enable();
389 /* loop is done by the caller */
390 cpu_relax();
391 }
392 }
393 #ifdef CONFIG_APM_MODULE
394 EXPORT_SYMBOL(default_idle);
395 #endif
396
397 void stop_this_cpu(void *dummy)
398 {
399 local_irq_disable();
400 /*
401 * Remove this CPU:
402 */
403 set_cpu_online(smp_processor_id(), false);
404 disable_local_APIC();
405
406 for (;;) {
407 if (hlt_works(smp_processor_id()))
408 halt();
409 }
410 }
411
412 static void do_nothing(void *unused)
413 {
414 }
415
416 /*
417 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
418 * pm_idle and update to new pm_idle value. Required while changing pm_idle
419 * handler on SMP systems.
420 *
421 * Caller must have changed pm_idle to the new value before the call. Old
422 * pm_idle value will not be used by any CPU after the return of this function.
423 */
424 void cpu_idle_wait(void)
425 {
426 smp_mb();
427 /* kick all the CPUs so that they exit out of pm_idle */
428 smp_call_function(do_nothing, NULL, 1);
429 }
430 EXPORT_SYMBOL_GPL(cpu_idle_wait);
431
432 /*
433 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
434 * which can obviate IPI to trigger checking of need_resched.
435 * We execute MONITOR against need_resched and enter optimized wait state
436 * through MWAIT. Whenever someone changes need_resched, we would be woken
437 * up from MWAIT (without an IPI).
438 *
439 * New with Core Duo processors, MWAIT can take some hints based on CPU
440 * capability.
441 */
442 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
443 {
444 trace_power_start(POWER_CSTATE, (ax>>4)+1);
445 if (!need_resched()) {
446 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
447 clflush((void *)&current_thread_info()->flags);
448
449 __monitor((void *)&current_thread_info()->flags, 0, 0);
450 smp_mb();
451 if (!need_resched())
452 __mwait(ax, cx);
453 }
454 }
455
456 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
457 static void mwait_idle(void)
458 {
459 if (!need_resched()) {
460 trace_power_start(POWER_CSTATE, 1);
461 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
462 clflush((void *)&current_thread_info()->flags);
463
464 __monitor((void *)&current_thread_info()->flags, 0, 0);
465 smp_mb();
466 if (!need_resched())
467 __sti_mwait(0, 0);
468 else
469 local_irq_enable();
470 } else
471 local_irq_enable();
472 }
473
474 /*
475 * On SMP it's slightly faster (but much more power-consuming!)
476 * to poll the ->work.need_resched flag instead of waiting for the
477 * cross-CPU IPI to arrive. Use this option with caution.
478 */
479 static void poll_idle(void)
480 {
481 trace_power_start(POWER_CSTATE, 0);
482 local_irq_enable();
483 while (!need_resched())
484 cpu_relax();
485 trace_power_end(0);
486 }
487
488 /*
489 * mwait selection logic:
490 *
491 * It depends on the CPU. For AMD CPUs that support MWAIT this is
492 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
493 * then depend on a clock divisor and current Pstate of the core. If
494 * all cores of a processor are in halt state (C1) the processor can
495 * enter the C1E (C1 enhanced) state. If mwait is used this will never
496 * happen.
497 *
498 * idle=mwait overrides this decision and forces the usage of mwait.
499 */
500 static int __cpuinitdata force_mwait;
501
502 #define MWAIT_INFO 0x05
503 #define MWAIT_ECX_EXTENDED_INFO 0x01
504 #define MWAIT_EDX_C1 0xf0
505
506 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
507 {
508 u32 eax, ebx, ecx, edx;
509
510 if (force_mwait)
511 return 1;
512
513 if (c->cpuid_level < MWAIT_INFO)
514 return 0;
515
516 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
517 /* Check, whether EDX has extended info about MWAIT */
518 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
519 return 1;
520
521 /*
522 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
523 * C1 supports MWAIT
524 */
525 return (edx & MWAIT_EDX_C1);
526 }
527
528 static cpumask_var_t c1e_mask;
529 static int c1e_detected;
530
531 void c1e_remove_cpu(int cpu)
532 {
533 if (c1e_mask != NULL)
534 cpumask_clear_cpu(cpu, c1e_mask);
535 }
536
537 /*
538 * C1E aware idle routine. We check for C1E active in the interrupt
539 * pending message MSR. If we detect C1E, then we handle it the same
540 * way as C3 power states (local apic timer and TSC stop)
541 */
542 static void c1e_idle(void)
543 {
544 if (need_resched())
545 return;
546
547 if (!c1e_detected) {
548 u32 lo, hi;
549
550 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
551 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
552 c1e_detected = 1;
553 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
554 mark_tsc_unstable("TSC halt in AMD C1E");
555 printk(KERN_INFO "System has AMD C1E enabled\n");
556 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
557 }
558 }
559
560 if (c1e_detected) {
561 int cpu = smp_processor_id();
562
563 if (!cpumask_test_cpu(cpu, c1e_mask)) {
564 cpumask_set_cpu(cpu, c1e_mask);
565 /*
566 * Force broadcast so ACPI can not interfere.
567 */
568 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
569 &cpu);
570 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
571 cpu);
572 }
573 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
574
575 default_idle();
576
577 /*
578 * The switch back from broadcast mode needs to be
579 * called with interrupts disabled.
580 */
581 local_irq_disable();
582 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
583 local_irq_enable();
584 } else
585 default_idle();
586 }
587
588 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
589 {
590 #ifdef CONFIG_SMP
591 if (pm_idle == poll_idle && smp_num_siblings > 1) {
592 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
593 " performance may degrade.\n");
594 }
595 #endif
596 if (pm_idle)
597 return;
598
599 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
600 /*
601 * One CPU supports mwait => All CPUs supports mwait
602 */
603 printk(KERN_INFO "using mwait in idle threads.\n");
604 pm_idle = mwait_idle;
605 } else if (cpu_has_amd_erratum(amd_erratum_400)) {
606 /* E400: APIC timer interrupt does not wake up CPU from C1e */
607 printk(KERN_INFO "using C1E aware idle routine\n");
608 pm_idle = c1e_idle;
609 } else
610 pm_idle = default_idle;
611 }
612
613 void __init init_c1e_mask(void)
614 {
615 /* If we're using c1e_idle, we need to allocate c1e_mask. */
616 if (pm_idle == c1e_idle)
617 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
618 }
619
620 static int __init idle_setup(char *str)
621 {
622 if (!str)
623 return -EINVAL;
624
625 if (!strcmp(str, "poll")) {
626 printk("using polling idle threads.\n");
627 pm_idle = poll_idle;
628 } else if (!strcmp(str, "mwait"))
629 force_mwait = 1;
630 else if (!strcmp(str, "halt")) {
631 /*
632 * When the boot option of idle=halt is added, halt is
633 * forced to be used for CPU idle. In such case CPU C2/C3
634 * won't be used again.
635 * To continue to load the CPU idle driver, don't touch
636 * the boot_option_idle_override.
637 */
638 pm_idle = default_idle;
639 idle_halt = 1;
640 return 0;
641 } else if (!strcmp(str, "nomwait")) {
642 /*
643 * If the boot option of "idle=nomwait" is added,
644 * it means that mwait will be disabled for CPU C2/C3
645 * states. In such case it won't touch the variable
646 * of boot_option_idle_override.
647 */
648 idle_nomwait = 1;
649 return 0;
650 } else
651 return -1;
652
653 boot_option_idle_override = 1;
654 return 0;
655 }
656 early_param("idle", idle_setup);
657
658 unsigned long arch_align_stack(unsigned long sp)
659 {
660 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
661 sp -= get_random_int() % 8192;
662 return sp & ~0xf;
663 }
664
665 unsigned long arch_randomize_brk(struct mm_struct *mm)
666 {
667 unsigned long range_end = mm->brk + 0x02000000;
668 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
669 }
670