arch/x86/kernel/process.c

   1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   2
   3 #include <linux/errno.h>
   4 #include <linux/kernel.h>
   5 #include <linux/mm.h>
   6 #include <linux/smp.h>
   7 #include <linux/prctl.h>
   8 #include <linux/slab.h>
   9 #include <linux/sched.h>
  10 #include <linux/sched/idle.h>
  11 #include <linux/sched/debug.h>
  12 #include <linux/sched/task.h>
  13 #include <linux/sched/task_stack.h>
  14 #include <linux/init.h>
  15 #include <linux/export.h>
  16 #include <linux/pm.h>
  17 #include <linux/tick.h>
  18 #include <linux/random.h>
  19 #include <linux/user-return-notifier.h>
  20 #include <linux/dmi.h>
  21 #include <linux/utsname.h>
  22 #include <linux/stackprotector.h>
  23 #include <linux/tick.h>
  24 #include <linux/cpuidle.h>
  25 #include <trace/events/power.h>
  26 #include <linux/hw_breakpoint.h>
  27 #include <asm/cpu.h>
  28 #include <asm/apic.h>
  29 #include <asm/syscalls.h>
  30 #include <linux/uaccess.h>
  31 #include <asm/mwait.h>
  32 #include <asm/fpu/internal.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/nmi.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/mce.h>
  37 #include <asm/vm86.h>
  38 #include <asm/switch_to.h>
  39 #include <asm/desc.h>
  40 #include <asm/prctl.h>
  41
  42 /*
  43  * per-CPU TSS segments. Threads are completely 'soft' on Linux,
  44  * no more per-task TSS's. The TSS size is kept cacheline-aligned
  45  * so they are allowed to end up in the .data..cacheline_aligned
  46  * section. Since TSS's are completely CPU-local, we want them
  47  * on exact cacheline boundaries, to eliminate cacheline ping-pong.
  48  */
  49 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
  50         .x86_tss = {
  51                 /*
  52                  * .sp0 is only used when entering ring 0 from a lower
  53                  * privilege level.  Since the init task never runs anything
  54                  * but ring 0 code, there is no need for a valid value here.
  55                  * Poison it.
  56                  */
  57                 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
  58 #ifdef CONFIG_X86_32
  59                 .ss0 = __KERNEL_DS,
  60                 .ss1 = __KERNEL_CS,
  61                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
  62 #endif
  63          },
  64 #ifdef CONFIG_X86_32
  65          /*
  66           * Note that the .io_bitmap member must be extra-big. This is because
  67           * the CPU will access an additional byte beyond the end of the IO
  68           * permission bitmap. The extra byte must be all 1 bits, and must
  69           * be within the limit.
  70           */
  71         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },
  72 #endif
  73 #ifdef CONFIG_X86_32
  74         .SYSENTER_stack_canary  = STACK_END_MAGIC,
  75 #endif
  76 };
  77 EXPORT_PER_CPU_SYMBOL(cpu_tss);
  78
  79 DEFINE_PER_CPU(bool, __tss_limit_invalid);
  80 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
  81
  82 /*
  83  * this gets called so that we can store lazy state into memory and copy the
  84  * current task into the new thread.
  85  */
  86 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  87 {
  88         memcpy(dst, src, arch_task_struct_size);
  89 #ifdef CONFIG_VM86
  90         dst->thread.vm86 = NULL;
  91 #endif
  92
  93         return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
  94 }
  95
  96 /*
  97  * Free current thread data structures etc..
  98  */
  99 void exit_thread(struct task_struct *tsk)
 100 {
 101         struct thread_struct *t = &tsk->thread;
 102         unsigned long *bp = t->io_bitmap_ptr;
 103         struct fpu *fpu = &t->fpu;
 104
 105         if (bp) {
 106                 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
 107
 108                 t->io_bitmap_ptr = NULL;
 109                 clear_thread_flag(TIF_IO_BITMAP);
 110                 /*
 111                  * Careful, clear this in the TSS too:
 112                  */
 113                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
 114                 t->io_bitmap_max = 0;
 115                 put_cpu();
 116                 kfree(bp);
 117         }
 118
 119         free_vm86(t);
 120
 121         fpu__drop(fpu);
 122 }
 123
 124 void flush_thread(void)
 125 {
 126         struct task_struct *tsk = current;
 127
 128         flush_ptrace_hw_breakpoint(tsk);
 129         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 130
 131         fpu__clear(&tsk->thread.fpu);
 132 }
 133
 134 void disable_TSC(void)
 135 {
 136         preempt_disable();
 137         if (!test_and_set_thread_flag(TIF_NOTSC))
 138                 /*
 139                  * Must flip the CPU state synchronously with
 140                  * TIF_NOTSC in the current running context.
 141                  */
 142                 cr4_set_bits(X86_CR4_TSD);
 143         preempt_enable();
 144 }
 145
 146 static void enable_TSC(void)
 147 {
 148         preempt_disable();
 149         if (test_and_clear_thread_flag(TIF_NOTSC))
 150                 /*
 151                  * Must flip the CPU state synchronously with
 152                  * TIF_NOTSC in the current running context.
 153                  */
 154                 cr4_clear_bits(X86_CR4_TSD);
 155         preempt_enable();
 156 }
 157
 158 int get_tsc_mode(unsigned long adr)
 159 {
 160         unsigned int val;
 161
 162         if (test_thread_flag(TIF_NOTSC))
 163                 val = PR_TSC_SIGSEGV;
 164         else
 165                 val = PR_TSC_ENABLE;
 166
 167         return put_user(val, (unsigned int __user *)adr);
 168 }
 169
 170 int set_tsc_mode(unsigned int val)
 171 {
 172         if (val == PR_TSC_SIGSEGV)
 173                 disable_TSC();
 174         else if (val == PR_TSC_ENABLE)
 175                 enable_TSC();
 176         else
 177                 return -EINVAL;
 178
 179         return 0;
 180 }
 181
 182 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
 183
 184 static void set_cpuid_faulting(bool on)
 185 {
 186         u64 msrval;
 187
 188         msrval = this_cpu_read(msr_misc_features_shadow);
 189         msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
 190         msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
 191         this_cpu_write(msr_misc_features_shadow, msrval);
 192         wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
 193 }
 194
 195 static void disable_cpuid(void)
 196 {
 197         preempt_disable();
 198         if (!test_and_set_thread_flag(TIF_NOCPUID)) {
 199                 /*
 200                  * Must flip the CPU state synchronously with
 201                  * TIF_NOCPUID in the current running context.
 202                  */
 203                 set_cpuid_faulting(true);
 204         }
 205         preempt_enable();
 206 }
 207
 208 static void enable_cpuid(void)
 209 {
 210         preempt_disable();
 211         if (test_and_clear_thread_flag(TIF_NOCPUID)) {
 212                 /*
 213                  * Must flip the CPU state synchronously with
 214                  * TIF_NOCPUID in the current running context.
 215                  */
 216                 set_cpuid_faulting(false);
 217         }
 218         preempt_enable();
 219 }
 220
 221 static int get_cpuid_mode(void)
 222 {
 223         return !test_thread_flag(TIF_NOCPUID);
 224 }
 225
 226 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
 227 {
 228         if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
 229                 return -ENODEV;
 230
 231         if (cpuid_enabled)
 232                 enable_cpuid();
 233         else
 234                 disable_cpuid();
 235
 236         return 0;
 237 }
 238
 239 /*
 240  * Called immediately after a successful exec.
 241  */
 242 void arch_setup_new_exec(void)
 243 {
 244         /* If cpuid was previously disabled for this task, re-enable it. */
 245         if (test_thread_flag(TIF_NOCPUID))
 246                 enable_cpuid();
 247 }
 248
 249 static inline void switch_to_bitmap(struct tss_struct *tss,
 250                                     struct thread_struct *prev,
 251                                     struct thread_struct *next,
 252                                     unsigned long tifp, unsigned long tifn)
 253 {
 254         if (tifn & _TIF_IO_BITMAP) {
 255                 /*
 256                  * Copy the relevant range of the IO bitmap.
 257                  * Normally this is 128 bytes or less:
 258                  */
 259                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 260                        max(prev->io_bitmap_max, next->io_bitmap_max));
 261                 /*
 262                  * Make sure that the TSS limit is correct for the CPU
 263                  * to notice the IO bitmap.
 264                  */
 265                 refresh_tss_limit();
 266         } else if (tifp & _TIF_IO_BITMAP) {
 267                 /*
 268                  * Clear any possible leftover bits:
 269                  */
 270                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 271         }
 272 }
 273
 274 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 275                       struct tss_struct *tss)
 276 {
 277         struct thread_struct *prev, *next;
 278         unsigned long tifp, tifn;
 279
 280         prev = &prev_p->thread;
 281         next = &next_p->thread;
 282
 283         tifn = READ_ONCE(task_thread_info(next_p)->flags);
 284         tifp = READ_ONCE(task_thread_info(prev_p)->flags);
 285         switch_to_bitmap(tss, prev, next, tifp, tifn);
 286
 287         propagate_user_return_notify(prev_p, next_p);
 288
 289         if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
 290             arch_has_block_step()) {
 291                 unsigned long debugctl, msk;
 292
 293                 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 294                 debugctl &= ~DEBUGCTLMSR_BTF;
 295                 msk = tifn & _TIF_BLOCKSTEP;
 296                 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
 297                 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 298         }
 299
 300         if ((tifp ^ tifn) & _TIF_NOTSC)
 301                 cr4_toggle_bits(X86_CR4_TSD);
 302
 303         if ((tifp ^ tifn) & _TIF_NOCPUID)
 304                 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
 305 }
 306
 307 /*
 308  * Idle related variables and functions
 309  */
 310 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
 311 EXPORT_SYMBOL(boot_option_idle_override);
 312
 313 static void (*x86_idle)(void);
 314
 315 #ifndef CONFIG_SMP
 316 static inline void play_dead(void)
 317 {
 318         BUG();
 319 }
 320 #endif
 321
 322 void arch_cpu_idle_enter(void)
 323 {
 324         tsc_verify_tsc_adjust(false);
 325         local_touch_nmi();
 326 }
 327
 328 void arch_cpu_idle_dead(void)
 329 {
 330         play_dead();
 331 }
 332
 333 /*
 334  * Called from the generic idle code.
 335  */
 336 void arch_cpu_idle(void)
 337 {
 338         x86_idle();
 339 }
 340
 341 /*
 342  * We use this if we don't have any better idle routine..
 343  */
 344 void __cpuidle default_idle(void)
 345 {
 346         trace_cpu_idle_rcuidle(1, smp_processor_id());
 347         safe_halt();
 348         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 349 }
 350 #ifdef CONFIG_APM_MODULE
 351 EXPORT_SYMBOL(default_idle);
 352 #endif
 353
 354 #ifdef CONFIG_XEN
 355 bool xen_set_default_idle(void)
 356 {
 357         bool ret = !!x86_idle;
 358
 359         x86_idle = default_idle;
 360
 361         return ret;
 362 }
 363 #endif
 364 void stop_this_cpu(void *dummy)
 365 {
 366         local_irq_disable();
 367         /*
 368          * Remove this CPU:
 369          */
 370         set_cpu_online(smp_processor_id(), false);
 371         disable_local_APIC();
 372         mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
 373
 374         for (;;)
 375                 halt();
 376 }
 377
 378 /*
 379  * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
 380  * states (local apic timer and TSC stop).
 381  */
 382 static void amd_e400_idle(void)
 383 {
 384         /*
 385          * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
 386          * gets set after static_cpu_has() places have been converted via
 387          * alternatives.
 388          */
 389         if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 390                 default_idle();
 391                 return;
 392         }
 393
 394         tick_broadcast_enter();
 395
 396         default_idle();
 397
 398         /*
 399          * The switch back from broadcast mode needs to be called with
 400          * interrupts disabled.
 401          */
 402         local_irq_disable();
 403         tick_broadcast_exit();
 404         local_irq_enable();
 405 }
 406
 407 /*
 408  * Intel Core2 and older machines prefer MWAIT over HALT for C1.
 409  * We can't rely on cpuidle installing MWAIT, because it will not load
 410  * on systems that support only C1 -- so the boot default must be MWAIT.
 411  *
 412  * Some AMD machines are the opposite, they depend on using HALT.
 413  *
 414  * So for default C1, which is used during boot until cpuidle loads,
 415  * use MWAIT-C1 on Intel HW that has it, else use HALT.
 416  */
 417 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
 418 {
 419         if (c->x86_vendor != X86_VENDOR_INTEL)
 420                 return 0;
 421
 422         if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
 423                 return 0;
 424
 425         return 1;
 426 }
 427
 428 /*
 429  * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
 430  * with interrupts enabled and no flags, which is backwards compatible with the
 431  * original MWAIT implementation.
 432  */
 433 static __cpuidle void mwait_idle(void)
 434 {
 435         if (!current_set_polling_and_test()) {
 436                 trace_cpu_idle_rcuidle(1, smp_processor_id());
 437                 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
 438                         mb(); /* quirk */
 439                         clflush((void *)&current_thread_info()->flags);
 440                         mb(); /* quirk */
 441                 }
 442
 443                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 444                 if (!need_resched())
 445                         __sti_mwait(0, 0);
 446                 else
 447                         local_irq_enable();
 448                 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 449         } else {
 450                 local_irq_enable();
 451         }
 452         __current_clr_polling();
 453 }
 454
 455 void select_idle_routine(const struct cpuinfo_x86 *c)
 456 {
 457 #ifdef CONFIG_SMP
 458         if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
 459                 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 460 #endif
 461         if (x86_idle || boot_option_idle_override == IDLE_POLL)
 462                 return;
 463
 464         if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
 465                 pr_info("using AMD E400 aware idle routine\n");
 466                 x86_idle = amd_e400_idle;
 467         } else if (prefer_mwait_c1_over_halt(c)) {
 468                 pr_info("using mwait in idle threads\n");
 469                 x86_idle = mwait_idle;
 470         } else
 471                 x86_idle = default_idle;
 472 }
 473
 474 void amd_e400_c1e_apic_setup(void)
 475 {
 476         if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 477                 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
 478                 local_irq_disable();
 479                 tick_broadcast_force();
 480                 local_irq_enable();
 481         }
 482 }
 483
 484 void __init arch_post_acpi_subsys_init(void)
 485 {
 486         u32 lo, hi;
 487
 488         if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
 489                 return;
 490
 491         /*
 492          * AMD E400 detection needs to happen after ACPI has been enabled. If
 493          * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
 494          * MSR_K8_INT_PENDING_MSG.
 495          */
 496         rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 497         if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
 498                 return;
 499
 500         boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
 501
 502         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 503                 mark_tsc_unstable("TSC halt in AMD C1E");
 504         pr_info("System has AMD C1E enabled\n");
 505 }
 506
 507 static int __init idle_setup(char *str)
 508 {
 509         if (!str)
 510                 return -EINVAL;
 511
 512         if (!strcmp(str, "poll")) {
 513                 pr_info("using polling idle threads\n");
 514                 boot_option_idle_override = IDLE_POLL;
 515                 cpu_idle_poll_ctrl(true);
 516         } else if (!strcmp(str, "halt")) {
 517                 /*
 518                  * When the boot option of idle=halt is added, halt is
 519                  * forced to be used for CPU idle. In such case CPU C2/C3
 520                  * won't be used again.
 521                  * To continue to load the CPU idle driver, don't touch
 522                  * the boot_option_idle_override.
 523                  */
 524                 x86_idle = default_idle;
 525                 boot_option_idle_override = IDLE_HALT;
 526         } else if (!strcmp(str, "nomwait")) {
 527                 /*
 528                  * If the boot option of "idle=nomwait" is added,
 529                  * it means that mwait will be disabled for CPU C2/C3
 530                  * states. In such case it won't touch the variable
 531                  * of boot_option_idle_override.
 532                  */
 533                 boot_option_idle_override = IDLE_NOMWAIT;
 534         } else
 535                 return -1;
 536
 537         return 0;
 538 }
 539 early_param("idle", idle_setup);
 540
 541 unsigned long arch_align_stack(unsigned long sp)
 542 {
 543         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 544                 sp -= get_random_int() % 8192;
 545         return sp & ~0xf;
 546 }
 547
 548 unsigned long arch_randomize_brk(struct mm_struct *mm)
 549 {
 550         return randomize_page(mm->brk, 0x02000000);
 551 }
 552
 553 /*
 554  * Called from fs/proc with a reference on @p to find the function
 555  * which called into schedule(). This needs to be done carefully
 556  * because the task might wake up and we might look at a stack
 557  * changing under us.
 558  */
 559 unsigned long get_wchan(struct task_struct *p)
 560 {
 561         unsigned long start, bottom, top, sp, fp, ip, ret = 0;
 562         int count = 0;
 563
 564         if (!p || p == current || p->state == TASK_RUNNING)
 565                 return 0;
 566
 567         if (!try_get_task_stack(p))
 568                 return 0;
 569
 570         start = (unsigned long)task_stack_page(p);
 571         if (!start)
 572                 goto out;
 573
 574         /*
 575          * Layout of the stack page:
 576          *
 577          * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
 578          * PADDING
 579          * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
 580          * stack
 581          * ----------- bottom = start
 582          *
 583          * The tasks stack pointer points at the location where the
 584          * framepointer is stored. The data on the stack is:
 585          * ... IP FP ... IP FP
 586          *
 587          * We need to read FP and IP, so we need to adjust the upper
 588          * bound by another unsigned long.
 589          */
 590         top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
 591         top -= 2 * sizeof(unsigned long);
 592         bottom = start;
 593
 594         sp = READ_ONCE(p->thread.sp);
 595         if (sp < bottom || sp > top)
 596                 goto out;
 597
 598         fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
 599         do {
 600                 if (fp < bottom || fp > top)
 601                         goto out;
 602                 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
 603                 if (!in_sched_functions(ip)) {
 604                         ret = ip;
 605                         goto out;
 606                 }
 607                 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
 608         } while (count++ < 16 && p->state != TASK_RUNNING);
 609
 610 out:
 611         put_task_stack(p);
 612         return ret;
 613 }
 614
 615 long do_arch_prctl_common(struct task_struct *task, int option,
 616                           unsigned long cpuid_enabled)
 617 {
 618         switch (option) {
 619         case ARCH_GET_CPUID:
 620                 return get_cpuid_mode();
 621         case ARCH_SET_CPUID:
 622                 return set_cpuid_mode(task, cpuid_enabled);
 623         }
 624
 625         return -EINVAL;
 626 }