arch/x86/kernel/process.c

   1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   2
   3 #include <linux/errno.h>
   4 #include <linux/kernel.h>
   5 #include <linux/mm.h>
   6 #include <linux/smp.h>
   7 #include <linux/prctl.h>
   8 #include <linux/slab.h>
   9 #include <linux/sched.h>
  10 #include <linux/sched/idle.h>
  11 #include <linux/sched/debug.h>
  12 #include <linux/sched/task.h>
  13 #include <linux/sched/task_stack.h>
  14 #include <linux/init.h>
  15 #include <linux/export.h>
  16 #include <linux/pm.h>
  17 #include <linux/tick.h>
  18 #include <linux/random.h>
  19 #include <linux/user-return-notifier.h>
  20 #include <linux/dmi.h>
  21 #include <linux/utsname.h>
  22 #include <linux/stackprotector.h>
  23 #include <linux/tick.h>
  24 #include <linux/cpuidle.h>
  25 #include <trace/events/power.h>
  26 #include <linux/hw_breakpoint.h>
  27 #include <asm/cpu.h>
  28 #include <asm/apic.h>
  29 #include <asm/syscalls.h>
  30 #include <linux/uaccess.h>
  31 #include <asm/mwait.h>
  32 #include <asm/fpu/internal.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/nmi.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/mce.h>
  37 #include <asm/vm86.h>
  38 #include <asm/switch_to.h>
  39 #include <asm/desc.h>
  40 #include <asm/prctl.h>
  41
  42 /*
  43  * per-CPU TSS segments. Threads are completely 'soft' on Linux,
  44  * no more per-task TSS's. The TSS size is kept cacheline-aligned
  45  * so they are allowed to end up in the .data..cacheline_aligned
  46  * section. Since TSS's are completely CPU-local, we want them
  47  * on exact cacheline boundaries, to eliminate cacheline ping-pong.
  48  */
  49 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
  50         .x86_tss = {
  51                 /*
  52                  * .sp0 is only used when entering ring 0 from a lower
  53                  * privilege level.  Since the init task never runs anything
  54                  * but ring 0 code, there is no need for a valid value here.
  55                  * Poison it.
  56                  */
  57                 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
  58 #ifdef CONFIG_X86_32
  59                 .ss0 = __KERNEL_DS,
  60                 .ss1 = __KERNEL_CS,
  61                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
  62 #endif
  63          },
  64 #ifdef CONFIG_X86_32
  65          /*
  66           * Note that the .io_bitmap member must be extra-big. This is because
  67           * the CPU will access an additional byte beyond the end of the IO
  68           * permission bitmap. The extra byte must be all 1 bits, and must
  69           * be within the limit.
  70           */
  71         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },
  72 #endif
  73         .SYSENTER_stack_canary  = STACK_END_MAGIC,
  74 };
  75 EXPORT_PER_CPU_SYMBOL(cpu_tss);
  76
  77 DEFINE_PER_CPU(bool, __tss_limit_invalid);
  78 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
  79
  80 /*
  81  * this gets called so that we can store lazy state into memory and copy the
  82  * current task into the new thread.
  83  */
  84 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  85 {
  86         memcpy(dst, src, arch_task_struct_size);
  87 #ifdef CONFIG_VM86
  88         dst->thread.vm86 = NULL;
  89 #endif
  90
  91         return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
  92 }
  93
  94 /*
  95  * Free current thread data structures etc..
  96  */
  97 void exit_thread(struct task_struct *tsk)
  98 {
  99         struct thread_struct *t = &tsk->thread;
 100         unsigned long *bp = t->io_bitmap_ptr;
 101         struct fpu *fpu = &t->fpu;
 102
 103         if (bp) {
 104                 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
 105
 106                 t->io_bitmap_ptr = NULL;
 107                 clear_thread_flag(TIF_IO_BITMAP);
 108                 /*
 109                  * Careful, clear this in the TSS too:
 110                  */
 111                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
 112                 t->io_bitmap_max = 0;
 113                 put_cpu();
 114                 kfree(bp);
 115         }
 116
 117         free_vm86(t);
 118
 119         fpu__drop(fpu);
 120 }
 121
 122 void flush_thread(void)
 123 {
 124         struct task_struct *tsk = current;
 125
 126         flush_ptrace_hw_breakpoint(tsk);
 127         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 128
 129         fpu__clear(&tsk->thread.fpu);
 130 }
 131
 132 void disable_TSC(void)
 133 {
 134         preempt_disable();
 135         if (!test_and_set_thread_flag(TIF_NOTSC))
 136                 /*
 137                  * Must flip the CPU state synchronously with
 138                  * TIF_NOTSC in the current running context.
 139                  */
 140                 cr4_set_bits(X86_CR4_TSD);
 141         preempt_enable();
 142 }
 143
 144 static void enable_TSC(void)
 145 {
 146         preempt_disable();
 147         if (test_and_clear_thread_flag(TIF_NOTSC))
 148                 /*
 149                  * Must flip the CPU state synchronously with
 150                  * TIF_NOTSC in the current running context.
 151                  */
 152                 cr4_clear_bits(X86_CR4_TSD);
 153         preempt_enable();
 154 }
 155
 156 int get_tsc_mode(unsigned long adr)
 157 {
 158         unsigned int val;
 159
 160         if (test_thread_flag(TIF_NOTSC))
 161                 val = PR_TSC_SIGSEGV;
 162         else
 163                 val = PR_TSC_ENABLE;
 164
 165         return put_user(val, (unsigned int __user *)adr);
 166 }
 167
 168 int set_tsc_mode(unsigned int val)
 169 {
 170         if (val == PR_TSC_SIGSEGV)
 171                 disable_TSC();
 172         else if (val == PR_TSC_ENABLE)
 173                 enable_TSC();
 174         else
 175                 return -EINVAL;
 176
 177         return 0;
 178 }
 179
 180 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
 181
 182 static void set_cpuid_faulting(bool on)
 183 {
 184         u64 msrval;
 185
 186         msrval = this_cpu_read(msr_misc_features_shadow);
 187         msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
 188         msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
 189         this_cpu_write(msr_misc_features_shadow, msrval);
 190         wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
 191 }
 192
 193 static void disable_cpuid(void)
 194 {
 195         preempt_disable();
 196         if (!test_and_set_thread_flag(TIF_NOCPUID)) {
 197                 /*
 198                  * Must flip the CPU state synchronously with
 199                  * TIF_NOCPUID in the current running context.
 200                  */
 201                 set_cpuid_faulting(true);
 202         }
 203         preempt_enable();
 204 }
 205
 206 static void enable_cpuid(void)
 207 {
 208         preempt_disable();
 209         if (test_and_clear_thread_flag(TIF_NOCPUID)) {
 210                 /*
 211                  * Must flip the CPU state synchronously with
 212                  * TIF_NOCPUID in the current running context.
 213                  */
 214                 set_cpuid_faulting(false);
 215         }
 216         preempt_enable();
 217 }
 218
 219 static int get_cpuid_mode(void)
 220 {
 221         return !test_thread_flag(TIF_NOCPUID);
 222 }
 223
 224 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
 225 {
 226         if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
 227                 return -ENODEV;
 228
 229         if (cpuid_enabled)
 230                 enable_cpuid();
 231         else
 232                 disable_cpuid();
 233
 234         return 0;
 235 }
 236
 237 /*
 238  * Called immediately after a successful exec.
 239  */
 240 void arch_setup_new_exec(void)
 241 {
 242         /* If cpuid was previously disabled for this task, re-enable it. */
 243         if (test_thread_flag(TIF_NOCPUID))
 244                 enable_cpuid();
 245 }
 246
 247 static inline void switch_to_bitmap(struct tss_struct *tss,
 248                                     struct thread_struct *prev,
 249                                     struct thread_struct *next,
 250                                     unsigned long tifp, unsigned long tifn)
 251 {
 252         if (tifn & _TIF_IO_BITMAP) {
 253                 /*
 254                  * Copy the relevant range of the IO bitmap.
 255                  * Normally this is 128 bytes or less:
 256                  */
 257                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 258                        max(prev->io_bitmap_max, next->io_bitmap_max));
 259                 /*
 260                  * Make sure that the TSS limit is correct for the CPU
 261                  * to notice the IO bitmap.
 262                  */
 263                 refresh_tss_limit();
 264         } else if (tifp & _TIF_IO_BITMAP) {
 265                 /*
 266                  * Clear any possible leftover bits:
 267                  */
 268                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 269         }
 270 }
 271
 272 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 273                       struct tss_struct *tss)
 274 {
 275         struct thread_struct *prev, *next;
 276         unsigned long tifp, tifn;
 277
 278         prev = &prev_p->thread;
 279         next = &next_p->thread;
 280
 281         tifn = READ_ONCE(task_thread_info(next_p)->flags);
 282         tifp = READ_ONCE(task_thread_info(prev_p)->flags);
 283         switch_to_bitmap(tss, prev, next, tifp, tifn);
 284
 285         propagate_user_return_notify(prev_p, next_p);
 286
 287         if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
 288             arch_has_block_step()) {
 289                 unsigned long debugctl, msk;
 290
 291                 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 292                 debugctl &= ~DEBUGCTLMSR_BTF;
 293                 msk = tifn & _TIF_BLOCKSTEP;
 294                 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
 295                 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 296         }
 297
 298         if ((tifp ^ tifn) & _TIF_NOTSC)
 299                 cr4_toggle_bits(X86_CR4_TSD);
 300
 301         if ((tifp ^ tifn) & _TIF_NOCPUID)
 302                 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
 303 }
 304
 305 /*
 306  * Idle related variables and functions
 307  */
 308 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
 309 EXPORT_SYMBOL(boot_option_idle_override);
 310
 311 static void (*x86_idle)(void);
 312
 313 #ifndef CONFIG_SMP
 314 static inline void play_dead(void)
 315 {
 316         BUG();
 317 }
 318 #endif
 319
 320 void arch_cpu_idle_enter(void)
 321 {
 322         tsc_verify_tsc_adjust(false);
 323         local_touch_nmi();
 324 }
 325
 326 void arch_cpu_idle_dead(void)
 327 {
 328         play_dead();
 329 }
 330
 331 /*
 332  * Called from the generic idle code.
 333  */
 334 void arch_cpu_idle(void)
 335 {
 336         x86_idle();
 337 }
 338
 339 /*
 340  * We use this if we don't have any better idle routine..
 341  */
 342 void __cpuidle default_idle(void)
 343 {
 344         trace_cpu_idle_rcuidle(1, smp_processor_id());
 345         safe_halt();
 346         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 347 }
 348 #ifdef CONFIG_APM_MODULE
 349 EXPORT_SYMBOL(default_idle);
 350 #endif
 351
 352 #ifdef CONFIG_XEN
 353 bool xen_set_default_idle(void)
 354 {
 355         bool ret = !!x86_idle;
 356
 357         x86_idle = default_idle;
 358
 359         return ret;
 360 }
 361 #endif
 362 void stop_this_cpu(void *dummy)
 363 {
 364         local_irq_disable();
 365         /*
 366          * Remove this CPU:
 367          */
 368         set_cpu_online(smp_processor_id(), false);
 369         disable_local_APIC();
 370         mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
 371
 372         for (;;)
 373                 halt();
 374 }
 375
 376 /*
 377  * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
 378  * states (local apic timer and TSC stop).
 379  */
 380 static void amd_e400_idle(void)
 381 {
 382         /*
 383          * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
 384          * gets set after static_cpu_has() places have been converted via
 385          * alternatives.
 386          */
 387         if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 388                 default_idle();
 389                 return;
 390         }
 391
 392         tick_broadcast_enter();
 393
 394         default_idle();
 395
 396         /*
 397          * The switch back from broadcast mode needs to be called with
 398          * interrupts disabled.
 399          */
 400         local_irq_disable();
 401         tick_broadcast_exit();
 402         local_irq_enable();
 403 }
 404
 405 /*
 406  * Intel Core2 and older machines prefer MWAIT over HALT for C1.
 407  * We can't rely on cpuidle installing MWAIT, because it will not load
 408  * on systems that support only C1 -- so the boot default must be MWAIT.
 409  *
 410  * Some AMD machines are the opposite, they depend on using HALT.
 411  *
 412  * So for default C1, which is used during boot until cpuidle loads,
 413  * use MWAIT-C1 on Intel HW that has it, else use HALT.
 414  */
 415 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
 416 {
 417         if (c->x86_vendor != X86_VENDOR_INTEL)
 418                 return 0;
 419
 420         if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
 421                 return 0;
 422
 423         return 1;
 424 }
 425
 426 /*
 427  * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
 428  * with interrupts enabled and no flags, which is backwards compatible with the
 429  * original MWAIT implementation.
 430  */
 431 static __cpuidle void mwait_idle(void)
 432 {
 433         if (!current_set_polling_and_test()) {
 434                 trace_cpu_idle_rcuidle(1, smp_processor_id());
 435                 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
 436                         mb(); /* quirk */
 437                         clflush((void *)&current_thread_info()->flags);
 438                         mb(); /* quirk */
 439                 }
 440
 441                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 442                 if (!need_resched())
 443                         __sti_mwait(0, 0);
 444                 else
 445                         local_irq_enable();
 446                 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 447         } else {
 448                 local_irq_enable();
 449         }
 450         __current_clr_polling();
 451 }
 452
 453 void select_idle_routine(const struct cpuinfo_x86 *c)
 454 {
 455 #ifdef CONFIG_SMP
 456         if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
 457                 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 458 #endif
 459         if (x86_idle || boot_option_idle_override == IDLE_POLL)
 460                 return;
 461
 462         if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
 463                 pr_info("using AMD E400 aware idle routine\n");
 464                 x86_idle = amd_e400_idle;
 465         } else if (prefer_mwait_c1_over_halt(c)) {
 466                 pr_info("using mwait in idle threads\n");
 467                 x86_idle = mwait_idle;
 468         } else
 469                 x86_idle = default_idle;
 470 }
 471
 472 void amd_e400_c1e_apic_setup(void)
 473 {
 474         if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 475                 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
 476                 local_irq_disable();
 477                 tick_broadcast_force();
 478                 local_irq_enable();
 479         }
 480 }
 481
 482 void __init arch_post_acpi_subsys_init(void)
 483 {
 484         u32 lo, hi;
 485
 486         if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
 487                 return;
 488
 489         /*
 490          * AMD E400 detection needs to happen after ACPI has been enabled. If
 491          * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
 492          * MSR_K8_INT_PENDING_MSG.
 493          */
 494         rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 495         if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
 496                 return;
 497
 498         boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
 499
 500         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 501                 mark_tsc_unstable("TSC halt in AMD C1E");
 502         pr_info("System has AMD C1E enabled\n");
 503 }
 504
 505 static int __init idle_setup(char *str)
 506 {
 507         if (!str)
 508                 return -EINVAL;
 509
 510         if (!strcmp(str, "poll")) {
 511                 pr_info("using polling idle threads\n");
 512                 boot_option_idle_override = IDLE_POLL;
 513                 cpu_idle_poll_ctrl(true);
 514         } else if (!strcmp(str, "halt")) {
 515                 /*
 516                  * When the boot option of idle=halt is added, halt is
 517                  * forced to be used for CPU idle. In such case CPU C2/C3
 518                  * won't be used again.
 519                  * To continue to load the CPU idle driver, don't touch
 520                  * the boot_option_idle_override.
 521                  */
 522                 x86_idle = default_idle;
 523                 boot_option_idle_override = IDLE_HALT;
 524         } else if (!strcmp(str, "nomwait")) {
 525                 /*
 526                  * If the boot option of "idle=nomwait" is added,
 527                  * it means that mwait will be disabled for CPU C2/C3
 528                  * states. In such case it won't touch the variable
 529                  * of boot_option_idle_override.
 530                  */
 531                 boot_option_idle_override = IDLE_NOMWAIT;
 532         } else
 533                 return -1;
 534
 535         return 0;
 536 }
 537 early_param("idle", idle_setup);
 538
 539 unsigned long arch_align_stack(unsigned long sp)
 540 {
 541         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 542                 sp -= get_random_int() % 8192;
 543         return sp & ~0xf;
 544 }
 545
 546 unsigned long arch_randomize_brk(struct mm_struct *mm)
 547 {
 548         return randomize_page(mm->brk, 0x02000000);
 549 }
 550
 551 /*
 552  * Called from fs/proc with a reference on @p to find the function
 553  * which called into schedule(). This needs to be done carefully
 554  * because the task might wake up and we might look at a stack
 555  * changing under us.
 556  */
 557 unsigned long get_wchan(struct task_struct *p)
 558 {
 559         unsigned long start, bottom, top, sp, fp, ip, ret = 0;
 560         int count = 0;
 561
 562         if (!p || p == current || p->state == TASK_RUNNING)
 563                 return 0;
 564
 565         if (!try_get_task_stack(p))
 566                 return 0;
 567
 568         start = (unsigned long)task_stack_page(p);
 569         if (!start)
 570                 goto out;
 571
 572         /*
 573          * Layout of the stack page:
 574          *
 575          * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
 576          * PADDING
 577          * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
 578          * stack
 579          * ----------- bottom = start
 580          *
 581          * The tasks stack pointer points at the location where the
 582          * framepointer is stored. The data on the stack is:
 583          * ... IP FP ... IP FP
 584          *
 585          * We need to read FP and IP, so we need to adjust the upper
 586          * bound by another unsigned long.
 587          */
 588         top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
 589         top -= 2 * sizeof(unsigned long);
 590         bottom = start;
 591
 592         sp = READ_ONCE(p->thread.sp);
 593         if (sp < bottom || sp > top)
 594                 goto out;
 595
 596         fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
 597         do {
 598                 if (fp < bottom || fp > top)
 599                         goto out;
 600                 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
 601                 if (!in_sched_functions(ip)) {
 602                         ret = ip;
 603                         goto out;
 604                 }
 605                 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
 606         } while (count++ < 16 && p->state != TASK_RUNNING);
 607
 608 out:
 609         put_task_stack(p);
 610         return ret;
 611 }
 612
 613 long do_arch_prctl_common(struct task_struct *task, int option,
 614                           unsigned long cpuid_enabled)
 615 {
 616         switch (option) {
 617         case ARCH_GET_CPUID:
 618                 return get_cpuid_mode();
 619         case ARCH_SET_CPUID:
 620                 return set_cpuid_mode(task, cpuid_enabled);
 621         }
 622
 623         return -EINVAL;
 624 }