arch/x86/kernel/process.c

   1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   2
   3 #include <linux/errno.h>
   4 #include <linux/kernel.h>
   5 #include <linux/mm.h>
   6 #include <linux/smp.h>
   7 #include <linux/prctl.h>
   8 #include <linux/slab.h>
   9 #include <linux/sched.h>
  10 #include <linux/module.h>
  11 #include <linux/pm.h>
  12 #include <linux/tick.h>
  13 #include <linux/random.h>
  14 #include <linux/user-return-notifier.h>
  15 #include <linux/dmi.h>
  16 #include <linux/utsname.h>
  17 #include <linux/stackprotector.h>
  18 #include <linux/tick.h>
  19 #include <linux/cpuidle.h>
  20 #include <trace/events/power.h>
  21 #include <linux/hw_breakpoint.h>
  22 #include <asm/cpu.h>
  23 #include <asm/apic.h>
  24 #include <asm/syscalls.h>
  25 #include <asm/idle.h>
  26 #include <asm/uaccess.h>
  27 #include <asm/mwait.h>
  28 #include <asm/i387.h>
  29 #include <asm/fpu-internal.h>
  30 #include <asm/debugreg.h>
  31 #include <asm/nmi.h>
  32 #include <asm/tlbflush.h>
  33
  34 /*
  35  * per-CPU TSS segments. Threads are completely 'soft' on Linux,
  36  * no more per-task TSS's. The TSS size is kept cacheline-aligned
  37  * so they are allowed to end up in the .data..cacheline_aligned
  38  * section. Since TSS's are completely CPU-local, we want them
  39  * on exact cacheline boundaries, to eliminate cacheline ping-pong.
  40  */
  41 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
  42         .x86_tss = {
  43                 .sp0 = TOP_OF_INIT_STACK,
  44 #ifdef CONFIG_X86_32
  45                 .ss0 = __KERNEL_DS,
  46                 .ss1 = __KERNEL_CS,
  47                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
  48 #endif
  49          },
  50 #ifdef CONFIG_X86_32
  51          /*
  52           * Note that the .io_bitmap member must be extra-big. This is because
  53           * the CPU will access an additional byte beyond the end of the IO
  54           * permission bitmap. The extra byte must be all 1 bits, and must
  55           * be within the limit.
  56           */
  57         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },
  58 #endif
  59 };
  60 EXPORT_PER_CPU_SYMBOL_GPL(cpu_tss);
  61
  62 #ifdef CONFIG_X86_64
  63 static DEFINE_PER_CPU(unsigned char, is_idle);
  64 static ATOMIC_NOTIFIER_HEAD(idle_notifier);
  65
  66 void idle_notifier_register(struct notifier_block *n)
  67 {
  68         atomic_notifier_chain_register(&idle_notifier, n);
  69 }
  70 EXPORT_SYMBOL_GPL(idle_notifier_register);
  71
  72 void idle_notifier_unregister(struct notifier_block *n)
  73 {
  74         atomic_notifier_chain_unregister(&idle_notifier, n);
  75 }
  76 EXPORT_SYMBOL_GPL(idle_notifier_unregister);
  77 #endif
  78
  79 struct kmem_cache *task_xstate_cachep;
  80 EXPORT_SYMBOL_GPL(task_xstate_cachep);
  81
  82 /*
  83  * this gets called so that we can store lazy state into memory and copy the
  84  * current task into the new thread.
  85  */
  86 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  87 {
  88         *dst = *src;
  89
  90         dst->thread.fpu_counter = 0;
  91         dst->thread.fpu.has_fpu = 0;
  92         dst->thread.fpu.last_cpu = ~0;
  93         dst->thread.fpu.state = NULL;
  94         if (tsk_used_math(src)) {
  95                 int err = fpu_alloc(&dst->thread.fpu);
  96                 if (err)
  97                         return err;
  98                 fpu_copy(dst, src);
  99         }
 100         return 0;
 101 }
 102
 103 void free_thread_xstate(struct task_struct *tsk)
 104 {
 105         fpu_free(&tsk->thread.fpu);
 106 }
 107
 108 void arch_release_task_struct(struct task_struct *tsk)
 109 {
 110         free_thread_xstate(tsk);
 111 }
 112
 113 void arch_task_cache_init(void)
 114 {
 115         task_xstate_cachep =
 116                 kmem_cache_create("task_xstate", xstate_size,
 117                                   __alignof__(union thread_xstate),
 118                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
 119         setup_xstate_comp();
 120 }
 121
 122 /*
 123  * Free current thread data structures etc..
 124  */
 125 void exit_thread(void)
 126 {
 127         struct task_struct *me = current;
 128         struct thread_struct *t = &me->thread;
 129         unsigned long *bp = t->io_bitmap_ptr;
 130
 131         if (bp) {
 132                 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
 133
 134                 t->io_bitmap_ptr = NULL;
 135                 clear_thread_flag(TIF_IO_BITMAP);
 136                 /*
 137                  * Careful, clear this in the TSS too:
 138                  */
 139                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
 140                 t->io_bitmap_max = 0;
 141                 put_cpu();
 142                 kfree(bp);
 143         }
 144
 145         drop_fpu(me);
 146 }
 147
 148 void flush_thread(void)
 149 {
 150         struct task_struct *tsk = current;
 151
 152         flush_ptrace_hw_breakpoint(tsk);
 153         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 154         drop_init_fpu(tsk);
 155         /*
 156          * Free the FPU state for non xsave platforms. They get reallocated
 157          * lazily at the first use.
 158          */
 159         if (!use_eager_fpu())
 160                 free_thread_xstate(tsk);
 161 }
 162
 163 static void hard_disable_TSC(void)
 164 {
 165         cr4_set_bits(X86_CR4_TSD);
 166 }
 167
 168 void disable_TSC(void)
 169 {
 170         preempt_disable();
 171         if (!test_and_set_thread_flag(TIF_NOTSC))
 172                 /*
 173                  * Must flip the CPU state synchronously with
 174                  * TIF_NOTSC in the current running context.
 175                  */
 176                 hard_disable_TSC();
 177         preempt_enable();
 178 }
 179
 180 static void hard_enable_TSC(void)
 181 {
 182         cr4_clear_bits(X86_CR4_TSD);
 183 }
 184
 185 static void enable_TSC(void)
 186 {
 187         preempt_disable();
 188         if (test_and_clear_thread_flag(TIF_NOTSC))
 189                 /*
 190                  * Must flip the CPU state synchronously with
 191                  * TIF_NOTSC in the current running context.
 192                  */
 193                 hard_enable_TSC();
 194         preempt_enable();
 195 }
 196
 197 int get_tsc_mode(unsigned long adr)
 198 {
 199         unsigned int val;
 200
 201         if (test_thread_flag(TIF_NOTSC))
 202                 val = PR_TSC_SIGSEGV;
 203         else
 204                 val = PR_TSC_ENABLE;
 205
 206         return put_user(val, (unsigned int __user *)adr);
 207 }
 208
 209 int set_tsc_mode(unsigned int val)
 210 {
 211         if (val == PR_TSC_SIGSEGV)
 212                 disable_TSC();
 213         else if (val == PR_TSC_ENABLE)
 214                 enable_TSC();
 215         else
 216                 return -EINVAL;
 217
 218         return 0;
 219 }
 220
 221 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 222                       struct tss_struct *tss)
 223 {
 224         struct thread_struct *prev, *next;
 225
 226         prev = &prev_p->thread;
 227         next = &next_p->thread;
 228
 229         if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
 230             test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
 231                 unsigned long debugctl = get_debugctlmsr();
 232
 233                 debugctl &= ~DEBUGCTLMSR_BTF;
 234                 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
 235                         debugctl |= DEBUGCTLMSR_BTF;
 236
 237                 update_debugctlmsr(debugctl);
 238         }
 239
 240         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 241             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 242                 /* prev and next are different */
 243                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 244                         hard_disable_TSC();
 245                 else
 246                         hard_enable_TSC();
 247         }
 248
 249         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 250                 /*
 251                  * Copy the relevant range of the IO bitmap.
 252                  * Normally this is 128 bytes or less:
 253                  */
 254                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 255                        max(prev->io_bitmap_max, next->io_bitmap_max));
 256         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 257                 /*
 258                  * Clear any possible leftover bits:
 259                  */
 260                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 261         }
 262         propagate_user_return_notify(prev_p, next_p);
 263 }
 264
 265 /*
 266  * Idle related variables and functions
 267  */
 268 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
 269 EXPORT_SYMBOL(boot_option_idle_override);
 270
 271 static void (*x86_idle)(void);
 272
 273 #ifndef CONFIG_SMP
 274 static inline void play_dead(void)
 275 {
 276         BUG();
 277 }
 278 #endif
 279
 280 #ifdef CONFIG_X86_64
 281 void enter_idle(void)
 282 {
 283         this_cpu_write(is_idle, 1);
 284         atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
 285 }
 286
 287 static void __exit_idle(void)
 288 {
 289         if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
 290                 return;
 291         atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
 292 }
 293
 294 /* Called from interrupts to signify idle end */
 295 void exit_idle(void)
 296 {
 297         /* idle loop has pid 0 */
 298         if (current->pid)
 299                 return;
 300         __exit_idle();
 301 }
 302 #endif
 303
 304 void arch_cpu_idle_enter(void)
 305 {
 306         local_touch_nmi();
 307         enter_idle();
 308 }
 309
 310 void arch_cpu_idle_exit(void)
 311 {
 312         __exit_idle();
 313 }
 314
 315 void arch_cpu_idle_dead(void)
 316 {
 317         play_dead();
 318 }
 319
 320 /*
 321  * Called from the generic idle code.
 322  */
 323 void arch_cpu_idle(void)
 324 {
 325         x86_idle();
 326 }
 327
 328 /*
 329  * We use this if we don't have any better idle routine..
 330  */
 331 void default_idle(void)
 332 {
 333         trace_cpu_idle_rcuidle(1, smp_processor_id());
 334         safe_halt();
 335         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 336 }
 337 #ifdef CONFIG_APM_MODULE
 338 EXPORT_SYMBOL(default_idle);
 339 #endif
 340
 341 #ifdef CONFIG_XEN
 342 bool xen_set_default_idle(void)
 343 {
 344         bool ret = !!x86_idle;
 345
 346         x86_idle = default_idle;
 347
 348         return ret;
 349 }
 350 #endif
 351 void stop_this_cpu(void *dummy)
 352 {
 353         local_irq_disable();
 354         /*
 355          * Remove this CPU:
 356          */
 357         set_cpu_online(smp_processor_id(), false);
 358         disable_local_APIC();
 359
 360         for (;;)
 361                 halt();
 362 }
 363
 364 bool amd_e400_c1e_detected;
 365 EXPORT_SYMBOL(amd_e400_c1e_detected);
 366
 367 static cpumask_var_t amd_e400_c1e_mask;
 368
 369 void amd_e400_remove_cpu(int cpu)
 370 {
 371         if (amd_e400_c1e_mask != NULL)
 372                 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
 373 }
 374
 375 /*
 376  * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
 377  * pending message MSR. If we detect C1E, then we handle it the same
 378  * way as C3 power states (local apic timer and TSC stop)
 379  */
 380 static void amd_e400_idle(void)
 381 {
 382         if (!amd_e400_c1e_detected) {
 383                 u32 lo, hi;
 384
 385                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 386
 387                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 388                         amd_e400_c1e_detected = true;
 389                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 390                                 mark_tsc_unstable("TSC halt in AMD C1E");
 391                         pr_info("System has AMD C1E enabled\n");
 392                 }
 393         }
 394
 395         if (amd_e400_c1e_detected) {
 396                 int cpu = smp_processor_id();
 397
 398                 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
 399                         cpumask_set_cpu(cpu, amd_e400_c1e_mask);
 400                         /* Force broadcast so ACPI can not interfere. */
 401                         tick_broadcast_force();
 402                         pr_info("Switch to broadcast mode on CPU%d\n", cpu);
 403                 }
 404                 tick_broadcast_enter();
 405
 406                 default_idle();
 407
 408                 /*
 409                  * The switch back from broadcast mode needs to be
 410                  * called with interrupts disabled.
 411                  */
 412                 local_irq_disable();
 413                 tick_broadcast_exit();
 414                 local_irq_enable();
 415         } else
 416                 default_idle();
 417 }
 418
 419 /*
 420  * Intel Core2 and older machines prefer MWAIT over HALT for C1.
 421  * We can't rely on cpuidle installing MWAIT, because it will not load
 422  * on systems that support only C1 -- so the boot default must be MWAIT.
 423  *
 424  * Some AMD machines are the opposite, they depend on using HALT.
 425  *
 426  * So for default C1, which is used during boot until cpuidle loads,
 427  * use MWAIT-C1 on Intel HW that has it, else use HALT.
 428  */
 429 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
 430 {
 431         if (c->x86_vendor != X86_VENDOR_INTEL)
 432                 return 0;
 433
 434         if (!cpu_has(c, X86_FEATURE_MWAIT))
 435                 return 0;
 436
 437         return 1;
 438 }
 439
 440 /*
 441  * MONITOR/MWAIT with no hints, used for default default C1 state.
 442  * This invokes MWAIT with interrutps enabled and no flags,
 443  * which is backwards compatible with the original MWAIT implementation.
 444  */
 445
 446 static void mwait_idle(void)
 447 {
 448         if (!current_set_polling_and_test()) {
 449                 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
 450                         smp_mb(); /* quirk */
 451                         clflush((void *)&current_thread_info()->flags);
 452                         smp_mb(); /* quirk */
 453                 }
 454
 455                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 456                 if (!need_resched())
 457                         __sti_mwait(0, 0);
 458                 else
 459                         local_irq_enable();
 460         } else {
 461                 local_irq_enable();
 462         }
 463         __current_clr_polling();
 464 }
 465
 466 void select_idle_routine(const struct cpuinfo_x86 *c)
 467 {
 468 #ifdef CONFIG_SMP
 469         if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
 470                 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 471 #endif
 472         if (x86_idle || boot_option_idle_override == IDLE_POLL)
 473                 return;
 474
 475         if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
 476                 /* E400: APIC timer interrupt does not wake up CPU from C1e */
 477                 pr_info("using AMD E400 aware idle routine\n");
 478                 x86_idle = amd_e400_idle;
 479         } else if (prefer_mwait_c1_over_halt(c)) {
 480                 pr_info("using mwait in idle threads\n");
 481                 x86_idle = mwait_idle;
 482         } else
 483                 x86_idle = default_idle;
 484 }
 485
 486 void __init init_amd_e400_c1e_mask(void)
 487 {
 488         /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
 489         if (x86_idle == amd_e400_idle)
 490                 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
 491 }
 492
 493 static int __init idle_setup(char *str)
 494 {
 495         if (!str)
 496                 return -EINVAL;
 497
 498         if (!strcmp(str, "poll")) {
 499                 pr_info("using polling idle threads\n");
 500                 boot_option_idle_override = IDLE_POLL;
 501                 cpu_idle_poll_ctrl(true);
 502         } else if (!strcmp(str, "halt")) {
 503                 /*
 504                  * When the boot option of idle=halt is added, halt is
 505                  * forced to be used for CPU idle. In such case CPU C2/C3
 506                  * won't be used again.
 507                  * To continue to load the CPU idle driver, don't touch
 508                  * the boot_option_idle_override.
 509                  */
 510                 x86_idle = default_idle;
 511                 boot_option_idle_override = IDLE_HALT;
 512         } else if (!strcmp(str, "nomwait")) {
 513                 /*
 514                  * If the boot option of "idle=nomwait" is added,
 515                  * it means that mwait will be disabled for CPU C2/C3
 516                  * states. In such case it won't touch the variable
 517                  * of boot_option_idle_override.
 518                  */
 519                 boot_option_idle_override = IDLE_NOMWAIT;
 520         } else
 521                 return -1;
 522
 523         return 0;
 524 }
 525 early_param("idle", idle_setup);
 526
 527 unsigned long arch_align_stack(unsigned long sp)
 528 {
 529         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 530                 sp -= get_random_int() % 8192;
 531         return sp & ~0xf;
 532 }
 533
 534 unsigned long arch_randomize_brk(struct mm_struct *mm)
 535 {
 536         unsigned long range_end = mm->brk + 0x02000000;
 537         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 538 }
 539